1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 9#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board_clk: xo-board-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <38400000>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32000>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a78c"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&l2_0>; 50 power-domains = <&cpu_pd0>; 51 power-domain-names = "psci"; 52 capacity-dmips-mhz = <1946>; 53 dynamic-power-coefficient = <472>; 54 55 l2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 next-level-cache = <&l3_0>; 60 }; 61 }; 62 63 cpu1: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a78c"; 66 reg = <0x0 0x100>; 67 enable-method = "psci"; 68 next-level-cache = <&l2_1>; 69 power-domains = <&cpu_pd1>; 70 power-domain-names = "psci"; 71 capacity-dmips-mhz = <1946>; 72 dynamic-power-coefficient = <472>; 73 74 l2_1: l2-cache { 75 compatible = "cache"; 76 cache-level = <2>; 77 cache-unified; 78 next-level-cache = <&l3_0>; 79 }; 80 }; 81 82 cpu2: cpu@200 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a78c"; 85 reg = <0x0 0x200>; 86 enable-method = "psci"; 87 next-level-cache = <&l2_2>; 88 power-domains = <&cpu_pd2>; 89 power-domain-names = "psci"; 90 capacity-dmips-mhz = <1946>; 91 dynamic-power-coefficient = <507>; 92 93 l2_2: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&l3_0>; 98 }; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a78c"; 104 reg = <0x0 0x300>; 105 enable-method = "psci"; 106 next-level-cache = <&l2_3>; 107 power-domains = <&cpu_pd3>; 108 power-domain-names = "psci"; 109 capacity-dmips-mhz = <1946>; 110 dynamic-power-coefficient = <507>; 111 112 l2_3: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-unified; 116 next-level-cache = <&l3_0>; 117 }; 118 }; 119 120 cpu4: cpu@10000 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a55"; 123 reg = <0x0 0x10000>; 124 enable-method = "psci"; 125 next-level-cache = <&l2_4>; 126 power-domains = <&cpu_pd4>; 127 power-domain-names = "psci"; 128 capacity-dmips-mhz = <1024>; 129 dynamic-power-coefficient = <100>; 130 131 l2_4: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&l3_1>; 136 }; 137 }; 138 139 cpu5: cpu@10100 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a55"; 142 reg = <0x0 0x10100>; 143 enable-method = "psci"; 144 next-level-cache = <&l2_5>; 145 power-domains = <&cpu_pd5>; 146 power-domain-names = "psci"; 147 capacity-dmips-mhz = <1024>; 148 dynamic-power-coefficient = <100>; 149 150 l2_5: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_1>; 155 }; 156 }; 157 158 cpu6: cpu@10200 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a55"; 161 reg = <0x0 0x10200>; 162 enable-method = "psci"; 163 next-level-cache = <&l2_6>; 164 power-domains = <&cpu_pd6>; 165 power-domain-names = "psci"; 166 capacity-dmips-mhz = <1024>; 167 dynamic-power-coefficient = <100>; 168 169 l2_6: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&l3_1>; 174 }; 175 }; 176 177 cpu7: cpu@10300 { 178 device_type = "cpu"; 179 compatible = "arm,cortex-a55"; 180 reg = <0x0 0x10300>; 181 enable-method = "psci"; 182 next-level-cache = <&l2_7>; 183 power-domains = <&cpu_pd7>; 184 power-domain-names = "psci"; 185 capacity-dmips-mhz = <1024>; 186 dynamic-power-coefficient = <100>; 187 188 l2_7: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&l3_1>; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&cpu0>; 200 }; 201 202 core1 { 203 cpu = <&cpu1>; 204 }; 205 206 core2 { 207 cpu = <&cpu2>; 208 }; 209 210 core3 { 211 cpu = <&cpu3>; 212 }; 213 }; 214 215 cluster1 { 216 core0 { 217 cpu = <&cpu4>; 218 }; 219 220 core1 { 221 cpu = <&cpu5>; 222 }; 223 224 core2 { 225 cpu = <&cpu6>; 226 }; 227 228 core3 { 229 cpu = <&cpu7>; 230 }; 231 }; 232 }; 233 234 l3_0: l3-cache-0 { 235 compatible = "cache"; 236 cache-level = <3>; 237 cache-unified; 238 }; 239 240 l3_1: l3-cache-1 { 241 compatible = "cache"; 242 cache-level = <3>; 243 cache-unified; 244 }; 245 246 idle-states { 247 entry-method = "psci"; 248 249 little_cpu_sleep_0: cpu-sleep-0-0 { 250 compatible = "arm,idle-state"; 251 idle-state-name = "silver-power-collapse"; 252 arm,psci-suspend-param = <0x40000003>; 253 entry-latency-us = <449>; 254 exit-latency-us = <801>; 255 min-residency-us = <1574>; 256 local-timer-stop; 257 }; 258 259 little_cpu_sleep_1: cpu-sleep-0-1 { 260 compatible = "arm,idle-state"; 261 idle-state-name = "silver-rail-power-collapse"; 262 arm,psci-suspend-param = <0x40000004>; 263 entry-latency-us = <602>; 264 exit-latency-us = <961>; 265 min-residency-us = <4288>; 266 local-timer-stop; 267 }; 268 269 big_cpu_sleep_0: cpu-sleep-1-0 { 270 compatible = "arm,idle-state"; 271 idle-state-name = "gold-power-collapse"; 272 arm,psci-suspend-param = <0x40000003>; 273 entry-latency-us = <549>; 274 exit-latency-us = <901>; 275 min-residency-us = <1774>; 276 local-timer-stop; 277 }; 278 279 big_cpu_sleep_1: cpu-sleep-1-1 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "gold-rail-power-collapse"; 282 arm,psci-suspend-param = <0x40000004>; 283 entry-latency-us = <702>; 284 exit-latency-us = <1061>; 285 min-residency-us = <4488>; 286 local-timer-stop; 287 }; 288 }; 289 290 domain-idle-states { 291 silver_cluster_sleep: cluster-sleep-0 { 292 compatible = "domain-idle-state"; 293 arm,psci-suspend-param = <0x41000044>; 294 entry-latency-us = <2552>; 295 exit-latency-us = <2848>; 296 min-residency-us = <5908>; 297 }; 298 299 gold_cluster_sleep: cluster-sleep-1 { 300 compatible = "domain-idle-state"; 301 arm,psci-suspend-param = <0x41000044>; 302 entry-latency-us = <2752>; 303 exit-latency-us = <3048>; 304 min-residency-us = <6118>; 305 }; 306 307 system_sleep: domain-sleep { 308 compatible = "domain-idle-state"; 309 arm,psci-suspend-param = <0x42000144>; 310 entry-latency-us = <3263>; 311 exit-latency-us = <6562>; 312 min-residency-us = <9987>; 313 }; 314 }; 315 }; 316 317 dummy_eud: dummy-sink { 318 compatible = "arm,coresight-dummy-sink"; 319 320 in-ports { 321 port { 322 eud_in: endpoint { 323 remote-endpoint = <&swao_rep_out1>; 324 }; 325 }; 326 }; 327 }; 328 329 firmware { 330 scm: scm { 331 compatible = "qcom,scm-qcs8300", "qcom,scm"; 332 qcom,dload-mode = <&tcsr 0x13000>; 333 }; 334 }; 335 336 memory@80000000 { 337 device_type = "memory"; 338 /* We expect the bootloader to fill in the size */ 339 reg = <0x0 0x80000000 0x0 0x0>; 340 }; 341 342 clk_virt: interconnect-0 { 343 compatible = "qcom,qcs8300-clk-virt"; 344 #interconnect-cells = <2>; 345 qcom,bcm-voters = <&apps_bcm_voter>; 346 }; 347 348 mc_virt: interconnect-1 { 349 compatible = "qcom,qcs8300-mc-virt"; 350 #interconnect-cells = <2>; 351 qcom,bcm-voters = <&apps_bcm_voter>; 352 }; 353 354 pmu-a55 { 355 compatible = "arm,cortex-a55-pmu"; 356 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 357 }; 358 359 pmu-a78 { 360 compatible = "arm,cortex-a78-pmu"; 361 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 362 }; 363 364 psci { 365 compatible = "arm,psci-1.0"; 366 method = "smc"; 367 368 cpu_pd0: power-domain-cpu0 { 369 #power-domain-cells = <0>; 370 power-domains = <&cluster_pd0>; 371 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 372 }; 373 374 cpu_pd1: power-domain-cpu1 { 375 #power-domain-cells = <0>; 376 power-domains = <&cluster_pd0>; 377 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 378 }; 379 380 cpu_pd2: power-domain-cpu2 { 381 #power-domain-cells = <0>; 382 power-domains = <&cluster_pd0>; 383 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 384 }; 385 386 cpu_pd3: power-domain-cpu3 { 387 #power-domain-cells = <0>; 388 power-domains = <&cluster_pd0>; 389 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 390 }; 391 392 cpu_pd4: power-domain-cpu4 { 393 #power-domain-cells = <0>; 394 power-domains = <&cluster_pd1>; 395 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 396 }; 397 398 cpu_pd5: power-domain-cpu5 { 399 #power-domain-cells = <0>; 400 power-domains = <&cluster_pd1>; 401 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 402 }; 403 404 cpu_pd6: power-domain-cpu6 { 405 #power-domain-cells = <0>; 406 power-domains = <&cluster_pd1>; 407 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 408 }; 409 410 cpu_pd7: power-domain-cpu7 { 411 #power-domain-cells = <0>; 412 power-domains = <&cluster_pd1>; 413 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 414 }; 415 416 cluster_pd0: power-domain-cluster0 { 417 #power-domain-cells = <0>; 418 power-domains = <&system_pd>; 419 domain-idle-states = <&gold_cluster_sleep>; 420 }; 421 422 cluster_pd1: power-domain-cluster1 { 423 #power-domain-cells = <0>; 424 power-domains = <&system_pd>; 425 domain-idle-states = <&silver_cluster_sleep>; 426 }; 427 428 system_pd: power-domain-system { 429 #power-domain-cells = <0>; 430 domain-idle-states = <&system_sleep>; 431 }; 432 }; 433 434 reserved-memory { 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges; 438 439 aop_image_mem: aop-image-region@90800000 { 440 reg = <0x0 0x90800000 0x0 0x60000>; 441 no-map; 442 }; 443 444 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 445 compatible = "qcom,cmd-db"; 446 reg = <0x0 0x90860000 0x0 0x20000>; 447 no-map; 448 }; 449 450 smem_mem: smem@90900000 { 451 compatible = "qcom,smem"; 452 reg = <0x0 0x90900000 0x0 0x200000>; 453 no-map; 454 hwlocks = <&tcsr_mutex 3>; 455 }; 456 457 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 458 reg = <0x0 0x93b00000 0x0 0xf00000>; 459 no-map; 460 }; 461 462 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 463 reg = <0x0 0x94a00000 0x0 0x800000>; 464 no-map; 465 }; 466 467 camera_mem: camera-region@95200000 { 468 reg = <0x0 0x95200000 0x0 0x500000>; 469 no-map; 470 }; 471 472 adsp_mem: adsp-region@95c00000 { 473 no-map; 474 reg = <0x0 0x95c00000 0x0 0x1e00000>; 475 }; 476 477 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 478 reg = <0x0 0x97a00000 0x0 0x80000>; 479 no-map; 480 }; 481 482 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 483 reg = <0x0 0x97a80000 0x0 0x80000>; 484 no-map; 485 }; 486 487 gpdsp_mem: gpdsp-region@97b00000 { 488 reg = <0x0 0x97b00000 0x0 0x1e00000>; 489 no-map; 490 }; 491 492 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 493 reg = <0x0 0x99900000 0x0 0x80000>; 494 no-map; 495 }; 496 497 cdsp_mem: cdsp-region@99980000 { 498 reg = <0x0 0x99980000 0x0 0x1e00000>; 499 no-map; 500 }; 501 502 gpu_microcode_mem: gpu-microcode-region@9b780000 { 503 reg = <0x0 0x9b780000 0x0 0x2000>; 504 no-map; 505 }; 506 507 cvp_mem: cvp-region@9b782000 { 508 reg = <0x0 0x9b782000 0x0 0x700000>; 509 no-map; 510 }; 511 512 video_mem: video-region@9be82000 { 513 reg = <0x0 0x9be82000 0x0 0x700000>; 514 no-map; 515 }; 516 }; 517 518 smp2p-adsp { 519 compatible = "qcom,smp2p"; 520 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 521 IPCC_MPROC_SIGNAL_SMP2P 522 IRQ_TYPE_EDGE_RISING>; 523 mboxes = <&ipcc IPCC_CLIENT_LPASS 524 IPCC_MPROC_SIGNAL_SMP2P>; 525 526 qcom,smem = <443>, <429>; 527 qcom,local-pid = <0>; 528 qcom,remote-pid = <2>; 529 530 smp2p_adsp_in: slave-kernel { 531 qcom,entry-name = "slave-kernel"; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 }; 535 536 smp2p_adsp_out: master-kernel { 537 qcom,entry-name = "master-kernel"; 538 #qcom,smem-state-cells = <1>; 539 }; 540 }; 541 542 smp2p-cdsp { 543 compatible = "qcom,smp2p"; 544 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 545 IPCC_MPROC_SIGNAL_SMP2P 546 IRQ_TYPE_EDGE_RISING>; 547 mboxes = <&ipcc IPCC_CLIENT_CDSP 548 IPCC_MPROC_SIGNAL_SMP2P>; 549 550 qcom,smem = <94>, <432>; 551 qcom,local-pid = <0>; 552 qcom,remote-pid = <5>; 553 554 smp2p_cdsp_in: slave-kernel { 555 qcom,entry-name = "slave-kernel"; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 560 smp2p_cdsp_out: master-kernel { 561 qcom,entry-name = "master-kernel"; 562 #qcom,smem-state-cells = <1>; 563 }; 564 }; 565 566 smp2p-gpdsp { 567 compatible = "qcom,smp2p"; 568 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 569 IPCC_MPROC_SIGNAL_SMP2P 570 IRQ_TYPE_EDGE_RISING>; 571 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 572 IPCC_MPROC_SIGNAL_SMP2P>; 573 574 qcom,smem = <617>, <616>; 575 qcom,local-pid = <0>; 576 qcom,remote-pid = <17>; 577 578 smp2p_gpdsp_in: slave-kernel { 579 qcom,entry-name = "slave-kernel"; 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 }; 583 584 smp2p_gpdsp_out: master-kernel { 585 qcom,entry-name = "master-kernel"; 586 #qcom,smem-state-cells = <1>; 587 }; 588 }; 589 590 soc: soc@0 { 591 compatible = "simple-bus"; 592 ranges = <0 0 0 0 0x10 0>; 593 #address-cells = <2>; 594 #size-cells = <2>; 595 596 gcc: clock-controller@100000 { 597 compatible = "qcom,qcs8300-gcc"; 598 reg = <0x0 0x00100000 0x0 0xc7018>; 599 #clock-cells = <1>; 600 #reset-cells = <1>; 601 #power-domain-cells = <1>; 602 clocks = <&rpmhcc RPMH_CXO_CLK>, 603 <&sleep_clk>, 604 <0>, 605 <0>, 606 <0>, 607 <0>, 608 <0>, 609 <0>, 610 <0>, 611 <0>; 612 }; 613 614 ipcc: mailbox@408000 { 615 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 616 reg = <0x0 0x408000 0x0 0x1000>; 617 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-controller; 619 #interrupt-cells = <3>; 620 #mbox-cells = <2>; 621 }; 622 623 qfprom: efuse@784000 { 624 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 625 reg = <0x0 0x00784000 0x0 0x1200>; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 }; 629 630 qupv3_id_0: geniqup@9c0000 { 631 compatible = "qcom,geni-se-qup"; 632 reg = <0x0 0x9c0000 0x0 0x2000>; 633 ranges; 634 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 635 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 636 clock-names = "m-ahb", 637 "s-ahb"; 638 #address-cells = <2>; 639 #size-cells = <2>; 640 status = "disabled"; 641 642 uart7: serial@99c000 { 643 compatible = "qcom,geni-debug-uart"; 644 reg = <0x0 0x0099c000 0x0 0x4000>; 645 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 646 clock-names = "se"; 647 pinctrl-0 = <&qup_uart7_default>; 648 pinctrl-names = "default"; 649 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 650 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 651 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 653 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 654 interconnect-names = "qup-core", 655 "qup-config"; 656 status = "disabled"; 657 }; 658 }; 659 660 rng: rng@10d2000 { 661 compatible = "qcom,qcs8300-trng", "qcom,trng"; 662 reg = <0x0 0x010d2000 0x0 0x1000>; 663 }; 664 665 config_noc: interconnect@14c0000 { 666 compatible = "qcom,qcs8300-config-noc"; 667 reg = <0x0 0x014c0000 0x0 0x13080>; 668 #interconnect-cells = <2>; 669 qcom,bcm-voters = <&apps_bcm_voter>; 670 }; 671 672 system_noc: interconnect@1680000 { 673 compatible = "qcom,qcs8300-system-noc"; 674 reg = <0x0 0x01680000 0x0 0x15080>; 675 #interconnect-cells = <2>; 676 qcom,bcm-voters = <&apps_bcm_voter>; 677 }; 678 679 aggre1_noc: interconnect@16c0000 { 680 compatible = "qcom,qcs8300-aggre1-noc"; 681 reg = <0x0 0x016c0000 0x0 0x17080>; 682 #interconnect-cells = <2>; 683 qcom,bcm-voters = <&apps_bcm_voter>; 684 }; 685 686 aggre2_noc: interconnect@1700000 { 687 compatible = "qcom,qcs8300-aggre2-noc"; 688 reg = <0x0 0x01700000 0x0 0x1a080>; 689 #interconnect-cells = <2>; 690 qcom,bcm-voters = <&apps_bcm_voter>; 691 }; 692 693 pcie_anoc: interconnect@1760000 { 694 compatible = "qcom,qcs8300-pcie-anoc"; 695 reg = <0x0 0x01760000 0x0 0xc080>; 696 #interconnect-cells = <2>; 697 qcom,bcm-voters = <&apps_bcm_voter>; 698 }; 699 700 gpdsp_anoc: interconnect@1780000 { 701 compatible = "qcom,qcs8300-gpdsp-anoc"; 702 reg = <0x0 0x01780000 0x0 0xd080>; 703 #interconnect-cells = <2>; 704 qcom,bcm-voters = <&apps_bcm_voter>; 705 }; 706 707 mmss_noc: interconnect@17a0000 { 708 compatible = "qcom,qcs8300-mmss-noc"; 709 reg = <0x0 0x017a0000 0x0 0x40000>; 710 #interconnect-cells = <2>; 711 qcom,bcm-voters = <&apps_bcm_voter>; 712 }; 713 714 ufs_mem_hc: ufs@1d84000 { 715 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 716 reg = <0x0 0x01d84000 0x0 0x3000>; 717 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 718 phys = <&ufs_mem_phy>; 719 phy-names = "ufsphy"; 720 lanes-per-direction = <2>; 721 #reset-cells = <1>; 722 resets = <&gcc GCC_UFS_PHY_BCR>; 723 reset-names = "rst"; 724 725 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 726 required-opps = <&rpmhpd_opp_nom>; 727 728 iommus = <&apps_smmu 0x100 0x0>; 729 dma-coherent; 730 731 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 732 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 733 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 734 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 735 interconnect-names = "ufs-ddr", 736 "cpu-ufs"; 737 738 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 739 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 740 <&gcc GCC_UFS_PHY_AHB_CLK>, 741 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 742 <&rpmhcc RPMH_CXO_CLK>, 743 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 744 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 745 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 746 clock-names = "core_clk", 747 "bus_aggr_clk", 748 "iface_clk", 749 "core_clk_unipro", 750 "ref_clk", 751 "tx_lane0_sync_clk", 752 "rx_lane0_sync_clk", 753 "rx_lane1_sync_clk"; 754 freq-table-hz = <75000000 300000000>, 755 <0 0>, 756 <0 0>, 757 <75000000 300000000>, 758 <0 0>, 759 <0 0>, 760 <0 0>, 761 <0 0>; 762 qcom,ice = <&ice>; 763 status = "disabled"; 764 }; 765 766 ufs_mem_phy: phy@1d87000 { 767 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 768 reg = <0x0 0x01d87000 0x0 0xe10>; 769 /* 770 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 771 * enables the CXO clock to eDP *and* UFS PHY. 772 */ 773 clocks = <&rpmhcc RPMH_CXO_CLK>, 774 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 775 <&gcc GCC_EDP_REF_CLKREF_EN>; 776 clock-names = "ref", 777 "ref_aux", 778 "qref"; 779 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 780 781 resets = <&ufs_mem_hc 0>; 782 reset-names = "ufsphy"; 783 784 #phy-cells = <0>; 785 status = "disabled"; 786 }; 787 788 cryptobam: dma-controller@1dc4000 { 789 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 790 reg = <0x0 0x01dc4000 0x0 0x28000>; 791 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 792 #dma-cells = <1>; 793 qcom,ee = <0>; 794 qcom,controlled-remotely; 795 num-channels = <20>; 796 qcom,num-ees = <4>; 797 iommus = <&apps_smmu 0x480 0x00>, 798 <&apps_smmu 0x481 0x00>; 799 }; 800 801 crypto: crypto@1dfa000 { 802 compatible = "qcom,qcs8300-qce", "qcom,qce"; 803 reg = <0x0 0x01dfa000 0x0 0x6000>; 804 dmas = <&cryptobam 4>, <&cryptobam 5>; 805 dma-names = "rx", "tx"; 806 iommus = <&apps_smmu 0x480 0x00>, 807 <&apps_smmu 0x481 0x00>; 808 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 809 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 810 interconnect-names = "memory"; 811 }; 812 813 ice: crypto@1d88000 { 814 compatible = "qcom,qcs8300-inline-crypto-engine", 815 "qcom,inline-crypto-engine"; 816 reg = <0x0 0x01d88000 0x0 0x18000>; 817 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 818 }; 819 820 tcsr_mutex: hwlock@1f40000 { 821 compatible = "qcom,tcsr-mutex"; 822 reg = <0x0 0x01f40000 0x0 0x20000>; 823 #hwlock-cells = <1>; 824 }; 825 826 tcsr: syscon@1fc0000 { 827 compatible = "qcom,qcs8300-tcsr", "syscon"; 828 reg = <0x0 0x1fc0000 0x0 0x30000>; 829 }; 830 831 remoteproc_adsp: remoteproc@3000000 { 832 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 833 reg = <0x0 0x3000000 0x0 0x00100>; 834 835 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 836 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 837 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 838 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 839 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 840 interrupt-names = "wdog", 841 "fatal", 842 "ready", 843 "handover", 844 "stop-ack"; 845 846 clocks = <&rpmhcc RPMH_CXO_CLK>; 847 clock-names = "xo"; 848 849 power-domains = <&rpmhpd RPMHPD_LCX>, 850 <&rpmhpd RPMHPD_LMX>; 851 power-domain-names = "lcx", 852 "lmx"; 853 854 memory-region = <&adsp_mem>; 855 856 qcom,qmp = <&aoss_qmp>; 857 858 qcom,smem-states = <&smp2p_adsp_out 0>; 859 qcom,smem-state-names = "stop"; 860 861 status = "disabled"; 862 863 remoteproc_adsp_glink: glink-edge { 864 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 865 IPCC_MPROC_SIGNAL_GLINK_QMP 866 IRQ_TYPE_EDGE_RISING>; 867 mboxes = <&ipcc IPCC_CLIENT_LPASS 868 IPCC_MPROC_SIGNAL_GLINK_QMP>; 869 870 label = "lpass"; 871 qcom,remote-pid = <2>; 872 873 fastrpc { 874 compatible = "qcom,fastrpc"; 875 qcom,glink-channels = "fastrpcglink-apps-dsp"; 876 label = "adsp"; 877 memory-region = <&adsp_rpc_remote_heap_mem>; 878 qcom,vmids = <QCOM_SCM_VMID_LPASS 879 QCOM_SCM_VMID_ADSP_HEAP>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 883 compute-cb@3 { 884 compatible = "qcom,fastrpc-compute-cb"; 885 reg = <3>; 886 iommus = <&apps_smmu 0x2003 0x0>; 887 dma-coherent; 888 }; 889 890 compute-cb@4 { 891 compatible = "qcom,fastrpc-compute-cb"; 892 reg = <4>; 893 iommus = <&apps_smmu 0x2004 0x0>; 894 dma-coherent; 895 }; 896 897 compute-cb@5 { 898 compatible = "qcom,fastrpc-compute-cb"; 899 reg = <5>; 900 iommus = <&apps_smmu 0x2005 0x0>; 901 dma-coherent; 902 }; 903 }; 904 }; 905 }; 906 907 lpass_ag_noc: interconnect@3c40000 { 908 compatible = "qcom,qcs8300-lpass-ag-noc"; 909 reg = <0x0 0x03c40000 0x0 0x17200>; 910 #interconnect-cells = <2>; 911 qcom,bcm-voters = <&apps_bcm_voter>; 912 }; 913 914 stm@4002000 { 915 compatible = "arm,coresight-stm", "arm,primecell"; 916 reg = <0x0 0x04002000 0x0 0x1000>, 917 <0x0 0x16280000 0x0 0x180000>; 918 reg-names = "stm-base", 919 "stm-stimulus-base"; 920 921 clocks = <&aoss_qmp>; 922 clock-names = "apb_pclk"; 923 924 out-ports { 925 port { 926 stm_out: endpoint { 927 remote-endpoint = <&funnel0_in7>; 928 }; 929 }; 930 }; 931 }; 932 933 tpda@4004000 { 934 compatible = "qcom,coresight-tpda", "arm,primecell"; 935 reg = <0x0 0x04004000 0x0 0x1000>; 936 937 clocks = <&aoss_qmp>; 938 clock-names = "apb_pclk"; 939 940 in-ports { 941 #address-cells = <1>; 942 #size-cells = <0>; 943 944 port@1 { 945 reg = <1>; 946 947 qdss_tpda_in1: endpoint { 948 remote-endpoint = <&qdss_tpdm1_out>; 949 }; 950 }; 951 }; 952 953 out-ports { 954 port { 955 qdss_tpda_out: endpoint { 956 remote-endpoint = <&funnel0_in6>; 957 }; 958 }; 959 }; 960 }; 961 962 tpdm@400f000 { 963 compatible = "qcom,coresight-tpdm", "arm,primecell"; 964 reg = <0x0 0x0400f000 0x0 0x1000>; 965 966 clocks = <&aoss_qmp>; 967 clock-names = "apb_pclk"; 968 969 qcom,cmb-element-bits = <32>; 970 qcom,cmb-msrs-num = <32>; 971 972 out-ports { 973 port { 974 qdss_tpdm1_out: endpoint { 975 remote-endpoint = <&qdss_tpda_in1>; 976 }; 977 }; 978 }; 979 }; 980 981 funnel@4041000 { 982 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 983 reg = <0x0 0x04041000 0x0 0x1000>; 984 985 clocks = <&aoss_qmp>; 986 clock-names = "apb_pclk"; 987 988 in-ports { 989 #address-cells = <1>; 990 #size-cells = <0>; 991 992 port@6 { 993 reg = <6>; 994 995 funnel0_in6: endpoint { 996 remote-endpoint = <&qdss_tpda_out>; 997 }; 998 }; 999 1000 port@7 { 1001 reg = <7>; 1002 1003 funnel0_in7: endpoint { 1004 remote-endpoint = <&stm_out>; 1005 }; 1006 }; 1007 }; 1008 1009 out-ports { 1010 port { 1011 funnel0_out: endpoint { 1012 remote-endpoint = <&qdss_funnel_in0>; 1013 }; 1014 }; 1015 }; 1016 }; 1017 1018 funnel@4042000 { 1019 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1020 reg = <0x0 0x04042000 0x0 0x1000>; 1021 1022 clocks = <&aoss_qmp>; 1023 clock-names = "apb_pclk"; 1024 1025 in-ports { 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 1029 port@4 { 1030 reg = <4>; 1031 1032 funnel1_in4: endpoint { 1033 remote-endpoint = <&apss_funnel1_out>; 1034 }; 1035 }; 1036 1037 port@5 { 1038 reg = <5>; 1039 1040 funnel1_in5: endpoint { 1041 remote-endpoint = <&dlct0_funnel_out>; 1042 }; 1043 }; 1044 1045 port@6 { 1046 reg = <6>; 1047 1048 funnel1_in6: endpoint { 1049 remote-endpoint = <&dlmm_funnel_out>; 1050 }; 1051 }; 1052 1053 port@7 { 1054 reg = <7>; 1055 1056 funnel1_in7: endpoint { 1057 remote-endpoint = <&dlst_ch_funnel_out>; 1058 }; 1059 }; 1060 }; 1061 1062 out-ports { 1063 port { 1064 funnel1_out: endpoint { 1065 remote-endpoint = <&qdss_funnel_in1>; 1066 }; 1067 }; 1068 }; 1069 }; 1070 1071 funnel@4045000 { 1072 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1073 reg = <0x0 0x04045000 0x0 0x1000>; 1074 1075 clocks = <&aoss_qmp>; 1076 clock-names = "apb_pclk"; 1077 1078 in-ports { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 port@0 { 1083 reg = <0>; 1084 1085 qdss_funnel_in0: endpoint { 1086 remote-endpoint = <&funnel0_out>; 1087 }; 1088 }; 1089 1090 port@1 { 1091 reg = <1>; 1092 1093 qdss_funnel_in1: endpoint { 1094 remote-endpoint = <&funnel1_out>; 1095 }; 1096 }; 1097 }; 1098 1099 out-ports { 1100 port { 1101 qdss_funnel_out: endpoint { 1102 remote-endpoint = <&aoss_funnel_in7>; 1103 }; 1104 }; 1105 }; 1106 }; 1107 1108 tpdm@4841000 { 1109 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1110 reg = <0x0 0x04841000 0x0 0x1000>; 1111 1112 clocks = <&aoss_qmp>; 1113 clock-names = "apb_pclk"; 1114 1115 qcom,cmb-element-bits = <32>; 1116 qcom,cmb-msrs-num = <32>; 1117 1118 out-ports { 1119 port { 1120 prng_tpdm_out: endpoint { 1121 remote-endpoint = <&dlct0_tpda_in19>; 1122 }; 1123 }; 1124 }; 1125 }; 1126 1127 tpdm@4850000 { 1128 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1129 reg = <0x0 0x04850000 0x0 0x1000>; 1130 1131 clocks = <&aoss_qmp>; 1132 clock-names = "apb_pclk"; 1133 1134 qcom,cmb-element-bits = <64>; 1135 qcom,cmb-msrs-num = <32>; 1136 qcom,dsb-element-bits = <32>; 1137 qcom,dsb-msrs-num = <32>; 1138 1139 out-ports { 1140 port { 1141 pimem_tpdm_out: endpoint { 1142 remote-endpoint = <&dlct0_tpda_in25>; 1143 }; 1144 }; 1145 }; 1146 }; 1147 1148 tpdm@4860000 { 1149 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1150 reg = <0x0 0x04860000 0x0 0x1000>; 1151 1152 clocks = <&aoss_qmp>; 1153 clock-names = "apb_pclk"; 1154 1155 qcom,dsb-element-bits = <32>; 1156 qcom,dsb-msrs-num = <32>; 1157 1158 out-ports { 1159 port { 1160 dlst_ch_tpdm0_out: endpoint { 1161 remote-endpoint = <&dlst_ch_tpda_in8>; 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 tpda@4864000 { 1168 compatible = "qcom,coresight-tpda", "arm,primecell"; 1169 reg = <0x0 0x04864000 0x0 0x1000>; 1170 1171 clocks = <&aoss_qmp>; 1172 clock-names = "apb_pclk"; 1173 1174 in-ports { 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 1178 port@8 { 1179 reg = <8>; 1180 1181 dlst_ch_tpda_in8: endpoint { 1182 remote-endpoint = <&dlst_ch_tpdm0_out>; 1183 }; 1184 }; 1185 }; 1186 1187 out-ports { 1188 port { 1189 dlst_ch_tpda_out: endpoint { 1190 remote-endpoint = <&dlst_ch_funnel_in0>; 1191 }; 1192 }; 1193 }; 1194 }; 1195 1196 funnel@4865000 { 1197 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1198 reg = <0x0 0x04865000 0x0 0x1000>; 1199 1200 clocks = <&aoss_qmp>; 1201 clock-names = "apb_pclk"; 1202 1203 in-ports { 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 1207 port@0 { 1208 reg = <0>; 1209 1210 dlst_ch_funnel_in0: endpoint { 1211 remote-endpoint = <&dlst_ch_tpda_out>; 1212 }; 1213 }; 1214 1215 port@4 { 1216 reg = <4>; 1217 1218 dlst_ch_funnel_in4: endpoint { 1219 remote-endpoint = <&dlst_funnel_out>; 1220 }; 1221 }; 1222 1223 port@6 { 1224 reg = <6>; 1225 1226 dlst_ch_funnel_in6: endpoint { 1227 remote-endpoint = <&gdsp_funnel_out>; 1228 }; 1229 }; 1230 }; 1231 1232 out-ports { 1233 port { 1234 dlst_ch_funnel_out: endpoint { 1235 remote-endpoint = <&funnel1_in7>; 1236 }; 1237 }; 1238 }; 1239 }; 1240 1241 tpdm@4980000 { 1242 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1243 reg = <0x0 0x04980000 0x0 0x1000>; 1244 1245 clocks = <&aoss_qmp>; 1246 clock-names = "apb_pclk"; 1247 1248 qcom,dsb-element-bits = <32>; 1249 qcom,dsb-msrs-num = <32>; 1250 1251 out-ports { 1252 port { 1253 turing2_tpdm_out: endpoint { 1254 remote-endpoint = <&turing2_funnel_in0>; 1255 }; 1256 }; 1257 }; 1258 }; 1259 1260 funnel@4983000 { 1261 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1262 reg = <0x0 0x04983000 0x0 0x1000>; 1263 1264 clocks = <&aoss_qmp>; 1265 clock-names = "apb_pclk"; 1266 1267 in-ports { 1268 port { 1269 turing2_funnel_in0: endpoint { 1270 remote-endpoint = <&turing2_tpdm_out>; 1271 }; 1272 }; 1273 }; 1274 1275 out-ports { 1276 port { 1277 turing2_funnel_out0: endpoint { 1278 remote-endpoint = <&gdsp_tpda_in5>; 1279 }; 1280 }; 1281 }; 1282 }; 1283 1284 tpdm@4ac0000 { 1285 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1286 reg = <0x0 0x04ac0000 0x0 0x1000>; 1287 1288 clocks = <&aoss_qmp>; 1289 clock-names = "apb_pclk"; 1290 1291 qcom,dsb-element-bits = <32>; 1292 qcom,dsb-msrs-num = <32>; 1293 1294 out-ports { 1295 port { 1296 dlmm_tpdm0_out: endpoint { 1297 remote-endpoint = <&dlmm_tpda_in27>; 1298 }; 1299 }; 1300 }; 1301 }; 1302 1303 tpda@4ac4000 { 1304 compatible = "qcom,coresight-tpda", "arm,primecell"; 1305 reg = <0x0 0x04ac4000 0x0 0x1000>; 1306 1307 clocks = <&aoss_qmp>; 1308 clock-names = "apb_pclk"; 1309 1310 in-ports { 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 1314 port@1b { 1315 reg = <27>; 1316 1317 dlmm_tpda_in27: endpoint { 1318 remote-endpoint = <&dlmm_tpdm0_out>; 1319 }; 1320 }; 1321 }; 1322 1323 out-ports { 1324 port { 1325 dlmm_tpda_out: endpoint { 1326 remote-endpoint = <&dlmm_funnel_in0>; 1327 }; 1328 }; 1329 }; 1330 }; 1331 1332 funnel@4ac5000 { 1333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1334 reg = <0x0 0x04ac5000 0x0 0x1000>; 1335 1336 clocks = <&aoss_qmp>; 1337 clock-names = "apb_pclk"; 1338 1339 in-ports { 1340 port { 1341 dlmm_funnel_in0: endpoint { 1342 remote-endpoint = <&dlmm_tpda_out>; 1343 }; 1344 }; 1345 }; 1346 1347 out-ports { 1348 port { 1349 dlmm_funnel_out: endpoint { 1350 remote-endpoint = <&funnel1_in6>; 1351 }; 1352 }; 1353 }; 1354 }; 1355 1356 tpdm@4ad0000 { 1357 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1358 reg = <0x0 0x04ad0000 0x0 0x1000>; 1359 1360 clocks = <&aoss_qmp>; 1361 clock-names = "apb_pclk"; 1362 1363 qcom,dsb-element-bits = <32>; 1364 qcom,dsb-msrs-num = <32>; 1365 1366 out-ports { 1367 port { 1368 dlct0_tpdm0_out: endpoint { 1369 remote-endpoint = <&dlct0_tpda_in26>; 1370 }; 1371 }; 1372 }; 1373 }; 1374 1375 tpda@4ad3000 { 1376 compatible = "qcom,coresight-tpda", "arm,primecell"; 1377 reg = <0x0 0x04ad3000 0x0 0x1000>; 1378 1379 clocks = <&aoss_qmp>; 1380 clock-names = "apb_pclk"; 1381 1382 in-ports { 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 1386 port@13 { 1387 reg = <19>; 1388 1389 dlct0_tpda_in19: endpoint { 1390 remote-endpoint = <&prng_tpdm_out>; 1391 }; 1392 }; 1393 1394 port@19 { 1395 reg = <25>; 1396 1397 dlct0_tpda_in25: endpoint { 1398 remote-endpoint = <&pimem_tpdm_out>; 1399 }; 1400 }; 1401 1402 port@1a { 1403 reg = <26>; 1404 1405 dlct0_tpda_in26: endpoint { 1406 remote-endpoint = <&dlct0_tpdm0_out>; 1407 }; 1408 }; 1409 }; 1410 1411 out-ports { 1412 port { 1413 dlct0_tpda_out: endpoint { 1414 remote-endpoint = <&dlct0_funnel_in0>; 1415 }; 1416 }; 1417 }; 1418 }; 1419 1420 funnel@4ad4000 { 1421 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1422 reg = <0x0 0x04ad4000 0x0 0x1000>; 1423 1424 clocks = <&aoss_qmp>; 1425 clock-names = "apb_pclk"; 1426 1427 in-ports { 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 1431 port@0 { 1432 reg = <0>; 1433 1434 dlct0_funnel_in0: endpoint { 1435 remote-endpoint = <&dlct0_tpda_out>; 1436 }; 1437 }; 1438 1439 port@4 { 1440 reg = <4>; 1441 1442 dlct0_funnel_in4: endpoint { 1443 remote-endpoint = <&ddr_funnel5_out>; 1444 }; 1445 }; 1446 }; 1447 1448 out-ports { 1449 port { 1450 dlct0_funnel_out: endpoint { 1451 remote-endpoint = <&funnel1_in5>; 1452 }; 1453 }; 1454 }; 1455 }; 1456 1457 funnel@4b04000 { 1458 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1459 reg = <0x0 0x04b04000 0x0 0x1000>; 1460 1461 clocks = <&aoss_qmp>; 1462 clock-names = "apb_pclk"; 1463 1464 in-ports { 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 1468 port@6 { 1469 reg = <6>; 1470 1471 aoss_funnel_in6: endpoint { 1472 remote-endpoint = <&aoss_tpda_out>; 1473 }; 1474 }; 1475 1476 port@7 { 1477 reg = <7>; 1478 1479 aoss_funnel_in7: endpoint { 1480 remote-endpoint = <&qdss_funnel_out>; 1481 }; 1482 }; 1483 }; 1484 1485 out-ports { 1486 port { 1487 aoss_funnel_out: endpoint { 1488 remote-endpoint = <&etf0_in>; 1489 }; 1490 }; 1491 }; 1492 }; 1493 1494 tmc_etf: tmc@4b05000 { 1495 compatible = "arm,coresight-tmc", "arm,primecell"; 1496 reg = <0x0 0x04b05000 0x0 0x1000>; 1497 1498 clocks = <&aoss_qmp>; 1499 clock-names = "apb_pclk"; 1500 1501 in-ports { 1502 port { 1503 etf0_in: endpoint { 1504 remote-endpoint = <&aoss_funnel_out>; 1505 }; 1506 }; 1507 }; 1508 1509 out-ports { 1510 port { 1511 etf0_out: endpoint { 1512 remote-endpoint = <&swao_rep_in>; 1513 }; 1514 }; 1515 }; 1516 }; 1517 1518 replicator@4b06000 { 1519 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1520 reg = <0x0 0x04b06000 0x0 0x1000>; 1521 1522 clocks = <&aoss_qmp>; 1523 clock-names = "apb_pclk"; 1524 1525 in-ports { 1526 port { 1527 swao_rep_in: endpoint { 1528 remote-endpoint = <&etf0_out>; 1529 }; 1530 }; 1531 }; 1532 1533 out-ports { 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 1537 port@1 { 1538 reg = <1>; 1539 1540 swao_rep_out1: endpoint { 1541 remote-endpoint = <&eud_in>; 1542 }; 1543 }; 1544 }; 1545 }; 1546 1547 tpda@4b08000 { 1548 compatible = "qcom,coresight-tpda", "arm,primecell"; 1549 reg = <0x0 0x04b08000 0x0 0x1000>; 1550 1551 clocks = <&aoss_qmp>; 1552 clock-names = "apb_pclk"; 1553 1554 in-ports { 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 1558 port@0 { 1559 reg = <0>; 1560 1561 aoss_tpda_in0: endpoint { 1562 remote-endpoint = <&aoss_tpdm0_out>; 1563 }; 1564 }; 1565 1566 port@1 { 1567 reg = <1>; 1568 1569 aoss_tpda_in1: endpoint { 1570 remote-endpoint = <&aoss_tpdm1_out>; 1571 }; 1572 }; 1573 1574 port@2 { 1575 reg = <2>; 1576 1577 aoss_tpda_in2: endpoint { 1578 remote-endpoint = <&aoss_tpdm2_out>; 1579 }; 1580 }; 1581 1582 port@3 { 1583 reg = <3>; 1584 1585 aoss_tpda_in3: endpoint { 1586 remote-endpoint = <&aoss_tpdm3_out>; 1587 }; 1588 }; 1589 1590 port@4 { 1591 reg = <4>; 1592 1593 aoss_tpda_in4: endpoint { 1594 remote-endpoint = <&aoss_tpdm4_out>; 1595 }; 1596 }; 1597 }; 1598 1599 out-ports { 1600 port { 1601 aoss_tpda_out: endpoint { 1602 remote-endpoint = <&aoss_funnel_in6>; 1603 }; 1604 }; 1605 }; 1606 }; 1607 1608 tpdm@4b09000 { 1609 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1610 reg = <0x0 0x04b09000 0x0 0x1000>; 1611 1612 clocks = <&aoss_qmp>; 1613 clock-names = "apb_pclk"; 1614 1615 qcom,cmb-element-bits = <64>; 1616 qcom,cmb-msrs-num = <32>; 1617 1618 out-ports { 1619 port { 1620 aoss_tpdm0_out: endpoint { 1621 remote-endpoint = <&aoss_tpda_in0>; 1622 }; 1623 }; 1624 }; 1625 }; 1626 1627 tpdm@4b0a000 { 1628 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1629 reg = <0x0 0x04b0a000 0x0 0x1000>; 1630 1631 clocks = <&aoss_qmp>; 1632 clock-names = "apb_pclk"; 1633 1634 qcom,cmb-element-bits = <64>; 1635 qcom,cmb-msrs-num = <32>; 1636 1637 out-ports { 1638 port { 1639 aoss_tpdm1_out: endpoint { 1640 remote-endpoint = <&aoss_tpda_in1>; 1641 }; 1642 }; 1643 }; 1644 }; 1645 1646 tpdm@4b0b000 { 1647 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1648 reg = <0x0 0x04b0b000 0x0 0x1000>; 1649 1650 clocks = <&aoss_qmp>; 1651 clock-names = "apb_pclk"; 1652 1653 qcom,cmb-element-bits = <64>; 1654 qcom,cmb-msrs-num = <32>; 1655 1656 out-ports { 1657 port { 1658 aoss_tpdm2_out: endpoint { 1659 remote-endpoint = <&aoss_tpda_in2>; 1660 }; 1661 }; 1662 }; 1663 }; 1664 1665 tpdm@4b0c000 { 1666 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1667 reg = <0x0 0x04b0c000 0x0 0x1000>; 1668 1669 clocks = <&aoss_qmp>; 1670 clock-names = "apb_pclk"; 1671 1672 qcom,cmb-element-bits = <64>; 1673 qcom,cmb-msrs-num = <32>; 1674 1675 out-ports { 1676 port { 1677 aoss_tpdm3_out: endpoint { 1678 remote-endpoint = <&aoss_tpda_in3>; 1679 }; 1680 }; 1681 }; 1682 }; 1683 1684 tpdm@4b0d000 { 1685 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1686 reg = <0x0 0x04b0d000 0x0 0x1000>; 1687 1688 clocks = <&aoss_qmp>; 1689 clock-names = "apb_pclk"; 1690 1691 qcom,dsb-element-bits = <32>; 1692 qcom,dsb-msrs-num = <32>; 1693 1694 out-ports { 1695 port { 1696 aoss_tpdm4_out: endpoint { 1697 remote-endpoint = <&aoss_tpda_in4>; 1698 }; 1699 }; 1700 }; 1701 }; 1702 1703 cti@4b13000 { 1704 compatible = "arm,coresight-cti", "arm,primecell"; 1705 reg = <0x0 0x04b13000 0x0 0x1000>; 1706 1707 clocks = <&aoss_qmp>; 1708 clock-names = "apb_pclk"; 1709 }; 1710 1711 tpdm@4b80000 { 1712 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1713 reg = <0x0 0x04b80000 0x0 0x1000>; 1714 1715 clocks = <&aoss_qmp>; 1716 clock-names = "apb_pclk"; 1717 1718 qcom,dsb-element-bits = <32>; 1719 qcom,dsb-msrs-num = <32>; 1720 1721 out-ports { 1722 port { 1723 turing0_tpdm0_out: endpoint { 1724 remote-endpoint = <&turing0_tpda_in0>; 1725 }; 1726 }; 1727 }; 1728 }; 1729 1730 tpda@4b86000 { 1731 compatible = "qcom,coresight-tpda", "arm,primecell"; 1732 reg = <0x0 0x04b86000 0x0 0x1000>; 1733 1734 clocks = <&aoss_qmp>; 1735 clock-names = "apb_pclk"; 1736 1737 in-ports { 1738 port { 1739 turing0_tpda_in0: endpoint { 1740 remote-endpoint = <&turing0_tpdm0_out>; 1741 }; 1742 }; 1743 }; 1744 1745 out-ports { 1746 port { 1747 turing0_tpda_out: endpoint { 1748 remote-endpoint = <&turing0_funnel_in0>; 1749 }; 1750 }; 1751 }; 1752 }; 1753 1754 funnel@4b87000 { 1755 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1756 reg = <0x0 0x04b87000 0x0 0x1000>; 1757 1758 clocks = <&aoss_qmp>; 1759 clock-names = "apb_pclk"; 1760 1761 in-ports { 1762 port { 1763 turing0_funnel_in0: endpoint { 1764 remote-endpoint = <&turing0_tpda_out>; 1765 }; 1766 }; 1767 }; 1768 1769 out-ports { 1770 port { 1771 turing0_funnel_out: endpoint { 1772 remote-endpoint = <&gdsp_funnel_in4>; 1773 }; 1774 }; 1775 }; 1776 }; 1777 1778 cti@4b8b000 { 1779 compatible = "arm,coresight-cti", "arm,primecell"; 1780 reg = <0x0 0x04b8b000 0x0 0x1000>; 1781 1782 clocks = <&aoss_qmp>; 1783 clock-names = "apb_pclk"; 1784 }; 1785 1786 tpdm@4c40000 { 1787 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1788 reg = <0x0 0x04c40000 0x0 0x1000>; 1789 1790 clocks = <&aoss_qmp>; 1791 clock-names = "apb_pclk"; 1792 1793 qcom,dsb-element-bits = <32>; 1794 qcom,dsb-msrs-num = <32>; 1795 1796 out-ports { 1797 port { 1798 gdsp_tpdm0_out: endpoint { 1799 remote-endpoint = <&gdsp_tpda_in8>; 1800 }; 1801 }; 1802 }; 1803 }; 1804 1805 tpda@4c44000 { 1806 compatible = "qcom,coresight-tpda", "arm,primecell"; 1807 reg = <0x0 0x04c44000 0x0 0x1000>; 1808 1809 clocks = <&aoss_qmp>; 1810 clock-names = "apb_pclk"; 1811 1812 in-ports { 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 1816 port@5 { 1817 reg = <5>; 1818 1819 gdsp_tpda_in5: endpoint { 1820 remote-endpoint = <&turing2_funnel_out0>; 1821 }; 1822 }; 1823 1824 port@8 { 1825 reg = <8>; 1826 1827 gdsp_tpda_in8: endpoint { 1828 remote-endpoint = <&gdsp_tpdm0_out>; 1829 }; 1830 }; 1831 }; 1832 1833 out-ports { 1834 port { 1835 gdsp_tpda_out: endpoint { 1836 remote-endpoint = <&gdsp_funnel_in0>; 1837 }; 1838 }; 1839 }; 1840 }; 1841 1842 funnel@4c45000 { 1843 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1844 reg = <0x0 0x04c45000 0x0 0x1000>; 1845 1846 clocks = <&aoss_qmp>; 1847 clock-names = "apb_pclk"; 1848 1849 in-ports { 1850 #address-cells = <1>; 1851 #size-cells = <0>; 1852 1853 port@0 { 1854 reg = <0>; 1855 1856 gdsp_funnel_in0: endpoint { 1857 remote-endpoint = <&gdsp_tpda_out>; 1858 }; 1859 }; 1860 1861 port@4 { 1862 reg = <4>; 1863 1864 gdsp_funnel_in4: endpoint { 1865 remote-endpoint = <&turing0_funnel_out>; 1866 }; 1867 }; 1868 }; 1869 1870 out-ports { 1871 port { 1872 gdsp_funnel_out: endpoint { 1873 remote-endpoint = <&dlst_ch_funnel_in6>; 1874 }; 1875 }; 1876 }; 1877 }; 1878 1879 tpdm@4c50000 { 1880 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1881 reg = <0x0 0x04c50000 0x0 0x1000>; 1882 1883 clocks = <&aoss_qmp>; 1884 clock-names = "apb_pclk"; 1885 1886 qcom,dsb-element-bits = <32>; 1887 qcom,dsb-msrs-num = <32>; 1888 1889 out-ports { 1890 port { 1891 dlst_tpdm0_out: endpoint { 1892 remote-endpoint = <&dlst_tpda_in8>; 1893 }; 1894 }; 1895 }; 1896 }; 1897 1898 tpda@4c54000 { 1899 compatible = "qcom,coresight-tpda", "arm,primecell"; 1900 reg = <0x0 0x04c54000 0x0 0x1000>; 1901 1902 clocks = <&aoss_qmp>; 1903 clock-names = "apb_pclk"; 1904 1905 in-ports { 1906 #address-cells = <1>; 1907 #size-cells = <0>; 1908 1909 port@8 { 1910 reg = <8>; 1911 1912 dlst_tpda_in8: endpoint { 1913 remote-endpoint = <&dlst_tpdm0_out>; 1914 }; 1915 }; 1916 }; 1917 1918 out-ports { 1919 port { 1920 dlst_tpda_out: endpoint { 1921 remote-endpoint = <&dlst_funnel_in0>; 1922 }; 1923 }; 1924 }; 1925 }; 1926 1927 funnel@4c55000 { 1928 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1929 reg = <0x0 0x04c55000 0x0 0x1000>; 1930 1931 clocks = <&aoss_qmp>; 1932 clock-names = "apb_pclk"; 1933 1934 in-ports { 1935 port { 1936 dlst_funnel_in0: endpoint { 1937 remote-endpoint = <&dlst_tpda_out>; 1938 }; 1939 }; 1940 }; 1941 1942 out-ports { 1943 port { 1944 dlst_funnel_out: endpoint { 1945 remote-endpoint = <&dlst_ch_funnel_in4>; 1946 }; 1947 }; 1948 }; 1949 }; 1950 1951 tpdm@4e00000 { 1952 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1953 reg = <0x0 0x04e00000 0x0 0x1000>; 1954 1955 clocks = <&aoss_qmp>; 1956 clock-names = "apb_pclk"; 1957 1958 qcom,dsb-element-bits = <32>; 1959 qcom,dsb-msrs-num = <32>; 1960 qcom,cmb-element-bits = <32>; 1961 qcom,cmb-msrs-num = <32>; 1962 1963 out-ports { 1964 port { 1965 ddr_tpdm3_out: endpoint { 1966 remote-endpoint = <&ddr_tpda_in4>; 1967 }; 1968 }; 1969 }; 1970 }; 1971 1972 tpda@4e03000 { 1973 compatible = "qcom,coresight-tpda", "arm,primecell"; 1974 reg = <0x0 0x04e03000 0x0 0x1000>; 1975 1976 clocks = <&aoss_qmp>; 1977 clock-names = "apb_pclk"; 1978 1979 in-ports { 1980 #address-cells = <1>; 1981 #size-cells = <0>; 1982 1983 port@0 { 1984 reg = <0>; 1985 1986 ddr_tpda_in0: endpoint { 1987 remote-endpoint = <&ddr_funnel0_out0>; 1988 }; 1989 }; 1990 1991 port@1 { 1992 reg = <1>; 1993 1994 ddr_tpda_in1: endpoint { 1995 remote-endpoint = <&ddr_funnel1_out0>; 1996 }; 1997 }; 1998 1999 port@4 { 2000 reg = <4>; 2001 2002 ddr_tpda_in4: endpoint { 2003 remote-endpoint = <&ddr_tpdm3_out>; 2004 }; 2005 }; 2006 }; 2007 2008 out-ports { 2009 port { 2010 ddr_tpda_out: endpoint { 2011 remote-endpoint = <&ddr_funnel5_in0>; 2012 }; 2013 }; 2014 }; 2015 }; 2016 2017 funnel@4e04000 { 2018 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2019 reg = <0x0 0x04e04000 0x0 0x1000>; 2020 2021 clocks = <&aoss_qmp>; 2022 clock-names = "apb_pclk"; 2023 2024 in-ports { 2025 port { 2026 ddr_funnel5_in0: endpoint { 2027 remote-endpoint = <&ddr_tpda_out>; 2028 }; 2029 }; 2030 }; 2031 2032 out-ports { 2033 port { 2034 ddr_funnel5_out: endpoint { 2035 remote-endpoint = <&dlct0_funnel_in4>; 2036 }; 2037 }; 2038 }; 2039 }; 2040 2041 tpdm@4e10000 { 2042 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2043 reg = <0x0 0x04e10000 0x0 0x1000>; 2044 2045 clocks = <&aoss_qmp>; 2046 clock-names = "apb_pclk"; 2047 2048 qcom,dsb-element-bits = <32>; 2049 qcom,dsb-msrs-num = <32>; 2050 2051 out-ports { 2052 port { 2053 ddr_tpdm0_out: endpoint { 2054 remote-endpoint = <&ddr_funnel0_in0>; 2055 }; 2056 }; 2057 }; 2058 }; 2059 2060 funnel@4e12000 { 2061 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2062 reg = <0x0 0x04e12000 0x0 0x1000>; 2063 2064 clocks = <&aoss_qmp>; 2065 clock-names = "apb_pclk"; 2066 2067 in-ports { 2068 port { 2069 ddr_funnel0_in0: endpoint { 2070 remote-endpoint = <&ddr_tpdm0_out>; 2071 }; 2072 }; 2073 }; 2074 2075 out-ports { 2076 port { 2077 ddr_funnel0_out0: endpoint { 2078 remote-endpoint = <&ddr_tpda_in0>; 2079 }; 2080 }; 2081 }; 2082 }; 2083 2084 tpdm@4e20000 { 2085 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2086 reg = <0x0 0x04e20000 0x0 0x1000>; 2087 2088 clocks = <&aoss_qmp>; 2089 clock-names = "apb_pclk"; 2090 2091 qcom,dsb-element-bits = <32>; 2092 qcom,dsb-msrs-num = <32>; 2093 2094 out-ports { 2095 port { 2096 ddr_tpdm1_out: endpoint { 2097 remote-endpoint = <&ddr_funnel1_in0>; 2098 }; 2099 }; 2100 }; 2101 }; 2102 2103 funnel@4e22000 { 2104 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2105 reg = <0x0 0x04e22000 0x0 0x1000>; 2106 2107 clocks = <&aoss_qmp>; 2108 clock-names = "apb_pclk"; 2109 2110 in-ports { 2111 port { 2112 ddr_funnel1_in0: endpoint { 2113 remote-endpoint = <&ddr_tpdm1_out>; 2114 }; 2115 }; 2116 }; 2117 2118 out-ports { 2119 port { 2120 ddr_funnel1_out0: endpoint { 2121 remote-endpoint = <&ddr_tpda_in1>; 2122 }; 2123 }; 2124 }; 2125 }; 2126 2127 etm@6040000 { 2128 compatible = "arm,primecell"; 2129 reg = <0x0 0x06040000 0x0 0x1000>; 2130 cpu = <&cpu0>; 2131 2132 clocks = <&aoss_qmp>; 2133 clock-names = "apb_pclk"; 2134 2135 arm,coresight-loses-context-with-cpu; 2136 qcom,skip-power-up; 2137 2138 out-ports { 2139 port { 2140 etm0_out: endpoint { 2141 remote-endpoint = <&apss_funnel0_in0>; 2142 }; 2143 }; 2144 }; 2145 }; 2146 2147 etm@6140000 { 2148 compatible = "arm,primecell"; 2149 reg = <0x0 0x06140000 0x0 0x1000>; 2150 cpu = <&cpu1>; 2151 2152 clocks = <&aoss_qmp>; 2153 clock-names = "apb_pclk"; 2154 2155 arm,coresight-loses-context-with-cpu; 2156 qcom,skip-power-up; 2157 2158 out-ports { 2159 port { 2160 etm1_out: endpoint { 2161 remote-endpoint = <&apss_funnel0_in1>; 2162 }; 2163 }; 2164 }; 2165 }; 2166 2167 etm@6240000 { 2168 compatible = "arm,primecell"; 2169 reg = <0x0 0x06240000 0x0 0x1000>; 2170 cpu = <&cpu2>; 2171 2172 clocks = <&aoss_qmp>; 2173 clock-names = "apb_pclk"; 2174 2175 arm,coresight-loses-context-with-cpu; 2176 qcom,skip-power-up; 2177 2178 out-ports { 2179 port { 2180 etm2_out: endpoint { 2181 remote-endpoint = <&apss_funnel0_in2>; 2182 }; 2183 }; 2184 }; 2185 }; 2186 2187 etm@6340000 { 2188 compatible = "arm,primecell"; 2189 reg = <0x0 0x06340000 0x0 0x1000>; 2190 cpu = <&cpu3>; 2191 2192 clocks = <&aoss_qmp>; 2193 clock-names = "apb_pclk"; 2194 2195 arm,coresight-loses-context-with-cpu; 2196 qcom,skip-power-up; 2197 2198 out-ports { 2199 port { 2200 etm3_out: endpoint { 2201 remote-endpoint = <&apss_funnel0_in3>; 2202 }; 2203 }; 2204 }; 2205 }; 2206 2207 etm@6440000 { 2208 compatible = "arm,primecell"; 2209 reg = <0x0 0x06440000 0x0 0x1000>; 2210 cpu = <&cpu4>; 2211 2212 clocks = <&aoss_qmp>; 2213 clock-names = "apb_pclk"; 2214 2215 arm,coresight-loses-context-with-cpu; 2216 qcom,skip-power-up; 2217 2218 out-ports { 2219 port { 2220 etm4_out: endpoint { 2221 remote-endpoint = <&apss_funnel0_in4>; 2222 }; 2223 }; 2224 }; 2225 }; 2226 2227 etm@6540000 { 2228 compatible = "arm,primecell"; 2229 reg = <0x0 0x06540000 0x0 0x1000>; 2230 cpu = <&cpu5>; 2231 2232 clocks = <&aoss_qmp>; 2233 clock-names = "apb_pclk"; 2234 2235 arm,coresight-loses-context-with-cpu; 2236 qcom,skip-power-up; 2237 2238 out-ports { 2239 port { 2240 etm5_out: endpoint { 2241 remote-endpoint = <&apss_funnel0_in5>; 2242 }; 2243 }; 2244 }; 2245 }; 2246 2247 etm@6640000 { 2248 compatible = "arm,primecell"; 2249 reg = <0x0 0x06640000 0x0 0x1000>; 2250 cpu = <&cpu6>; 2251 2252 clocks = <&aoss_qmp>; 2253 clock-names = "apb_pclk"; 2254 2255 arm,coresight-loses-context-with-cpu; 2256 qcom,skip-power-up; 2257 2258 out-ports { 2259 port { 2260 etm6_out: endpoint { 2261 remote-endpoint = <&apss_funnel0_in6>; 2262 }; 2263 }; 2264 }; 2265 }; 2266 2267 etm@6740000 { 2268 compatible = "arm,primecell"; 2269 reg = <0x0 0x06740000 0x0 0x1000>; 2270 cpu = <&cpu7>; 2271 2272 clocks = <&aoss_qmp>; 2273 clock-names = "apb_pclk"; 2274 2275 arm,coresight-loses-context-with-cpu; 2276 qcom,skip-power-up; 2277 2278 out-ports { 2279 port { 2280 etm7_out: endpoint { 2281 remote-endpoint = <&apss_funnel0_in7>; 2282 }; 2283 }; 2284 }; 2285 }; 2286 2287 funnel@6800000 { 2288 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2289 reg = <0x0 0x06800000 0x0 0x1000>; 2290 2291 clocks = <&aoss_qmp>; 2292 clock-names = "apb_pclk"; 2293 2294 in-ports { 2295 #address-cells = <1>; 2296 #size-cells = <0>; 2297 2298 port@0 { 2299 reg = <0>; 2300 2301 apss_funnel0_in0: endpoint { 2302 remote-endpoint = <&etm0_out>; 2303 }; 2304 }; 2305 2306 port@1 { 2307 reg = <1>; 2308 2309 apss_funnel0_in1: endpoint { 2310 remote-endpoint = <&etm1_out>; 2311 }; 2312 }; 2313 2314 port@2 { 2315 reg = <2>; 2316 2317 apss_funnel0_in2: endpoint { 2318 remote-endpoint = <&etm2_out>; 2319 }; 2320 }; 2321 2322 port@3 { 2323 reg = <3>; 2324 2325 apss_funnel0_in3: endpoint { 2326 remote-endpoint = <&etm3_out>; 2327 }; 2328 }; 2329 2330 port@4 { 2331 reg = <4>; 2332 2333 apss_funnel0_in4: endpoint { 2334 remote-endpoint = <&etm4_out>; 2335 }; 2336 }; 2337 2338 port@5 { 2339 reg = <5>; 2340 2341 apss_funnel0_in5: endpoint { 2342 remote-endpoint = <&etm5_out>; 2343 }; 2344 }; 2345 2346 port@6 { 2347 reg = <6>; 2348 2349 apss_funnel0_in6: endpoint { 2350 remote-endpoint = <&etm6_out>; 2351 }; 2352 }; 2353 2354 port@7 { 2355 reg = <7>; 2356 2357 apss_funnel0_in7: endpoint { 2358 remote-endpoint = <&etm7_out>; 2359 }; 2360 }; 2361 }; 2362 2363 out-ports { 2364 port { 2365 apss_funnel0_out: endpoint { 2366 remote-endpoint = <&apss_funnel1_in0>; 2367 }; 2368 }; 2369 }; 2370 }; 2371 2372 funnel@6810000 { 2373 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2374 reg = <0x0 0x06810000 0x0 0x1000>; 2375 2376 clocks = <&aoss_qmp>; 2377 clock-names = "apb_pclk"; 2378 2379 in-ports { 2380 #address-cells = <1>; 2381 #size-cells = <0>; 2382 2383 port@0 { 2384 reg = <0>; 2385 2386 apss_funnel1_in0: endpoint { 2387 remote-endpoint = <&apss_funnel0_out>; 2388 }; 2389 }; 2390 2391 port@3 { 2392 reg = <3>; 2393 2394 apss_funnel1_in3: endpoint { 2395 remote-endpoint = <&apss_tpda_out>; 2396 }; 2397 }; 2398 }; 2399 2400 out-ports { 2401 port { 2402 apss_funnel1_out: endpoint { 2403 remote-endpoint = <&funnel1_in4>; 2404 }; 2405 }; 2406 }; 2407 }; 2408 2409 cti@682b000 { 2410 compatible = "arm,coresight-cti", "arm,primecell"; 2411 reg = <0x0 0x0682b000 0x0 0x1000>; 2412 2413 clocks = <&aoss_qmp>; 2414 clock-names = "apb_pclk"; 2415 }; 2416 2417 tpdm@6860000 { 2418 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2419 reg = <0x0 0x06860000 0x0 0x1000>; 2420 2421 clocks = <&aoss_qmp>; 2422 clock-names = "apb_pclk"; 2423 2424 qcom,cmb-element-bits = <64>; 2425 qcom,cmb-msrs-num = <32>; 2426 2427 out-ports { 2428 port { 2429 apss_tpdm3_out: endpoint { 2430 remote-endpoint = <&apss_tpda_in3>; 2431 }; 2432 }; 2433 }; 2434 }; 2435 2436 tpdm@6861000 { 2437 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2438 reg = <0x0 0x06861000 0x0 0x1000>; 2439 2440 clocks = <&aoss_qmp>; 2441 clock-names = "apb_pclk"; 2442 2443 qcom,dsb-element-bits = <32>; 2444 qcom,dsb-msrs-num = <32>; 2445 2446 out-ports { 2447 port { 2448 apss_tpdm4_out: endpoint { 2449 remote-endpoint = <&apss_tpda_in4>; 2450 }; 2451 }; 2452 }; 2453 }; 2454 2455 tpda@6863000 { 2456 compatible = "qcom,coresight-tpda", "arm,primecell"; 2457 reg = <0x0 0x06863000 0x0 0x1000>; 2458 2459 clocks = <&aoss_qmp>; 2460 clock-names = "apb_pclk"; 2461 2462 in-ports { 2463 #address-cells = <1>; 2464 #size-cells = <0>; 2465 2466 port@0 { 2467 reg = <0>; 2468 2469 apss_tpda_in0: endpoint { 2470 remote-endpoint = <&apss_tpdm0_out>; 2471 }; 2472 }; 2473 2474 port@1 { 2475 reg = <1>; 2476 2477 apss_tpda_in1: endpoint { 2478 remote-endpoint = <&apss_tpdm1_out>; 2479 }; 2480 }; 2481 2482 port@2 { 2483 reg = <2>; 2484 2485 apss_tpda_in2: endpoint { 2486 remote-endpoint = <&apss_tpdm2_out>; 2487 }; 2488 }; 2489 2490 port@3 { 2491 reg = <3>; 2492 2493 apss_tpda_in3: endpoint { 2494 remote-endpoint = <&apss_tpdm3_out>; 2495 }; 2496 }; 2497 2498 port@4 { 2499 reg = <4>; 2500 2501 apss_tpda_in4: endpoint { 2502 remote-endpoint = <&apss_tpdm4_out>; 2503 }; 2504 }; 2505 }; 2506 2507 out-ports { 2508 port { 2509 apss_tpda_out: endpoint { 2510 remote-endpoint = <&apss_funnel1_in3>; 2511 }; 2512 }; 2513 }; 2514 }; 2515 2516 tpdm@68a0000 { 2517 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2518 reg = <0x0 0x068a0000 0x0 0x1000>; 2519 2520 clocks = <&aoss_qmp>; 2521 clock-names = "apb_pclk"; 2522 2523 qcom,cmb-element-bits = <32>; 2524 qcom,cmb-msrs-num = <32>; 2525 2526 out-ports { 2527 port { 2528 apss_tpdm1_out: endpoint { 2529 remote-endpoint = <&apss_tpda_in1>; 2530 }; 2531 }; 2532 }; 2533 }; 2534 2535 tpdm@68b0000 { 2536 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2537 reg = <0x0 0x068b0000 0x0 0x1000>; 2538 2539 clocks = <&aoss_qmp>; 2540 clock-names = "apb_pclk"; 2541 2542 qcom,cmb-element-bits = <32>; 2543 qcom,cmb-msrs-num = <32>; 2544 2545 out-ports { 2546 port { 2547 apss_tpdm0_out: endpoint { 2548 remote-endpoint = <&apss_tpda_in0>; 2549 }; 2550 }; 2551 }; 2552 }; 2553 2554 tpdm@68c0000 { 2555 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2556 reg = <0x0 0x068c0000 0x0 0x1000>; 2557 2558 clocks = <&aoss_qmp>; 2559 clock-names = "apb_pclk"; 2560 2561 qcom,dsb-element-bits = <32>; 2562 qcom,dsb-msrs-num = <32>; 2563 2564 out-ports { 2565 port { 2566 apss_tpdm2_out: endpoint { 2567 remote-endpoint = <&apss_tpda_in2>; 2568 }; 2569 }; 2570 }; 2571 }; 2572 2573 cti@68e0000 { 2574 compatible = "arm,coresight-cti", "arm,primecell"; 2575 reg = <0x0 0x068e0000 0x0 0x1000>; 2576 2577 clocks = <&aoss_qmp>; 2578 clock-names = "apb_pclk"; 2579 }; 2580 2581 cti@68f0000 { 2582 compatible = "arm,coresight-cti", "arm,primecell"; 2583 reg = <0x0 0x068f0000 0x0 0x1000>; 2584 2585 clocks = <&aoss_qmp>; 2586 clock-names = "apb_pclk"; 2587 }; 2588 2589 cti@6900000 { 2590 compatible = "arm,coresight-cti", "arm,primecell"; 2591 reg = <0x0 0x06900000 0x0 0x1000>; 2592 2593 clocks = <&aoss_qmp>; 2594 clock-names = "apb_pclk"; 2595 }; 2596 2597 usb_1_hsphy: phy@8904000 { 2598 compatible = "qcom,qcs8300-usb-hs-phy", 2599 "qcom,usb-snps-hs-7nm-phy"; 2600 reg = <0x0 0x08904000 0x0 0x400>; 2601 2602 clocks = <&rpmhcc RPMH_CXO_CLK>; 2603 clock-names = "ref"; 2604 2605 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 2606 2607 #phy-cells = <0>; 2608 2609 status = "disabled"; 2610 }; 2611 2612 usb_2_hsphy: phy@8906000 { 2613 compatible = "qcom,qcs8300-usb-hs-phy", 2614 "qcom,usb-snps-hs-7nm-phy"; 2615 reg = <0x0 0x08906000 0x0 0x400>; 2616 2617 clocks = <&rpmhcc RPMH_CXO_CLK>; 2618 clock-names = "ref"; 2619 2620 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 2621 2622 #phy-cells = <0>; 2623 2624 status = "disabled"; 2625 }; 2626 2627 usb_qmpphy: phy@8907000 { 2628 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 2629 reg = <0x0 0x08907000 0x0 0x2000>; 2630 2631 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2632 <&gcc GCC_USB_CLKREF_EN>, 2633 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2634 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2635 clock-names = "aux", 2636 "ref", 2637 "com_aux", 2638 "pipe"; 2639 2640 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2641 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2642 reset-names = "phy", "phy_phy"; 2643 2644 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2645 2646 #clock-cells = <0>; 2647 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2648 2649 #phy-cells = <0>; 2650 2651 status = "disabled"; 2652 }; 2653 2654 serdes0: phy@8909000 { 2655 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 2656 reg = <0x0 0x08909000 0x0 0x00000e10>; 2657 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 2658 clock-names = "sgmi_ref"; 2659 #phy-cells = <0>; 2660 status = "disabled"; 2661 }; 2662 2663 gpucc: clock-controller@3d90000 { 2664 compatible = "qcom,qcs8300-gpucc"; 2665 reg = <0x0 0x03d90000 0x0 0xa000>; 2666 clocks = <&rpmhcc RPMH_CXO_CLK>, 2667 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2668 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2669 clock-names = "bi_tcxo", 2670 "gcc_gpu_gpll0_clk_src", 2671 "gcc_gpu_gpll0_div_clk_src"; 2672 #clock-cells = <1>; 2673 #reset-cells = <1>; 2674 #power-domain-cells = <1>; 2675 }; 2676 2677 pmu@9091000 { 2678 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2679 reg = <0x0 0x9091000 0x0 0x1000>; 2680 2681 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 2682 2683 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 2684 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2685 2686 operating-points-v2 = <&llcc_bwmon_opp_table>; 2687 2688 llcc_bwmon_opp_table: opp-table { 2689 compatible = "operating-points-v2"; 2690 2691 opp-0 { 2692 opp-peak-kBps = <762000>; 2693 }; 2694 2695 opp-1 { 2696 opp-peak-kBps = <1720000>; 2697 }; 2698 2699 opp-2 { 2700 opp-peak-kBps = <2086000>; 2701 }; 2702 2703 opp-3 { 2704 opp-peak-kBps = <2601000>; 2705 }; 2706 2707 opp-4 { 2708 opp-peak-kBps = <2929000>; 2709 }; 2710 2711 opp-5 { 2712 opp-peak-kBps = <5931000>; 2713 }; 2714 2715 opp-6 { 2716 opp-peak-kBps = <6515000>; 2717 }; 2718 2719 opp-7 { 2720 opp-peak-kBps = <7984000>; 2721 }; 2722 2723 opp-8 { 2724 opp-peak-kBps = <10437000>; 2725 }; 2726 2727 opp-9 { 2728 opp-peak-kBps = <12195000>; 2729 }; 2730 }; 2731 }; 2732 2733 pmu@90b5400 { 2734 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 2735 reg = <0x0 0x90b5400 0x0 0x600>; 2736 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2737 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2738 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2739 2740 operating-points-v2 = <&cpu_bwmon_opp_table>; 2741 2742 cpu_bwmon_opp_table: opp-table { 2743 compatible = "operating-points-v2"; 2744 2745 opp-0 { 2746 opp-peak-kBps = <9155000>; 2747 }; 2748 2749 opp-1 { 2750 opp-peak-kBps = <12298000>; 2751 }; 2752 2753 opp-2 { 2754 opp-peak-kBps = <14236000>; 2755 }; 2756 2757 opp-3 { 2758 opp-peak-kBps = <16265000>; 2759 }; 2760 }; 2761 }; 2762 2763 pmu@90b6400 { 2764 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 2765 reg = <0x0 0x90b6400 0x0 0x600>; 2766 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2767 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2768 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2769 2770 operating-points-v2 = <&cpu_bwmon_opp_table>; 2771 }; 2772 2773 dc_noc: interconnect@90e0000 { 2774 compatible = "qcom,qcs8300-dc-noc"; 2775 reg = <0x0 0x090e0000 0x0 0x5080>; 2776 #interconnect-cells = <2>; 2777 qcom,bcm-voters = <&apps_bcm_voter>; 2778 }; 2779 2780 gem_noc: interconnect@9100000 { 2781 compatible = "qcom,qcs8300-gem-noc"; 2782 reg = <0x0 0x9100000 0x0 0xf7080>; 2783 #interconnect-cells = <2>; 2784 qcom,bcm-voters = <&apps_bcm_voter>; 2785 }; 2786 2787 llcc: system-cache-controller@9200000 { 2788 compatible = "qcom,qcs8300-llcc"; 2789 reg = <0x0 0x09200000 0x0 0x80000>, 2790 <0x0 0x09300000 0x0 0x80000>, 2791 <0x0 0x09400000 0x0 0x80000>, 2792 <0x0 0x09500000 0x0 0x80000>, 2793 <0x0 0x09a00000 0x0 0x80000>; 2794 reg-names = "llcc0_base", 2795 "llcc1_base", 2796 "llcc2_base", 2797 "llcc3_base", 2798 "llcc_broadcast_base"; 2799 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2800 }; 2801 2802 usb_1: usb@a6f8800 { 2803 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; 2804 reg = <0x0 0x0a6f8800 0x0 0x400>; 2805 2806 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2807 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2808 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2809 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2810 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2811 clock-names = "cfg_noc", 2812 "core", 2813 "iface", 2814 "sleep", 2815 "mock_utmi"; 2816 2817 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2818 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2819 assigned-clock-rates = <19200000>, <200000000>; 2820 2821 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 2822 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2823 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2824 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2825 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 2826 interrupt-names = "pwr_event", 2827 "hs_phy_irq", 2828 "dp_hs_phy_irq", 2829 "dm_hs_phy_irq", 2830 "ss_phy_irq"; 2831 2832 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2833 required-opps = <&rpmhpd_opp_nom>; 2834 2835 resets = <&gcc GCC_USB30_PRIM_BCR>; 2836 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 2837 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2838 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2839 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 2840 interconnect-names = "usb-ddr", "apps-usb"; 2841 2842 wakeup-source; 2843 2844 #address-cells = <2>; 2845 #size-cells = <2>; 2846 ranges; 2847 2848 status = "disabled"; 2849 2850 usb_1_dwc3: usb@a600000 { 2851 compatible = "snps,dwc3"; 2852 reg = <0x0 0x0a600000 0x0 0xe000>; 2853 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 2854 iommus = <&apps_smmu 0x80 0x0>; 2855 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 2856 phy-names = "usb2-phy", "usb3-phy"; 2857 snps,dis_enblslpm_quirk; 2858 snps,dis-u1-entry-quirk; 2859 snps,dis-u2-entry-quirk; 2860 snps,dis_u2_susphy_quirk; 2861 snps,dis_u3_susphy_quirk; 2862 }; 2863 }; 2864 2865 usb_2: usb@a4f8800 { 2866 compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; 2867 reg = <0x0 0x0a4f8800 0x0 0x400>; 2868 2869 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 2870 <&gcc GCC_USB20_MASTER_CLK>, 2871 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2872 <&gcc GCC_USB20_SLEEP_CLK>, 2873 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 2874 clock-names = "cfg_noc", 2875 "core", 2876 "iface", 2877 "sleep", 2878 "mock_utmi"; 2879 2880 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 2881 <&gcc GCC_USB20_MASTER_CLK>; 2882 assigned-clock-rates = <19200000>, <120000000>; 2883 2884 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 2885 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 2886 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2887 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2888 interrupt-names = "pwr_event", 2889 "hs_phy_irq", 2890 "dp_hs_phy_irq", 2891 "dm_hs_phy_irq"; 2892 2893 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 2894 required-opps = <&rpmhpd_opp_nom>; 2895 2896 resets = <&gcc GCC_USB20_PRIM_BCR>; 2897 2898 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 2899 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2900 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2901 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 2902 interconnect-names = "usb-ddr", "apps-usb"; 2903 2904 qcom,select-utmi-as-pipe-clk; 2905 wakeup-source; 2906 2907 #address-cells = <2>; 2908 #size-cells = <2>; 2909 ranges; 2910 2911 status = "disabled"; 2912 2913 usb_2_dwc3: usb@a400000 { 2914 compatible = "snps,dwc3"; 2915 reg = <0x0 0x0a400000 0x0 0xe000>; 2916 2917 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 2918 iommus = <&apps_smmu 0x20 0x0>; 2919 2920 phys = <&usb_2_hsphy>; 2921 phy-names = "usb2-phy"; 2922 maximum-speed = "high-speed"; 2923 2924 snps,dis-u1-entry-quirk; 2925 snps,dis-u2-entry-quirk; 2926 snps,dis_u2_susphy_quirk; 2927 snps,dis_u3_susphy_quirk; 2928 snps,dis_enblslpm_quirk; 2929 }; 2930 }; 2931 2932 videocc: clock-controller@abf0000 { 2933 compatible = "qcom,qcs8300-videocc"; 2934 reg = <0x0 0x0abf0000 0x0 0x10000>; 2935 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2936 <&rpmhcc RPMH_CXO_CLK>, 2937 <&rpmhcc RPMH_CXO_CLK_A>, 2938 <&sleep_clk>; 2939 power-domains = <&rpmhpd RPMHPD_MMCX>; 2940 #clock-cells = <1>; 2941 #reset-cells = <1>; 2942 #power-domain-cells = <1>; 2943 }; 2944 2945 camcc: clock-controller@ade0000 { 2946 compatible = "qcom,qcs8300-camcc"; 2947 reg = <0x0 0x0ade0000 0x0 0x20000>; 2948 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2949 <&rpmhcc RPMH_CXO_CLK>, 2950 <&rpmhcc RPMH_CXO_CLK_A>, 2951 <&sleep_clk>; 2952 power-domains = <&rpmhpd RPMHPD_MMCX>; 2953 #clock-cells = <1>; 2954 #reset-cells = <1>; 2955 #power-domain-cells = <1>; 2956 }; 2957 2958 dispcc: clock-controller@af00000 { 2959 compatible = "qcom,sa8775p-dispcc0"; 2960 reg = <0x0 0x0af00000 0x0 0x20000>; 2961 clocks = <&gcc GCC_DISP_AHB_CLK>, 2962 <&rpmhcc RPMH_CXO_CLK>, 2963 <&rpmhcc RPMH_CXO_CLK_A>, 2964 <&sleep_clk>, 2965 <0>, <0>, <0>, <0>, 2966 <0>, <0>, <0>, <0>; 2967 power-domains = <&rpmhpd RPMHPD_MMCX>; 2968 #clock-cells = <1>; 2969 #reset-cells = <1>; 2970 #power-domain-cells = <1>; 2971 }; 2972 2973 pdc: interrupt-controller@b220000 { 2974 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 2975 reg = <0x0 0xb220000 0x0 0x30000>, 2976 <0x0 0x17c000f0 0x0 0x64>; 2977 interrupt-parent = <&intc>; 2978 #interrupt-cells = <2>; 2979 interrupt-controller; 2980 qcom,pdc-ranges = <0 480 40>, 2981 <40 140 14>, 2982 <54 263 1>, 2983 <55 306 4>, 2984 <59 312 3>, 2985 <62 374 2>, 2986 <64 434 2>, 2987 <66 438 2>, 2988 <70 520 1>, 2989 <73 523 1>, 2990 <118 568 6>, 2991 <124 609 3>, 2992 <159 638 1>, 2993 <160 720 3>, 2994 <169 728 30>, 2995 <199 416 2>, 2996 <201 449 1>, 2997 <202 89 1>, 2998 <203 451 1>, 2999 <204 462 1>, 3000 <205 264 1>, 3001 <206 579 1>, 3002 <207 653 1>, 3003 <208 656 1>, 3004 <209 659 1>, 3005 <210 122 1>, 3006 <211 699 1>, 3007 <212 705 1>, 3008 <213 450 1>, 3009 <214 643 2>, 3010 <216 646 5>, 3011 <221 390 5>, 3012 <226 700 2>, 3013 <228 440 1>, 3014 <229 663 1>, 3015 <230 524 2>, 3016 <232 612 3>, 3017 <235 723 5>; 3018 }; 3019 3020 aoss_qmp: power-management@c300000 { 3021 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 3022 reg = <0x0 0x0c300000 0x0 0x400>; 3023 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3024 IPCC_MPROC_SIGNAL_GLINK_QMP 3025 IRQ_TYPE_EDGE_RISING>; 3026 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3027 #clock-cells = <0>; 3028 }; 3029 3030 tlmm: pinctrl@f100000 { 3031 compatible = "qcom,qcs8300-tlmm"; 3032 reg = <0x0 0x0f100000 0x0 0x300000>; 3033 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3034 gpio-controller; 3035 #gpio-cells = <2>; 3036 gpio-ranges = <&tlmm 0 0 134>; 3037 interrupt-controller; 3038 #interrupt-cells = <2>; 3039 wakeup-parent = <&pdc>; 3040 3041 qup_uart7_default: qup-uart7-state { 3042 /* TX, RX */ 3043 pins = "gpio43", "gpio44"; 3044 function = "qup0_se7"; 3045 }; 3046 }; 3047 3048 sram: sram@146d8000 { 3049 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 3050 reg = <0x0 0x146d8000 0x0 0x1000>; 3051 ranges = <0x0 0x0 0x146d8000 0x1000>; 3052 3053 #address-cells = <1>; 3054 #size-cells = <1>; 3055 3056 pil-reloc@94c { 3057 compatible = "qcom,pil-reloc-info"; 3058 reg = <0x94c 0xc8>; 3059 }; 3060 }; 3061 3062 apps_smmu: iommu@15000000 { 3063 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3064 3065 reg = <0x0 0x15000000 0x0 0x100000>; 3066 #iommu-cells = <2>; 3067 #global-interrupts = <2>; 3068 dma-coherent; 3069 3070 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 3200 }; 3201 3202 intc: interrupt-controller@17a00000 { 3203 compatible = "arm,gic-v3"; 3204 reg = <0x0 0x17a00000 0x0 0x10000>, 3205 <0x0 0x17a60000 0x0 0x100000>; 3206 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3207 #interrupt-cells = <3>; 3208 interrupt-controller; 3209 #redistributor-regions = <1>; 3210 redistributor-stride = <0x0 0x20000>; 3211 }; 3212 3213 watchdog@17c10000 { 3214 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 3215 reg = <0x0 0x17c10000 0x0 0x1000>; 3216 clocks = <&sleep_clk>; 3217 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3218 }; 3219 3220 timer@17c20000 { 3221 compatible = "arm,armv7-timer-mem"; 3222 reg = <0x0 0x17c20000 0x0 0x1000>; 3223 ranges = <0x0 0x0 0x0 0x20000000>; 3224 #address-cells = <1>; 3225 #size-cells = <1>; 3226 3227 frame@17c21000 { 3228 reg = <0x17c21000 0x1000>, 3229 <0x17c22000 0x1000>; 3230 frame-number = <0>; 3231 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3233 }; 3234 3235 frame@17c23000 { 3236 reg = <0x17c23000 0x1000>; 3237 frame-number = <1>; 3238 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3239 status = "disabled"; 3240 }; 3241 3242 frame@17c25000 { 3243 reg = <0x17c25000 0x1000>; 3244 frame-number = <2>; 3245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3246 status = "disabled"; 3247 }; 3248 3249 frame@17c27000 { 3250 reg = <0x17c27000 0x1000>; 3251 frame-number = <3>; 3252 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3253 status = "disabled"; 3254 }; 3255 3256 frame@17c29000 { 3257 reg = <0x17c29000 0x1000>; 3258 frame-number = <4>; 3259 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3260 status = "disabled"; 3261 }; 3262 3263 frame@17c2b000 { 3264 reg = <0x17c2b000 0x1000>; 3265 frame-number = <5>; 3266 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3267 status = "disabled"; 3268 }; 3269 3270 frame@17c2d000 { 3271 reg = <0x17c2d000 0x1000>; 3272 frame-number = <6>; 3273 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3274 status = "disabled"; 3275 }; 3276 }; 3277 3278 apps_rsc: rsc@18200000 { 3279 compatible = "qcom,rpmh-rsc"; 3280 reg = <0x0 0x18200000 0x0 0x10000>, 3281 <0x0 0x18210000 0x0 0x10000>, 3282 <0x0 0x18220000 0x0 0x10000>; 3283 reg-names = "drv-0", 3284 "drv-1", 3285 "drv-2"; 3286 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3289 3290 power-domains = <&system_pd>; 3291 label = "apps_rsc"; 3292 3293 qcom,tcs-offset = <0xd00>; 3294 qcom,drv-id = <2>; 3295 qcom,tcs-config = <ACTIVE_TCS 2>, 3296 <SLEEP_TCS 3>, 3297 <WAKE_TCS 3>, 3298 <CONTROL_TCS 0>; 3299 3300 apps_bcm_voter: bcm-voter { 3301 compatible = "qcom,bcm-voter"; 3302 }; 3303 3304 rpmhcc: clock-controller { 3305 compatible = "qcom,sa8775p-rpmh-clk"; 3306 #clock-cells = <1>; 3307 clocks = <&xo_board_clk>; 3308 clock-names = "xo"; 3309 }; 3310 3311 rpmhpd: power-controller { 3312 compatible = "qcom,qcs8300-rpmhpd"; 3313 #power-domain-cells = <1>; 3314 operating-points-v2 = <&rpmhpd_opp_table>; 3315 3316 rpmhpd_opp_table: opp-table { 3317 compatible = "operating-points-v2"; 3318 3319 rpmhpd_opp_ret: opp-0 { 3320 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3321 }; 3322 3323 rpmhpd_opp_min_svs: opp-1 { 3324 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3325 }; 3326 3327 rpmhpd_opp_low_svs: opp-2 { 3328 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3329 }; 3330 3331 rpmhpd_opp_svs: opp-3 { 3332 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3333 }; 3334 3335 rpmhpd_opp_svs_l1: opp-4 { 3336 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3337 }; 3338 3339 rpmhpd_opp_nom: opp-5 { 3340 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3341 }; 3342 3343 rpmhpd_opp_nom_l1: opp-6 { 3344 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3345 }; 3346 3347 rpmhpd_opp_nom_l2: opp-7 { 3348 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3349 }; 3350 3351 rpmhpd_opp_turbo: opp-8 { 3352 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3353 }; 3354 3355 rpmhpd_opp_turbo_l1: opp-9 { 3356 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3357 }; 3358 }; 3359 }; 3360 }; 3361 3362 remoteproc_gpdsp: remoteproc@20c00000 { 3363 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 3364 reg = <0x0 0x20c00000 0x0 0x10000>; 3365 3366 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 3367 <&smp2p_gpdsp_in 0 0>, 3368 <&smp2p_gpdsp_in 1 0>, 3369 <&smp2p_gpdsp_in 2 0>, 3370 <&smp2p_gpdsp_in 3 0>; 3371 interrupt-names = "wdog", 3372 "fatal", 3373 "ready", 3374 "handover", 3375 "stop-ack"; 3376 3377 clocks = <&rpmhcc RPMH_CXO_CLK>; 3378 clock-names = "xo"; 3379 3380 power-domains = <&rpmhpd RPMHPD_CX>, 3381 <&rpmhpd RPMHPD_MXC>; 3382 power-domain-names = "cx", 3383 "mxc"; 3384 3385 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 3386 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 3387 3388 memory-region = <&gpdsp_mem>; 3389 3390 qcom,qmp = <&aoss_qmp>; 3391 3392 qcom,smem-states = <&smp2p_gpdsp_out 0>; 3393 qcom,smem-state-names = "stop"; 3394 3395 status = "disabled"; 3396 3397 glink-edge { 3398 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 3399 IPCC_MPROC_SIGNAL_GLINK_QMP 3400 IRQ_TYPE_EDGE_RISING>; 3401 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 3402 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3403 3404 label = "gpdsp"; 3405 qcom,remote-pid = <17>; 3406 }; 3407 }; 3408 3409 ethernet0: ethernet@23040000 { 3410 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 3411 reg = <0x0 0x23040000 0x0 0x00010000>, 3412 <0x0 0x23056000 0x0 0x00000100>; 3413 reg-names = "stmmaceth", "rgmii"; 3414 3415 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 3417 interrupt-names = "macirq", "sfty"; 3418 3419 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 3420 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 3421 <&gcc GCC_EMAC0_PTP_CLK>, 3422 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 3423 clock-names = "stmmaceth", 3424 "pclk", 3425 "ptp_ref", 3426 "phyaux"; 3427 power-domains = <&gcc GCC_EMAC0_GDSC>; 3428 3429 phys = <&serdes0>; 3430 phy-names = "serdes"; 3431 3432 iommus = <&apps_smmu 0x120 0xf>; 3433 dma-coherent; 3434 3435 snps,tso; 3436 snps,pbl = <32>; 3437 rx-fifo-depth = <16384>; 3438 tx-fifo-depth = <20480>; 3439 3440 status = "disabled"; 3441 }; 3442 3443 nspa_noc: interconnect@260c0000 { 3444 compatible = "qcom,qcs8300-nspa-noc"; 3445 reg = <0x0 0x260c0000 0x0 0x16080>; 3446 #interconnect-cells = <2>; 3447 qcom,bcm-voters = <&apps_bcm_voter>; 3448 }; 3449 3450 remoteproc_cdsp: remoteproc@26300000 { 3451 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 3452 reg = <0x0 0x26300000 0x0 0x10000>; 3453 3454 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3455 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3456 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3457 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3458 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3459 interrupt-names = "wdog", 3460 "fatal", 3461 "ready", 3462 "handover", 3463 "stop-ack"; 3464 3465 clocks = <&rpmhcc RPMH_CXO_CLK>; 3466 clock-names = "xo"; 3467 3468 power-domains = <&rpmhpd RPMHPD_CX>, 3469 <&rpmhpd RPMHPD_MXC>, 3470 <&rpmhpd RPMHPD_NSP0>; 3471 3472 power-domain-names = "cx", 3473 "mxc", 3474 "nsp"; 3475 3476 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 3477 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3478 3479 memory-region = <&cdsp_mem>; 3480 3481 qcom,qmp = <&aoss_qmp>; 3482 3483 qcom,smem-states = <&smp2p_cdsp_out 0>; 3484 qcom,smem-state-names = "stop"; 3485 3486 status = "disabled"; 3487 3488 glink-edge { 3489 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3490 IPCC_MPROC_SIGNAL_GLINK_QMP 3491 IRQ_TYPE_EDGE_RISING>; 3492 mboxes = <&ipcc IPCC_CLIENT_CDSP 3493 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3494 3495 label = "cdsp"; 3496 qcom,remote-pid = <5>; 3497 3498 fastrpc { 3499 compatible = "qcom,fastrpc"; 3500 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3501 label = "cdsp"; 3502 #address-cells = <1>; 3503 #size-cells = <0>; 3504 3505 compute-cb@1 { 3506 compatible = "qcom,fastrpc-compute-cb"; 3507 reg = <1>; 3508 iommus = <&apps_smmu 0x19c1 0x0440>, 3509 <&apps_smmu 0x1961 0x0400>; 3510 dma-coherent; 3511 }; 3512 3513 compute-cb@2 { 3514 compatible = "qcom,fastrpc-compute-cb"; 3515 reg = <2>; 3516 iommus = <&apps_smmu 0x19c2 0x0440>, 3517 <&apps_smmu 0x1962 0x0400>; 3518 dma-coherent; 3519 }; 3520 3521 compute-cb@3 { 3522 compatible = "qcom,fastrpc-compute-cb"; 3523 reg = <3>; 3524 iommus = <&apps_smmu 0x19c3 0x0440>, 3525 <&apps_smmu 0x1963 0x0400>; 3526 dma-coherent; 3527 }; 3528 3529 compute-cb@4 { 3530 compatible = "qcom,fastrpc-compute-cb"; 3531 reg = <4>; 3532 iommus = <&apps_smmu 0x19c4 0x0440>, 3533 <&apps_smmu 0x1964 0x0400>; 3534 dma-coherent; 3535 }; 3536 }; 3537 }; 3538 }; 3539 }; 3540 3541 timer { 3542 compatible = "arm,armv8-timer"; 3543 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3544 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3545 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3546 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3547 }; 3548}; 3549