1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs615-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/interconnect/qcom,icc.h> 10#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/power/qcom,rpmhpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 power-domains = <&cpu_pd0>; 31 power-domain-names = "psci"; 32 capacity-dmips-mhz = <1024>; 33 dynamic-power-coefficient = <100>; 34 next-level-cache = <&l2_0>; 35 #cooling-cells = <2>; 36 37 l2_0: l2-cache { 38 compatible = "cache"; 39 cache-level = <2>; 40 cache-unified; 41 next-level-cache = <&l3_0>; 42 }; 43 }; 44 45 cpu1: cpu@100 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a55"; 48 reg = <0x0 0x100>; 49 enable-method = "psci"; 50 power-domains = <&cpu_pd1>; 51 power-domain-names = "psci"; 52 capacity-dmips-mhz = <1024>; 53 dynamic-power-coefficient = <100>; 54 next-level-cache = <&l2_100>; 55 56 l2_100: l2-cache { 57 compatible = "cache"; 58 cache-level = <2>; 59 cache-unified; 60 next-level-cache = <&l3_0>; 61 }; 62 }; 63 64 cpu2: cpu@200 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x0 0x200>; 68 enable-method = "psci"; 69 power-domains = <&cpu_pd2>; 70 power-domain-names = "psci"; 71 capacity-dmips-mhz = <1024>; 72 dynamic-power-coefficient = <100>; 73 next-level-cache = <&l2_200>; 74 75 l2_200: l2-cache { 76 compatible = "cache"; 77 cache-level = <2>; 78 cache-unified; 79 next-level-cache = <&l3_0>; 80 }; 81 }; 82 83 cpu3: cpu@300 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x0 0x300>; 87 enable-method = "psci"; 88 power-domains = <&cpu_pd3>; 89 power-domain-names = "psci"; 90 capacity-dmips-mhz = <1024>; 91 dynamic-power-coefficient = <100>; 92 next-level-cache = <&l2_300>; 93 94 l2_300: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_0>; 99 }; 100 }; 101 102 cpu4: cpu@400 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a55"; 105 reg = <0x0 0x400>; 106 enable-method = "psci"; 107 power-domains = <&cpu_pd4>; 108 power-domain-names = "psci"; 109 capacity-dmips-mhz = <1024>; 110 dynamic-power-coefficient = <100>; 111 next-level-cache = <&l2_400>; 112 113 l2_400: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&l3_0>; 118 }; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x0 0x500>; 125 enable-method = "psci"; 126 power-domains = <&cpu_pd5>; 127 power-domain-names = "psci"; 128 capacity-dmips-mhz = <1024>; 129 dynamic-power-coefficient = <100>; 130 next-level-cache = <&l2_500>; 131 132 l2_500: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&l3_0>; 137 }; 138 }; 139 140 cpu6: cpu@600 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a76"; 143 reg = <0x0 0x600>; 144 enable-method = "psci"; 145 power-domains = <&cpu_pd6>; 146 power-domain-names = "psci"; 147 capacity-dmips-mhz = <1740>; 148 dynamic-power-coefficient = <404>; 149 next-level-cache = <&l2_600>; 150 #cooling-cells = <2>; 151 152 l2_600: l2-cache { 153 compatible = "cache"; 154 cache-level = <2>; 155 cache-unified; 156 next-level-cache = <&l3_0>; 157 }; 158 }; 159 160 cpu7: cpu@700 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a76"; 163 reg = <0x0 0x700>; 164 enable-method = "psci"; 165 power-domains = <&cpu_pd7>; 166 power-domain-names = "psci"; 167 capacity-dmips-mhz = <1740>; 168 dynamic-power-coefficient = <404>; 169 next-level-cache = <&l2_700>; 170 171 l2_700: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu-map { 180 cluster0 { 181 core0 { 182 cpu = <&cpu0>; 183 }; 184 185 core1 { 186 cpu = <&cpu1>; 187 }; 188 189 core2 { 190 cpu = <&cpu2>; 191 }; 192 193 core3 { 194 cpu = <&cpu3>; 195 }; 196 197 core4 { 198 cpu = <&cpu4>; 199 }; 200 201 core5 { 202 cpu = <&cpu5>; 203 }; 204 205 core6 { 206 cpu = <&cpu6>; 207 }; 208 209 core7 { 210 cpu = <&cpu7>; 211 }; 212 }; 213 }; 214 215 l3_0: l3-cache { 216 compatible = "cache"; 217 cache-level = <3>; 218 cache-unified; 219 }; 220 }; 221 222 dummy_eud: dummy-sink { 223 compatible = "arm,coresight-dummy-sink"; 224 225 in-ports { 226 port { 227 eud_in: endpoint { 228 remote-endpoint = <&replicator_swao_out1>; 229 }; 230 }; 231 }; 232 }; 233 234 idle-states { 235 entry-method = "psci"; 236 237 little_cpu_sleep_0: cpu-sleep-0-0 { 238 compatible = "arm,idle-state"; 239 idle-state-name = "silver-power-collapse"; 240 arm,psci-suspend-param = <0x40000003>; 241 entry-latency-us = <549>; 242 exit-latency-us = <901>; 243 min-residency-us = <1774>; 244 local-timer-stop; 245 }; 246 247 little_cpu_sleep_1: cpu-sleep-0-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "silver-rail-power-collapse"; 250 arm,psci-suspend-param = <0x40000004>; 251 entry-latency-us = <702>; 252 exit-latency-us = <915>; 253 min-residency-us = <4001>; 254 local-timer-stop; 255 }; 256 257 big_cpu_sleep_0: cpu-sleep-1-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "gold-power-collapse"; 260 arm,psci-suspend-param = <0x40000003>; 261 entry-latency-us = <523>; 262 exit-latency-us = <1244>; 263 min-residency-us = <2207>; 264 local-timer-stop; 265 }; 266 267 big_cpu_sleep_1: cpu-sleep-1-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "gold-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <526>; 272 exit-latency-us = <1854>; 273 min-residency-us = <5555>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 cluster_sleep_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x41000044>; 282 entry-latency-us = <2752>; 283 exit-latency-us = <3048>; 284 min-residency-us = <6118>; 285 }; 286 287 cluster_sleep_1: cluster-sleep-1 { 288 compatible = "domain-idle-state"; 289 arm,psci-suspend-param = <0x41001344>; 290 entry-latency-us = <3263>; 291 exit-latency-us = <4562>; 292 min-residency-us = <8467>; 293 }; 294 295 cluster_sleep_2: cluster-sleep-2 { 296 compatible = "domain-idle-state"; 297 arm,psci-suspend-param = <0x4100b344>; 298 entry-latency-us = <3638>; 299 exit-latency-us = <6562>; 300 min-residency-us = <9826>; 301 }; 302 }; 303 304 memory@80000000 { 305 device_type = "memory"; 306 /* We expect the bootloader to fill in the size */ 307 reg = <0 0x80000000 0 0>; 308 }; 309 310 firmware { 311 scm { 312 compatible = "qcom,scm-qcs615", "qcom,scm"; 313 qcom,dload-mode = <&tcsr 0x13000>; 314 }; 315 }; 316 317 camnoc_virt: interconnect-0 { 318 compatible = "qcom,qcs615-camnoc-virt"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 ipa_virt: interconnect-1 { 324 compatible = "qcom,qcs615-ipa-virt"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 mc_virt: interconnect-2 { 330 compatible = "qcom,qcs615-mc-virt"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 qup_opp_table: opp-table-qup { 336 compatible = "operating-points-v2"; 337 opp-shared; 338 339 opp-75000000 { 340 opp-hz = /bits/ 64 <75000000>; 341 required-opps = <&rpmhpd_opp_low_svs>; 342 }; 343 344 opp-100000000 { 345 opp-hz = /bits/ 64 <100000000>; 346 required-opps = <&rpmhpd_opp_svs>; 347 }; 348 349 opp-128000000 { 350 opp-hz = /bits/ 64 <128000000>; 351 required-opps = <&rpmhpd_opp_nom>; 352 }; 353 }; 354 355 psci { 356 compatible = "arm,psci-1.0"; 357 method = "smc"; 358 359 cpu_pd0: power-domain-cpu0 { 360 #power-domain-cells = <0>; 361 power-domains = <&cluster_pd>; 362 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 363 }; 364 365 cpu_pd1: power-domain-cpu1 { 366 #power-domain-cells = <0>; 367 power-domains = <&cluster_pd>; 368 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 369 }; 370 371 cpu_pd2: power-domain-cpu2 { 372 #power-domain-cells = <0>; 373 power-domains = <&cluster_pd>; 374 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 375 }; 376 377 cpu_pd3: power-domain-cpu3 { 378 #power-domain-cells = <0>; 379 power-domains = <&cluster_pd>; 380 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 381 }; 382 383 cpu_pd4: power-domain-cpu4 { 384 #power-domain-cells = <0>; 385 power-domains = <&cluster_pd>; 386 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 387 }; 388 389 cpu_pd5: power-domain-cpu5 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster_pd>; 392 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 393 }; 394 395 cpu_pd6: power-domain-cpu6 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster_pd>; 398 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 399 }; 400 401 cpu_pd7: power-domain-cpu7 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster_pd>; 404 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 405 }; 406 407 cluster_pd: power-domain-cluster { 408 #power-domain-cells = <0>; 409 domain-idle-states = <&cluster_sleep_0 410 &cluster_sleep_1 411 &cluster_sleep_2>; 412 }; 413 }; 414 415 reserved-memory { 416 #address-cells = <2>; 417 #size-cells = <2>; 418 ranges; 419 420 smem_region: smem@86000000 { 421 compatible = "qcom,smem"; 422 reg = <0x0 0x86000000 0x0 0x200000>; 423 no-map; 424 hwlocks = <&tcsr_mutex 3>; 425 }; 426 }; 427 428 soc: soc@0 { 429 compatible = "simple-bus"; 430 ranges = <0 0 0 0 0x10 0>; 431 dma-ranges = <0 0 0 0 0x10 0>; 432 #address-cells = <2>; 433 #size-cells = <2>; 434 435 gcc: clock-controller@100000 { 436 compatible = "qcom,qcs615-gcc"; 437 reg = <0 0x00100000 0 0x1f0000>; 438 439 #clock-cells = <1>; 440 #reset-cells = <1>; 441 #power-domain-cells = <1>; 442 }; 443 444 qfprom: efuse@780000 { 445 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 446 reg = <0x0 0x00780000 0x0 0x7000>; 447 #address-cells = <1>; 448 #size-cells = <1>; 449 450 qusb2_hstx_trim: hstx-trim@1f8 { 451 reg = <0x1fb 0x1>; 452 bits = <1 4>; 453 }; 454 }; 455 456 sdhc_1: mmc@7c4000 { 457 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 458 reg = <0x0 0x007c4000 0x0 0x1000>, 459 <0x0 0x007c5000 0x0 0x1000>, 460 <0x0 0x007c8000 0x0 0x8000>; 461 reg-names = "hc", 462 "cqhci", 463 "ice"; 464 465 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-names = "hc_irq", 468 "pwr_irq"; 469 470 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 471 <&gcc GCC_SDCC1_APPS_CLK>, 472 <&rpmhcc RPMH_CXO_CLK>, 473 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 474 clock-names = "iface", 475 "core", 476 "xo", 477 "ice"; 478 479 resets = <&gcc GCC_SDCC1_BCR>; 480 481 power-domains = <&rpmhpd RPMHPD_CX>; 482 operating-points-v2 = <&sdhc1_opp_table>; 483 iommus = <&apps_smmu 0x02c0 0x0>; 484 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 485 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 487 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 488 interconnect-names = "sdhc-ddr", 489 "cpu-sdhc"; 490 491 qcom,dll-config = <0x000f642c>; 492 qcom,ddr-config = <0x80040868>; 493 supports-cqe; 494 dma-coherent; 495 496 status = "disabled"; 497 498 sdhc1_opp_table: opp-table { 499 compatible = "operating-points-v2"; 500 501 opp-50000000 { 502 opp-hz = /bits/ 64 <50000000>; 503 required-opps = <&rpmhpd_opp_low_svs>; 504 }; 505 506 opp-100000000 { 507 opp-hz = /bits/ 64 <100000000>; 508 required-opps = <&rpmhpd_opp_svs>; 509 }; 510 511 opp-200000000 { 512 opp-hz = /bits/ 64 <200000000>; 513 required-opps = <&rpmhpd_opp_svs_l1>; 514 }; 515 516 opp-384000000 { 517 opp-hz = /bits/ 64 <384000000>; 518 required-opps = <&rpmhpd_opp_nom>; 519 }; 520 }; 521 }; 522 523 gpi_dma0: dma-controller@800000 { 524 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 525 reg = <0x0 0x800000 0x0 0x60000>; 526 #dma-cells = <3>; 527 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 535 dma-channels = <8>; 536 dma-channel-mask = <0xf>; 537 iommus = <&apps_smmu 0xd6 0x0>; 538 status = "disabled"; 539 }; 540 541 qupv3_id_0: geniqup@8c0000 { 542 compatible = "qcom,geni-se-qup"; 543 reg = <0x0 0x008c0000 0x0 0x6000>; 544 ranges; 545 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 546 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 547 clock-names = "m-ahb", 548 "s-ahb"; 549 iommus = <&apps_smmu 0xc3 0x0>; 550 #address-cells = <2>; 551 #size-cells = <2>; 552 status = "disabled"; 553 554 uart0: serial@880000 { 555 compatible = "qcom,geni-debug-uart"; 556 reg = <0x0 0x00880000 0x0 0x4000>; 557 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 558 clock-names = "se"; 559 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 560 pinctrl-names = "default"; 561 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 562 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 563 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 564 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 565 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 566 interconnect-names = "qup-core", 567 "qup-config"; 568 power-domains = <&rpmhpd RPMHPD_CX>; 569 status = "disabled"; 570 }; 571 572 i2c1: i2c@884000 { 573 compatible = "qcom,geni-i2c"; 574 reg = <0x0 0x884000 0x0 0x4000>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 579 clock-names = "se"; 580 pinctrl-0 = <&qup_i2c1_data_clk>; 581 pinctrl-names = "default"; 582 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 583 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 584 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 585 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 586 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 587 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 588 interconnect-names = "qup-core", 589 "qup-config", 590 "qup-memory"; 591 power-domains = <&rpmhpd RPMHPD_CX>; 592 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 593 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 594 dma-names = "tx", 595 "rx"; 596 status = "disabled"; 597 }; 598 599 i2c2: i2c@888000 { 600 compatible = "qcom,geni-i2c"; 601 reg = <0x0 0x888000 0x0 0x4000>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 606 clock-names = "se"; 607 pinctrl-0 = <&qup_i2c2_data_clk>; 608 pinctrl-names = "default"; 609 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 610 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 611 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 612 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 613 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 614 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 615 interconnect-names = "qup-core", 616 "qup-config", 617 "qup-memory"; 618 power-domains = <&rpmhpd RPMHPD_CX>; 619 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 620 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 621 dma-names = "tx", 622 "rx"; 623 status = "disabled"; 624 }; 625 626 spi2: spi@888000 { 627 compatible = "qcom,geni-spi"; 628 reg = <0x0 0x00888000 0x0 0x4000>; 629 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 631 clock-names = "se"; 632 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 633 pinctrl-names = "default"; 634 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 635 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 636 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 637 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 638 interconnect-names = "qup-core", 639 "qup-config"; 640 power-domains = <&rpmhpd RPMHPD_CX>; 641 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 642 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 643 dma-names = "tx", 644 "rx"; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 status = "disabled"; 648 }; 649 650 uart2: serial@888000 { 651 compatible = "qcom,geni-uart"; 652 reg = <0x0 0x00888000 0x0 0x4000>; 653 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 655 clock-names = "se"; 656 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 657 <&qup_uart2_tx>, <&qup_uart2_rx>; 658 pinctrl-names = "default"; 659 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 660 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 661 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 662 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 663 interconnect-names = "qup-core", 664 "qup-config"; 665 power-domains = <&rpmhpd RPMHPD_CX>; 666 status = "disabled"; 667 }; 668 669 i2c3: i2c@88c000 { 670 compatible = "qcom,geni-i2c"; 671 reg = <0x0 0x88c000 0x0 0x4000>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 676 clock-names = "se"; 677 pinctrl-0 = <&qup_i2c3_data_clk>; 678 pinctrl-names = "default"; 679 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 680 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 681 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 682 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 683 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 684 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 685 interconnect-names = "qup-core", 686 "qup-config", 687 "qup-memory"; 688 power-domains = <&rpmhpd RPMHPD_CX>; 689 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 690 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 691 dma-names = "tx", 692 "rx"; 693 status = "disabled"; 694 }; 695 }; 696 697 gpi_dma1: dma-controller@a00000 { 698 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 699 reg = <0x0 0xa00000 0x0 0x60000>; 700 #dma-cells = <3>; 701 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 709 dma-channels = <8>; 710 dma-channel-mask = <0xf>; 711 iommus = <&apps_smmu 0x376 0x0>; 712 status = "disabled"; 713 }; 714 715 qupv3_id_1: geniqup@ac0000 { 716 compatible = "qcom,geni-se-qup"; 717 reg = <0x0 0xac0000 0x0 0x2000>; 718 ranges; 719 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 720 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 721 clock-names = "m-ahb", 722 "s-ahb"; 723 iommus = <&apps_smmu 0x363 0x0>; 724 #address-cells = <2>; 725 #size-cells = <2>; 726 status = "disabled"; 727 728 i2c4: i2c@a80000 { 729 compatible = "qcom,geni-i2c"; 730 reg = <0x0 0xa80000 0x0 0x4000>; 731 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 732 clock-names = "se"; 733 pinctrl-0 = <&qup_i2c4_data_clk>; 734 pinctrl-names = "default"; 735 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 739 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 740 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 741 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 742 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 743 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 744 interconnect-names = "qup-core", 745 "qup-config", 746 "qup-memory"; 747 power-domains = <&rpmhpd RPMHPD_CX>; 748 required-opps = <&rpmhpd_opp_low_svs>; 749 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 750 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 751 dma-names = "tx", 752 "rx"; 753 status = "disabled"; 754 }; 755 756 spi4: spi@a80000 { 757 compatible = "qcom,geni-spi"; 758 reg = <0x0 0xa80000 0x0 0x4000>; 759 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 760 clock-names = "se"; 761 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 762 pinctrl-names = "default"; 763 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 768 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 769 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 770 interconnect-names = "qup-core", 771 "qup-config"; 772 power-domains = <&rpmhpd RPMHPD_CX>; 773 operating-points-v2 = <&qup_opp_table>; 774 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 775 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 776 dma-names = "tx", 777 "rx"; 778 status = "disabled"; 779 }; 780 781 uart4: serial@a80000 { 782 compatible = "qcom,geni-uart"; 783 reg = <0x0 0xa80000 0x0 0x4000>; 784 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 785 clock-names = "se"; 786 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 787 <&qup_uart4_tx>, <&qup_uart4_rx>; 788 pinctrl-names = "default"; 789 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 790 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 791 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 792 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 793 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 794 interconnect-names = "qup-core", 795 "qup-config"; 796 power-domains = <&rpmhpd RPMHPD_CX>; 797 operating-points-v2 = <&qup_opp_table>; 798 status = "disabled"; 799 }; 800 801 i2c5: i2c@a84000 { 802 compatible = "qcom,geni-i2c"; 803 reg = <0x0 0xa84000 0x0 0x4000>; 804 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 805 clock-names = "se"; 806 pinctrl-0 = <&qup_i2c5_data_clk>; 807 pinctrl-names = "default"; 808 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 812 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 813 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 814 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 815 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 816 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 817 interconnect-names = "qup-core", 818 "qup-config", 819 "qup-memory"; 820 power-domains = <&rpmhpd RPMHPD_CX>; 821 required-opps = <&rpmhpd_opp_low_svs>; 822 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 823 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 824 dma-names = "tx", 825 "rx"; 826 status = "disabled"; 827 }; 828 829 i2c6: i2c@a88000 { 830 compatible = "qcom,geni-i2c"; 831 reg = <0x0 0xa88000 0x0 0x4000>; 832 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 833 clock-names = "se"; 834 pinctrl-0 = <&qup_i2c6_data_clk>; 835 pinctrl-names = "default"; 836 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 840 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 841 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 842 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 843 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 844 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 845 interconnect-names = "qup-core", 846 "qup-config", 847 "qup-memory"; 848 power-domains = <&rpmhpd RPMHPD_CX>; 849 required-opps = <&rpmhpd_opp_low_svs>; 850 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 851 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 852 dma-names = "tx", 853 "rx"; 854 status = "disabled"; 855 }; 856 857 spi6: spi@a88000 { 858 compatible = "qcom,geni-spi"; 859 reg = <0x0 0xa88000 0x0 0x4000>; 860 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 861 clock-names = "se"; 862 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 863 pinctrl-names = "default"; 864 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 868 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 869 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 870 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 871 interconnect-names = "qup-core", 872 "qup-config"; 873 power-domains = <&rpmhpd RPMHPD_CX>; 874 operating-points-v2 = <&qup_opp_table>; 875 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 876 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 877 dma-names = "tx", 878 "rx"; 879 status = "disabled"; 880 }; 881 882 uart6: serial@a88000 { 883 compatible = "qcom,geni-uart"; 884 reg = <0x0 0xa88000 0x0 0x4000>; 885 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 886 clock-names = "se"; 887 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 888 <&qup_uart6_tx>, <&qup_uart6_rx>; 889 pinctrl-names = "default"; 890 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 891 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 892 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 893 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 894 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 895 interconnect-names = "qup-core", 896 "qup-config"; 897 power-domains = <&rpmhpd RPMHPD_CX>; 898 operating-points-v2 = <&qup_opp_table>; 899 status = "disabled"; 900 }; 901 902 i2c7: i2c@a8c000 { 903 compatible = "qcom,geni-i2c"; 904 reg = <0x0 0xa8c000 0x0 0x4000>; 905 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 906 clock-names = "se"; 907 pinctrl-0 = <&qup_i2c7_data_clk>; 908 pinctrl-names = "default"; 909 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 913 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 915 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 916 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 918 interconnect-names = "qup-core", 919 "qup-config", 920 "qup-memory"; 921 power-domains = <&rpmhpd RPMHPD_CX>; 922 required-opps = <&rpmhpd_opp_low_svs>; 923 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 924 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 925 dma-names = "tx", 926 "rx"; 927 status = "disabled"; 928 }; 929 930 spi7: spi@a8c000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0x0 0xa8c000 0x0 0x4000>; 933 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 934 clock-names = "se"; 935 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 936 pinctrl-names = "default"; 937 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 941 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 942 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 943 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 944 interconnect-names = "qup-core", 945 "qup-config"; 946 power-domains = <&rpmhpd RPMHPD_CX>; 947 operating-points-v2 = <&qup_opp_table>; 948 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 949 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 950 dma-names = "tx", 951 "rx"; 952 status = "disabled"; 953 }; 954 955 uart7: serial@a8c000 { 956 compatible = "qcom,geni-uart"; 957 reg = <0x0 0xa8c000 0x0 0x4000>; 958 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 959 clock-names = "se"; 960 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 961 <&qup_uart7_tx>, <&qup_uart7_rx>; 962 pinctrl-names = "default"; 963 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 964 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 965 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 966 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 967 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 968 interconnect-names = "qup-core", 969 "qup-config"; 970 power-domains = <&rpmhpd RPMHPD_CX>; 971 operating-points-v2 = <&qup_opp_table>; 972 status = "disabled"; 973 }; 974 }; 975 976 config_noc: interconnect@1500000 { 977 reg = <0x0 0x01500000 0x0 0x5080>; 978 compatible = "qcom,qcs615-config-noc"; 979 #interconnect-cells = <2>; 980 qcom,bcm-voters = <&apps_bcm_voter>; 981 }; 982 983 system_noc: interconnect@1620000 { 984 reg = <0x0 0x01620000 0x0 0x1f300>; 985 compatible = "qcom,qcs615-system-noc"; 986 #interconnect-cells = <2>; 987 qcom,bcm-voters = <&apps_bcm_voter>; 988 }; 989 990 aggre1_noc: interconnect@1700000 { 991 reg = <0x0 0x01700000 0x0 0x3f200>; 992 compatible = "qcom,qcs615-aggre1-noc"; 993 #interconnect-cells = <2>; 994 qcom,bcm-voters = <&apps_bcm_voter>; 995 }; 996 997 mmss_noc: interconnect@1740000 { 998 reg = <0x0 0x01740000 0x0 0x1c100>; 999 compatible = "qcom,qcs615-mmss-noc"; 1000 #interconnect-cells = <2>; 1001 qcom,bcm-voters = <&apps_bcm_voter>; 1002 }; 1003 1004 ufs_mem_hc: ufshc@1d84000 { 1005 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1006 reg = <0x0 0x01d84000 0x0 0x3000>, 1007 <0x0 0x01d90000 0x0 0x8000>; 1008 reg-names = "std", 1009 "ice"; 1010 1011 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1012 1013 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1014 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1015 <&gcc GCC_UFS_PHY_AHB_CLK>, 1016 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1017 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 1018 <&rpmhcc RPMH_CXO_CLK>, 1019 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1020 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1021 clock-names = "core_clk", 1022 "bus_aggr_clk", 1023 "iface_clk", 1024 "core_clk_unipro", 1025 "core_clk_ice", 1026 "ref_clk", 1027 "tx_lane0_sync_clk", 1028 "rx_lane0_sync_clk"; 1029 1030 resets = <&gcc GCC_UFS_PHY_BCR>; 1031 reset-names = "rst"; 1032 1033 operating-points-v2 = <&ufs_opp_table>; 1034 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1035 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1036 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1037 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1038 interconnect-names = "ufs-ddr", 1039 "cpu-ufs"; 1040 1041 power-domains = <&gcc UFS_PHY_GDSC>; 1042 1043 iommus = <&apps_smmu 0x300 0x0>; 1044 dma-coherent; 1045 1046 lanes-per-direction = <1>; 1047 1048 phys = <&ufs_mem_phy>; 1049 phy-names = "ufsphy"; 1050 1051 #reset-cells = <1>; 1052 1053 status = "disabled"; 1054 1055 ufs_opp_table: opp-table { 1056 compatible = "operating-points-v2"; 1057 1058 opp-50000000 { 1059 opp-hz = /bits/ 64 <50000000>, 1060 /bits/ 64 <0>, 1061 /bits/ 64 <0>, 1062 /bits/ 64 <37500000>, 1063 /bits/ 64 <75000000>, 1064 /bits/ 64 <0>, 1065 /bits/ 64 <0>, 1066 /bits/ 64 <0>; 1067 required-opps = <&rpmhpd_opp_low_svs>; 1068 }; 1069 1070 opp-100000000 { 1071 opp-hz = /bits/ 64 <100000000>, 1072 /bits/ 64 <0>, 1073 /bits/ 64 <0>, 1074 /bits/ 64 <75000000>, 1075 /bits/ 64 <150000000>, 1076 /bits/ 64 <0>, 1077 /bits/ 64 <0>, 1078 /bits/ 64 <0>; 1079 required-opps = <&rpmhpd_opp_svs>; 1080 }; 1081 1082 opp-200000000 { 1083 opp-hz = /bits/ 64 <200000000>, 1084 /bits/ 64 <0>, 1085 /bits/ 64 <0>, 1086 /bits/ 64 <150000000>, 1087 /bits/ 64 <300000000>, 1088 /bits/ 64 <0>, 1089 /bits/ 64 <0>, 1090 /bits/ 64 <0>; 1091 required-opps = <&rpmhpd_opp_nom>; 1092 }; 1093 }; 1094 }; 1095 1096 ufs_mem_phy: phy@1d87000 { 1097 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1098 reg = <0x0 0x01d87000 0x0 0xe00>; 1099 clocks = <&rpmhcc RPMH_CXO_CLK>, 1100 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1101 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1102 clock-names = "ref", 1103 "ref_aux", 1104 "qref"; 1105 1106 power-domains = <&gcc UFS_PHY_GDSC>; 1107 1108 resets = <&ufs_mem_hc 0>; 1109 reset-names = "ufsphy"; 1110 1111 #clock-cells = <1>; 1112 #phy-cells = <0>; 1113 1114 status = "disabled"; 1115 }; 1116 1117 tcsr_mutex: hwlock@1f40000 { 1118 compatible = "qcom,tcsr-mutex"; 1119 reg = <0x0 0x01f40000 0x0 0x20000>; 1120 #hwlock-cells = <1>; 1121 }; 1122 1123 tcsr: syscon@1fc0000 { 1124 compatible = "qcom,qcs615-tcsr", "syscon"; 1125 reg = <0x0 0x01fc0000 0x0 0x30000>; 1126 }; 1127 1128 tlmm: pinctrl@3100000 { 1129 compatible = "qcom,qcs615-tlmm"; 1130 reg = <0x0 0x03100000 0x0 0x300000>, 1131 <0x0 0x03500000 0x0 0x300000>, 1132 <0x0 0x03d00000 0x0 0x300000>; 1133 reg-names = "east", 1134 "west", 1135 "south"; 1136 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1137 gpio-ranges = <&tlmm 0 0 124>; 1138 gpio-controller; 1139 #gpio-cells = <2>; 1140 interrupt-controller; 1141 #interrupt-cells = <2>; 1142 wakeup-parent = <&pdc>; 1143 1144 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1145 pins = "gpio4", "gpio5"; 1146 function = "qup0"; 1147 1148 }; 1149 1150 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1151 pins = "gpio0", "gpio1"; 1152 function = "qup0"; 1153 }; 1154 1155 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1156 pins = "gpio18", "gpio19"; 1157 function = "qup0"; 1158 }; 1159 1160 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1161 pins = "gpio20", "gpio21"; 1162 function = "qup1"; 1163 }; 1164 1165 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1166 pins = "gpio14", "gpio15"; 1167 function = "qup1"; 1168 }; 1169 1170 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1171 pins = "gpio6", "gpio7"; 1172 function = "qup1"; 1173 }; 1174 1175 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1176 pins = "gpio10", "gpio11"; 1177 function = "qup1"; 1178 }; 1179 1180 qup_spi2_data_clk: qup-spi2-data-clk-state { 1181 pins = "gpio0", "gpio1", "gpio2"; 1182 function = "qup0"; 1183 }; 1184 1185 qup_spi2_cs: qup-spi2-cs-state { 1186 pins = "gpio3"; 1187 function = "qup0"; 1188 }; 1189 1190 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1191 pins = "gpio3"; 1192 function = "gpio"; 1193 }; 1194 1195 qup_spi4_data_clk: qup-spi4-data-clk-state { 1196 pins = "gpio20", "gpio21", "gpio22"; 1197 function = "qup1"; 1198 }; 1199 1200 qup_spi4_cs: qup-spi4-cs-state { 1201 pins = "gpio23"; 1202 function = "qup1"; 1203 }; 1204 1205 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1206 pins = "gpio23"; 1207 function = "gpio"; 1208 }; 1209 1210 qup_spi6_data_clk: qup-spi6-data-clk-state { 1211 pins = "gpio6", "gpio7", "gpio8"; 1212 function = "qup1"; 1213 }; 1214 1215 qup_spi6_cs: qup-spi6-cs-state { 1216 pins = "gpio9"; 1217 function = "qup1"; 1218 }; 1219 1220 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1221 pins = "gpio9"; 1222 function = "gpio"; 1223 }; 1224 1225 qup_spi7_data_clk: qup-spi7-data-clk-state { 1226 pins = "gpio10", "gpio11", "gpio12"; 1227 function = "qup1"; 1228 }; 1229 1230 qup_spi7_cs: qup-spi7-cs-state { 1231 pins = "gpio13"; 1232 function = "qup1"; 1233 }; 1234 1235 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1236 pins = "gpio13"; 1237 function = "gpio"; 1238 }; 1239 1240 qup_uart0_tx: qup-uart0-tx-state { 1241 pins = "gpio16"; 1242 function = "qup0"; 1243 }; 1244 1245 qup_uart0_rx: qup-uart0-rx-state { 1246 pins = "gpio17"; 1247 function = "qup0"; 1248 }; 1249 1250 qup_uart2_cts: qup-uart2-cts-state { 1251 pins = "gpio0"; 1252 function = "qup0"; 1253 }; 1254 1255 qup_uart2_rts: qup-uart2-rts-state { 1256 pins = "gpio1"; 1257 function = "qup0"; 1258 }; 1259 1260 qup_uart2_tx: qup-uart2-tx-state { 1261 pins = "gpio2"; 1262 function = "qup0"; 1263 }; 1264 1265 qup_uart2_rx: qup-uart2-rx-state { 1266 pins = "gpio3"; 1267 function = "qup0"; 1268 }; 1269 1270 qup_uart4_cts: qup-uart4-cts-state { 1271 pins = "gpio20"; 1272 function = "qup1"; 1273 }; 1274 1275 qup_uart4_rts: qup-uart4-rts-state { 1276 pins = "gpio21"; 1277 function = "qup1"; 1278 }; 1279 1280 qup_uart4_tx: qup-uart4-tx-state { 1281 pins = "gpio22"; 1282 function = "qup1"; 1283 }; 1284 1285 qup_uart4_rx: qup-uart4-rx-state { 1286 pins = "gpio23"; 1287 function = "qup1"; 1288 }; 1289 1290 qup_uart6_cts: qup-uart6-cts-state { 1291 pins = "gpio6"; 1292 function = "qup1"; 1293 }; 1294 1295 qup_uart6_rts: qup-uart6-rts-state { 1296 pins = "gpio7"; 1297 function = "qup1"; 1298 }; 1299 1300 qup_uart6_tx: qup-uart6-tx-state { 1301 pins = "gpio8"; 1302 function = "qup1"; 1303 }; 1304 1305 qup_uart6_rx: qup-uart6-rx-state { 1306 pins = "gpio9"; 1307 function = "qup1"; 1308 }; 1309 1310 qup_uart7_cts: qup-uart7-cts-state { 1311 pins = "gpio10"; 1312 function = "qup1"; 1313 }; 1314 1315 qup_uart7_rts: qup-uart7-rts-state { 1316 pins = "gpio11"; 1317 function = "qup1"; 1318 }; 1319 1320 qup_uart7_tx: qup-uart7-tx-state { 1321 pins = "gpio12"; 1322 function = "qup1"; 1323 }; 1324 1325 qup_uart7_rx: qup-uart7-rx-state { 1326 pins = "gpio13"; 1327 function = "qup1"; 1328 }; 1329 1330 sdc1_state_on: sdc1-on-state { 1331 clk-pins { 1332 pins = "sdc1_clk"; 1333 bias-disable; 1334 drive-strength = <16>; 1335 }; 1336 1337 cmd-pins { 1338 pins = "sdc1_cmd"; 1339 bias-pull-up; 1340 drive-strength = <10>; 1341 }; 1342 1343 data-pins { 1344 pins = "sdc1_data"; 1345 bias-pull-up; 1346 drive-strength = <10>; 1347 }; 1348 1349 rclk-pins { 1350 pins = "sdc1_rclk"; 1351 bias-pull-down; 1352 }; 1353 }; 1354 1355 sdc1_state_off: sdc1-off-state { 1356 clk-pins { 1357 pins = "sdc1_clk"; 1358 bias-disable; 1359 drive-strength = <2>; 1360 }; 1361 1362 cmd-pins { 1363 pins = "sdc1_cmd"; 1364 bias-pull-up; 1365 drive-strength = <2>; 1366 }; 1367 1368 data-pins { 1369 pins = "sdc1_data"; 1370 bias-pull-up; 1371 drive-strength = <2>; 1372 }; 1373 1374 rclk-pins { 1375 pins = "sdc1_rclk"; 1376 bias-pull-down; 1377 }; 1378 }; 1379 1380 sdc2_state_on: sdc2-on-state { 1381 clk-pins { 1382 pins = "sdc2_clk"; 1383 bias-disable; 1384 drive-strength = <16>; 1385 }; 1386 1387 cmd-pins { 1388 pins = "sdc2_cmd"; 1389 bias-pull-up; 1390 drive-strength = <10>; 1391 }; 1392 1393 data-pins { 1394 pins = "sdc2_data"; 1395 bias-pull-up; 1396 drive-strength = <10>; 1397 }; 1398 }; 1399 1400 sdc2_state_off: sdc2-off-state { 1401 clk-pins { 1402 pins = "sdc2_clk"; 1403 bias-disable; 1404 drive-strength = <2>; 1405 }; 1406 1407 cmd-pins { 1408 pins = "sdc2_cmd"; 1409 bias-pull-up; 1410 drive-strength = <2>; 1411 }; 1412 1413 data-pins { 1414 pins = "sdc2_data"; 1415 bias-pull-up; 1416 drive-strength = <2>; 1417 }; 1418 }; 1419 }; 1420 1421 stm@6002000 { 1422 compatible = "arm,coresight-stm", "arm,primecell"; 1423 reg = <0x0 0x06002000 0x0 0x1000>, 1424 <0x0 0x16280000 0x0 0x180000>; 1425 reg-names = "stm-base", 1426 "stm-stimulus-base"; 1427 1428 clocks = <&aoss_qmp>; 1429 clock-names = "apb_pclk"; 1430 1431 out-ports { 1432 port { 1433 stm_out: endpoint { 1434 remote-endpoint = <&funnel_in0_in7>; 1435 }; 1436 }; 1437 }; 1438 }; 1439 1440 tpda@6004000 { 1441 compatible = "qcom,coresight-tpda", "arm,primecell"; 1442 reg = <0x0 0x06004000 0x0 0x1000>; 1443 1444 clocks = <&aoss_qmp>; 1445 clock-names = "apb_pclk"; 1446 1447 in-ports { 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 1451 port@0 { 1452 reg = <0>; 1453 1454 tpda_qdss_in0: endpoint { 1455 remote-endpoint = <&tpdm_center_out>; 1456 }; 1457 }; 1458 1459 port@4 { 1460 reg = <4>; 1461 1462 tpda_qdss_in4: endpoint { 1463 remote-endpoint = <&funnel_monaq_out>; 1464 }; 1465 }; 1466 1467 port@5 { 1468 reg = <5>; 1469 1470 tpda_qdss_in5: endpoint { 1471 remote-endpoint = <&funnel_ddr_0_out>; 1472 }; 1473 }; 1474 1475 port@6 { 1476 reg = <6>; 1477 1478 tpda_qdss_in6: endpoint { 1479 remote-endpoint = <&funnel_turing_out>; 1480 }; 1481 }; 1482 1483 port@7 { 1484 reg = <7>; 1485 1486 tpda_qdss_in7: endpoint { 1487 remote-endpoint = <&tpdm_vsense_out>; 1488 }; 1489 }; 1490 1491 port@8 { 1492 reg = <8>; 1493 1494 tpda_qdss_in8: endpoint { 1495 remote-endpoint = <&tpdm_dcc_out>; 1496 }; 1497 }; 1498 1499 port@9 { 1500 reg = <9>; 1501 1502 tpda_qdss_in9: endpoint { 1503 remote-endpoint = <&tpdm_prng_out>; 1504 }; 1505 }; 1506 1507 port@b { 1508 reg = <11>; 1509 1510 tpda_qdss_in11: endpoint { 1511 remote-endpoint = <&tpdm_qm_out>; 1512 }; 1513 }; 1514 1515 port@c { 1516 reg = <12>; 1517 1518 tpda_qdss_in12: endpoint { 1519 remote-endpoint = <&tpdm_west_out>; 1520 }; 1521 }; 1522 1523 port@d { 1524 reg = <13>; 1525 1526 tpda_qdss_in13: endpoint { 1527 remote-endpoint = <&tpdm_pimem_out>; 1528 }; 1529 }; 1530 }; 1531 1532 out-ports { 1533 port { 1534 tpda_qdss_out: endpoint { 1535 remote-endpoint = <&funnel_qatb_in>; 1536 }; 1537 }; 1538 }; 1539 }; 1540 1541 funnel@6005000 { 1542 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1543 reg = <0x0 0x06005000 0x0 0x1000>; 1544 1545 clocks = <&aoss_qmp>; 1546 clock-names = "apb_pclk"; 1547 1548 in-ports { 1549 port { 1550 funnel_qatb_in: endpoint { 1551 remote-endpoint = <&tpda_qdss_out>; 1552 }; 1553 }; 1554 }; 1555 1556 out-ports { 1557 port { 1558 funnel_qatb_out: endpoint { 1559 remote-endpoint = <&funnel_in0_in6>; 1560 }; 1561 }; 1562 }; 1563 }; 1564 1565 cti@6010000 { 1566 compatible = "arm,coresight-cti", "arm,primecell"; 1567 reg = <0x0 0x06010000 0x0 0x1000>; 1568 1569 clocks = <&aoss_qmp>; 1570 clock-names = "apb_pclk"; 1571 }; 1572 1573 cti@6011000 { 1574 compatible = "arm,coresight-cti", "arm,primecell"; 1575 reg = <0x0 0x06011000 0x0 0x1000>; 1576 1577 clocks = <&aoss_qmp>; 1578 clock-names = "apb_pclk"; 1579 }; 1580 1581 cti@6012000 { 1582 compatible = "arm,coresight-cti", "arm,primecell"; 1583 reg = <0x0 0x06012000 0x0 0x1000>; 1584 1585 clocks = <&aoss_qmp>; 1586 clock-names = "apb_pclk"; 1587 }; 1588 1589 cti@6013000 { 1590 compatible = "arm,coresight-cti", "arm,primecell"; 1591 reg = <0x0 0x06013000 0x0 0x1000>; 1592 1593 clocks = <&aoss_qmp>; 1594 clock-names = "apb_pclk"; 1595 }; 1596 1597 cti@6014000 { 1598 compatible = "arm,coresight-cti", "arm,primecell"; 1599 reg = <0x0 0x06014000 0x0 0x1000>; 1600 1601 clocks = <&aoss_qmp>; 1602 clock-names = "apb_pclk"; 1603 }; 1604 1605 cti@6015000 { 1606 compatible = "arm,coresight-cti", "arm,primecell"; 1607 reg = <0x0 0x06015000 0x0 0x1000>; 1608 1609 clocks = <&aoss_qmp>; 1610 clock-names = "apb_pclk"; 1611 }; 1612 1613 cti@6016000 { 1614 compatible = "arm,coresight-cti", "arm,primecell"; 1615 reg = <0x0 0x06016000 0x0 0x1000>; 1616 1617 clocks = <&aoss_qmp>; 1618 clock-names = "apb_pclk"; 1619 }; 1620 1621 cti@6017000 { 1622 compatible = "arm,coresight-cti", "arm,primecell"; 1623 reg = <0x0 0x06017000 0x0 0x1000>; 1624 1625 clocks = <&aoss_qmp>; 1626 clock-names = "apb_pclk"; 1627 }; 1628 1629 cti@6018000 { 1630 compatible = "arm,coresight-cti", "arm,primecell"; 1631 reg = <0x0 0x06018000 0x0 0x1000>; 1632 1633 clocks = <&aoss_qmp>; 1634 clock-names = "apb_pclk"; 1635 }; 1636 1637 cti@6019000 { 1638 compatible = "arm,coresight-cti", "arm,primecell"; 1639 reg = <0x0 0x06019000 0x0 0x1000>; 1640 1641 clocks = <&aoss_qmp>; 1642 clock-names = "apb_pclk"; 1643 }; 1644 1645 cti@601a000 { 1646 compatible = "arm,coresight-cti", "arm,primecell"; 1647 reg = <0x0 0x0601a000 0x0 0x1000>; 1648 1649 clocks = <&aoss_qmp>; 1650 clock-names = "apb_pclk"; 1651 }; 1652 1653 cti@601b000 { 1654 compatible = "arm,coresight-cti", "arm,primecell"; 1655 reg = <0x0 0x0601b000 0x0 0x1000>; 1656 1657 clocks = <&aoss_qmp>; 1658 clock-names = "apb_pclk"; 1659 }; 1660 1661 cti@601c000 { 1662 compatible = "arm,coresight-cti", "arm,primecell"; 1663 reg = <0x0 0x0601c000 0x0 0x1000>; 1664 1665 clocks = <&aoss_qmp>; 1666 clock-names = "apb_pclk"; 1667 }; 1668 1669 cti@601d000 { 1670 compatible = "arm,coresight-cti", "arm,primecell"; 1671 reg = <0x0 0x0601d000 0x0 0x1000>; 1672 1673 clocks = <&aoss_qmp>; 1674 clock-names = "apb_pclk"; 1675 }; 1676 1677 cti@601e000 { 1678 compatible = "arm,coresight-cti", "arm,primecell"; 1679 reg = <0x0 0x0601e000 0x0 0x1000>; 1680 1681 clocks = <&aoss_qmp>; 1682 clock-names = "apb_pclk"; 1683 }; 1684 1685 cti@601f000 { 1686 compatible = "arm,coresight-cti", "arm,primecell"; 1687 reg = <0x0 0x0601f000 0x0 0x1000>; 1688 1689 clocks = <&aoss_qmp>; 1690 clock-names = "apb_pclk"; 1691 }; 1692 1693 funnel@6041000 { 1694 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1695 reg = <0x0 0x06041000 0x0 0x1000>; 1696 1697 clocks = <&aoss_qmp>; 1698 clock-names = "apb_pclk"; 1699 1700 in-ports { 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 1704 port@6 { 1705 reg = <6>; 1706 1707 funnel_in0_in6: endpoint { 1708 remote-endpoint = <&funnel_qatb_out>; 1709 }; 1710 }; 1711 1712 port@7 { 1713 reg = <7>; 1714 1715 funnel_in0_in7: endpoint { 1716 remote-endpoint = <&stm_out>; 1717 }; 1718 }; 1719 }; 1720 1721 out-ports { 1722 port { 1723 funnel_in0_out: endpoint { 1724 remote-endpoint = <&funnel_merg_in0>; 1725 }; 1726 }; 1727 }; 1728 }; 1729 1730 funnel@6042000 { 1731 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1732 reg = <0x0 0x06042000 0x0 0x1000>; 1733 1734 clocks = <&aoss_qmp>; 1735 clock-names = "apb_pclk"; 1736 1737 in-ports { 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 1741 port@3 { 1742 reg = <3>; 1743 1744 funnel_in1_in3: endpoint { 1745 remote-endpoint = <&replicator_swao_out0>; 1746 }; 1747 }; 1748 1749 port@4 { 1750 reg = <4>; 1751 1752 funnel_in1_in4: endpoint { 1753 remote-endpoint = <&tpdm_wcss_out>; 1754 }; 1755 }; 1756 1757 port@7 { 1758 reg = <7>; 1759 1760 funnel_in1_in7: endpoint { 1761 remote-endpoint = <&funnel_apss_merg_out>; 1762 }; 1763 }; 1764 }; 1765 1766 out-ports { 1767 port { 1768 funnel_in1_out: endpoint { 1769 remote-endpoint = <&funnel_merg_in1>; 1770 }; 1771 }; 1772 }; 1773 }; 1774 1775 funnel@6045000 { 1776 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1777 reg = <0x0 0x06045000 0x0 0x1000>; 1778 1779 clocks = <&aoss_qmp>; 1780 clock-names = "apb_pclk"; 1781 1782 in-ports { 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 1786 port@0 { 1787 reg = <0>; 1788 1789 funnel_merg_in0: endpoint { 1790 remote-endpoint = <&funnel_in0_out>; 1791 }; 1792 }; 1793 1794 port@1 { 1795 reg = <1>; 1796 1797 funnel_merg_in1: endpoint { 1798 remote-endpoint = <&funnel_in1_out>; 1799 }; 1800 }; 1801 }; 1802 1803 out-ports { 1804 port { 1805 funnel_merg_out: endpoint { 1806 remote-endpoint = <&tmc_etf_in>; 1807 }; 1808 }; 1809 }; 1810 }; 1811 1812 replicator@6046000 { 1813 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1814 reg = <0x0 0x06046000 0x0 0x1000>; 1815 1816 clocks = <&aoss_qmp>; 1817 clock-names = "apb_pclk"; 1818 1819 in-ports { 1820 port { 1821 replicator0_in: endpoint { 1822 remote-endpoint= <&tmc_etf_out>; 1823 }; 1824 }; 1825 }; 1826 1827 out-ports { 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 1831 port@1 { 1832 reg = <1>; 1833 1834 replicator0_out1: endpoint { 1835 remote-endpoint= <&replicator1_in>; 1836 }; 1837 }; 1838 }; 1839 }; 1840 1841 tmc@6047000 { 1842 compatible = "arm,coresight-tmc", "arm,primecell"; 1843 reg = <0x0 0x06047000 0x0 0x1000>; 1844 1845 clocks = <&aoss_qmp>; 1846 clock-names = "apb_pclk"; 1847 1848 in-ports { 1849 port { 1850 tmc_etf_in: endpoint { 1851 remote-endpoint = <&funnel_merg_out>; 1852 }; 1853 }; 1854 }; 1855 1856 out-ports { 1857 port { 1858 tmc_etf_out: endpoint { 1859 remote-endpoint = <&replicator0_in>; 1860 }; 1861 }; 1862 }; 1863 }; 1864 1865 replicator@604a000 { 1866 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1867 reg = <0x0 0x0604a000 0x0 0x1000>; 1868 1869 clocks = <&aoss_qmp>; 1870 clock-names = "apb_pclk"; 1871 1872 in-ports { 1873 port { 1874 replicator1_in: endpoint { 1875 remote-endpoint= <&replicator0_out1>; 1876 }; 1877 }; 1878 }; 1879 1880 out-ports { 1881 port { 1882 replicator1_out: endpoint { 1883 remote-endpoint= <&funnel_swao_in6>; 1884 }; 1885 }; 1886 }; 1887 }; 1888 1889 cti@683b000 { 1890 compatible = "arm,coresight-cti", "arm,primecell"; 1891 reg = <0x0 0x0683b000 0x0 0x1000>; 1892 1893 clocks = <&aoss_qmp>; 1894 clock-names = "apb_pclk"; 1895 }; 1896 1897 tpdm@6840000 { 1898 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1899 reg = <0x0 0x06840000 0x0 0x1000>; 1900 1901 clocks = <&aoss_qmp>; 1902 clock-names = "apb_pclk"; 1903 1904 qcom,cmb-element-bits = <64>; 1905 qcom,cmb-msrs-num = <32>; 1906 status = "disabled"; 1907 1908 out-ports { 1909 port { 1910 tpdm_vsense_out: endpoint { 1911 remote-endpoint = <&tpda_qdss_in7>; 1912 }; 1913 }; 1914 }; 1915 }; 1916 1917 tpdm@684c000 { 1918 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1919 reg = <0x0 0x0684c000 0x0 0x1000>; 1920 1921 clocks = <&aoss_qmp>; 1922 clock-names = "apb_pclk"; 1923 1924 qcom,cmb-element-bits = <32>; 1925 qcom,cmb-msrs-num = <32>; 1926 1927 out-ports { 1928 port { 1929 tpdm_prng_out: endpoint { 1930 remote-endpoint = <&tpda_qdss_in9>; 1931 }; 1932 }; 1933 }; 1934 }; 1935 1936 tpdm@6850000 { 1937 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1938 reg = <0x0 0x06850000 0x0 0x1000>; 1939 1940 clocks = <&aoss_qmp>; 1941 clock-names = "apb_pclk"; 1942 1943 qcom,cmb-element-bits = <64>; 1944 qcom,cmb-msrs-num = <32>; 1945 qcom,dsb-element-bits = <32>; 1946 qcom,dsb-msrs-num = <32>; 1947 1948 out-ports { 1949 port { 1950 tpdm_pimem_out: endpoint { 1951 remote-endpoint = <&tpda_qdss_in13>; 1952 }; 1953 }; 1954 }; 1955 }; 1956 1957 tpdm@6860000 { 1958 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1959 reg = <0x0 0x06860000 0x0 0x1000>; 1960 1961 clocks = <&aoss_qmp>; 1962 clock-names = "apb_pclk"; 1963 1964 qcom,dsb-element-bits = <32>; 1965 qcom,dsb-msrs-num = <32>; 1966 1967 out-ports { 1968 port { 1969 tpdm_turing_out: endpoint { 1970 remote-endpoint = <&funnel_turing_in>; 1971 }; 1972 }; 1973 }; 1974 }; 1975 1976 funnel@6861000 { 1977 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1978 reg = <0x0 0x06861000 0x0 0x1000>; 1979 1980 clocks = <&aoss_qmp>; 1981 clock-names = "apb_pclk"; 1982 1983 in-ports { 1984 port { 1985 funnel_turing_in: endpoint { 1986 remote-endpoint = <&tpdm_turing_out>; 1987 }; 1988 }; 1989 }; 1990 1991 out-ports { 1992 port { 1993 funnel_turing_out: endpoint { 1994 remote-endpoint = <&tpda_qdss_in6>; 1995 }; 1996 }; 1997 }; 1998 }; 1999 2000 cti@6867000 { 2001 compatible = "arm,coresight-cti", "arm,primecell"; 2002 reg = <0x0 0x06867000 0x0 0x1000>; 2003 2004 clocks = <&aoss_qmp>; 2005 clock-names = "apb_pclk"; 2006 }; 2007 2008 tpdm@6870000 { 2009 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2010 reg = <0x0 0x06870000 0x0 0x1000>; 2011 2012 clocks = <&aoss_qmp>; 2013 clock-names = "apb_pclk"; 2014 2015 qcom,cmb-element-bits = <32>; 2016 qcom,cmb-msrs-num = <32>; 2017 status = "disabled"; 2018 2019 out-ports { 2020 port { 2021 tpdm_dcc_out: endpoint { 2022 remote-endpoint = <&tpda_qdss_in8>; 2023 }; 2024 }; 2025 }; 2026 }; 2027 2028 tpdm@699c000 { 2029 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2030 reg = <0x0 0x0699c000 0x0 0x1000>; 2031 2032 clocks = <&aoss_qmp>; 2033 clock-names = "apb_pclk"; 2034 2035 qcom,cmb-element-bits = <32>; 2036 qcom,cmb-msrs-num = <32>; 2037 qcom,dsb-element-bits = <32>; 2038 qcom,dsb-msrs-num = <32>; 2039 status = "disabled"; 2040 2041 out-ports { 2042 port { 2043 tpdm_wcss_out: endpoint { 2044 remote-endpoint = <&funnel_in1_in4>; 2045 }; 2046 }; 2047 }; 2048 }; 2049 2050 tpdm@69c0000 { 2051 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2052 reg = <0x0 0x069c0000 0x0 0x1000>; 2053 2054 clocks = <&aoss_qmp>; 2055 clock-names = "apb_pclk"; 2056 2057 qcom,dsb-element-bits = <32>; 2058 qcom,dsb-msrs-num = <32>; 2059 2060 out-ports { 2061 port { 2062 tpdm_monaq_out: endpoint { 2063 remote-endpoint = <&funnel_monaq_in>; 2064 }; 2065 }; 2066 }; 2067 }; 2068 2069 funnel@69c3000 { 2070 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2071 reg = <0x0 0x069c3000 0x0 0x1000>; 2072 2073 clocks = <&aoss_qmp>; 2074 clock-names = "apb_pclk"; 2075 2076 in-ports { 2077 port { 2078 funnel_monaq_in: endpoint { 2079 remote-endpoint = <&tpdm_monaq_out>; 2080 }; 2081 }; 2082 }; 2083 2084 out-ports { 2085 port { 2086 funnel_monaq_out: endpoint { 2087 remote-endpoint = <&tpda_qdss_in4>; 2088 }; 2089 }; 2090 }; 2091 }; 2092 2093 tpdm@69d0000 { 2094 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2095 reg = <0x0 0x069d0000 0x0 0x1000>; 2096 2097 clocks = <&aoss_qmp>; 2098 clock-names = "apb_pclk"; 2099 2100 qcom,dsb-element-bits = <32>; 2101 qcom,dsb-msrs-num = <32>; 2102 status = "disabled"; 2103 2104 out-ports { 2105 port { 2106 tpdm_qm_out: endpoint { 2107 remote-endpoint = <&tpda_qdss_in11>; 2108 }; 2109 }; 2110 }; 2111 }; 2112 2113 tpdm@6a00000 { 2114 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2115 reg = <0x0 0x06a00000 0x0 0x1000>; 2116 2117 clocks = <&aoss_qmp>; 2118 clock-names = "apb_pclk"; 2119 2120 qcom,dsb-element-bits = <32>; 2121 qcom,dsb-msrs-num = <32>; 2122 status = "disabled"; 2123 2124 out-ports { 2125 port { 2126 tpdm_ddr_out: endpoint { 2127 remote-endpoint = <&funnel_ddr_0_in>; 2128 }; 2129 }; 2130 }; 2131 }; 2132 2133 cti@6a02000 { 2134 compatible = "arm,coresight-cti", "arm,primecell"; 2135 reg = <0x0 0x06a02000 0x0 0x1000>; 2136 2137 clocks = <&aoss_qmp>; 2138 clock-names = "apb_pclk"; 2139 }; 2140 2141 cti@6a03000 { 2142 compatible = "arm,coresight-cti", "arm,primecell"; 2143 reg = <0x0 0x06a03000 0x0 0x1000>; 2144 2145 clocks = <&aoss_qmp>; 2146 clock-names = "apb_pclk"; 2147 }; 2148 2149 cti@6a10000 { 2150 compatible = "arm,coresight-cti", "arm,primecell"; 2151 reg = <0x0 0x06a10000 0x0 0x1000>; 2152 2153 clocks = <&aoss_qmp>; 2154 clock-names = "apb_pclk"; 2155 }; 2156 2157 cti@6a11000 { 2158 compatible = "arm,coresight-cti", "arm,primecell"; 2159 reg = <0x0 0x06a11000 0x0 0x1000>; 2160 2161 clocks = <&aoss_qmp>; 2162 clock-names = "apb_pclk"; 2163 }; 2164 2165 funnel@6a05000 { 2166 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2167 reg = <0x0 0x06a05000 0x0 0x1000>; 2168 2169 clocks = <&aoss_qmp>; 2170 clock-names = "apb_pclk"; 2171 2172 in-ports { 2173 port { 2174 funnel_ddr_0_in: endpoint { 2175 remote-endpoint = <&tpdm_ddr_out>; 2176 }; 2177 }; 2178 }; 2179 2180 out-ports { 2181 port { 2182 funnel_ddr_0_out: endpoint { 2183 remote-endpoint = <&tpda_qdss_in5>; 2184 }; 2185 }; 2186 }; 2187 }; 2188 2189 tpda@6b01000 { 2190 compatible = "qcom,coresight-tpda", "arm,primecell"; 2191 reg = <0x0 0x06b01000 0x0 0x1000>; 2192 2193 clocks = <&aoss_qmp>; 2194 clock-names = "apb_pclk"; 2195 2196 in-ports { 2197 #address-cells = <1>; 2198 #size-cells = <0>; 2199 2200 port@0 { 2201 reg = <0>; 2202 2203 tpda_swao_in0: endpoint { 2204 remote-endpoint = <&tpdm_swao0_out>; 2205 }; 2206 }; 2207 2208 port@1 { 2209 reg = <1>; 2210 2211 tpda_swao_in1: endpoint { 2212 remote-endpoint = <&tpdm_swao1_out>; 2213 }; 2214 2215 }; 2216 }; 2217 2218 out-ports { 2219 port { 2220 tpda_swao_out: endpoint { 2221 remote-endpoint = <&funnel_swao_in7>; 2222 }; 2223 }; 2224 }; 2225 }; 2226 2227 tpdm@6b02000 { 2228 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2229 reg = <0x0 0x06b02000 0x0 0x1000>; 2230 2231 clocks = <&aoss_qmp>; 2232 clock-names = "apb_pclk"; 2233 2234 qcom,cmb-element-bits = <64>; 2235 qcom,cmb-msrs-num = <32>; 2236 status = "disabled"; 2237 2238 out-ports { 2239 port { 2240 tpdm_swao0_out: endpoint { 2241 remote-endpoint = <&tpda_swao_in0>; 2242 }; 2243 }; 2244 }; 2245 }; 2246 2247 tpdm@6b03000 { 2248 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2249 reg = <0x0 0x06b03000 0x0 0x1000>; 2250 2251 clocks = <&aoss_qmp>; 2252 clock-names = "apb_pclk"; 2253 2254 qcom,dsb-element-bits = <32>; 2255 qcom,dsb-msrs-num = <32>; 2256 status = "disabled"; 2257 2258 out-ports { 2259 port { 2260 tpdm_swao1_out: endpoint { 2261 remote-endpoint = <&tpda_swao_in1>; 2262 }; 2263 }; 2264 }; 2265 }; 2266 2267 cti@6b04000 { 2268 compatible = "arm,coresight-cti", "arm,primecell"; 2269 reg = <0x0 0x06b04000 0x0 0x1000>; 2270 2271 clocks = <&aoss_qmp>; 2272 clock-names = "apb_pclk"; 2273 }; 2274 2275 cti@6b05000 { 2276 compatible = "arm,coresight-cti", "arm,primecell"; 2277 reg = <0x0 0x06b05000 0x0 0x1000>; 2278 2279 clocks = <&aoss_qmp>; 2280 clock-names = "apb_pclk"; 2281 }; 2282 2283 cti@6b06000 { 2284 compatible = "arm,coresight-cti", "arm,primecell"; 2285 reg = <0x0 0x06b06000 0x0 0x1000>; 2286 2287 clocks = <&aoss_qmp>; 2288 clock-names = "apb_pclk"; 2289 }; 2290 2291 cti@6b07000 { 2292 compatible = "arm,coresight-cti", "arm,primecell"; 2293 reg = <0x0 0x06b07000 0x0 0x1000>; 2294 2295 clocks = <&aoss_qmp>; 2296 clock-names = "apb_pclk"; 2297 }; 2298 2299 funnel@6b08000 { 2300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2301 reg = <0x0 0x06b08000 0x0 0x1000>; 2302 2303 clocks = <&aoss_qmp>; 2304 clock-names = "apb_pclk"; 2305 2306 in-ports { 2307 #address-cells = <1>; 2308 #size-cells = <0>; 2309 2310 port@6 { 2311 reg = <6>; 2312 2313 funnel_swao_in6: endpoint { 2314 remote-endpoint= <&replicator1_out>; 2315 }; 2316 }; 2317 2318 port@7 { 2319 reg = <7>; 2320 2321 funnel_swao_in7: endpoint { 2322 remote-endpoint= <&tpda_swao_out>; 2323 }; 2324 }; 2325 }; 2326 2327 out-ports { 2328 port { 2329 funnel_swao_out: endpoint { 2330 remote-endpoint = <&tmc_etf_swao_in>; 2331 }; 2332 }; 2333 }; 2334 }; 2335 2336 tmc@6b09000 { 2337 compatible = "arm,coresight-tmc", "arm,primecell"; 2338 reg = <0x0 0x06b09000 0x0 0x1000>; 2339 2340 clocks = <&aoss_qmp>; 2341 clock-names = "apb_pclk"; 2342 2343 in-ports { 2344 port { 2345 tmc_etf_swao_in: endpoint { 2346 remote-endpoint= <&funnel_swao_out>; 2347 }; 2348 }; 2349 }; 2350 2351 out-ports { 2352 port { 2353 tmc_etf_swao_out: endpoint { 2354 remote-endpoint= <&replicator_swao_in>; 2355 }; 2356 }; 2357 }; 2358 }; 2359 2360 replicator@6b0a000 { 2361 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2362 reg = <0x0 0x06b0a000 0x0 0x1000>; 2363 2364 clocks = <&aoss_qmp>; 2365 clock-names = "apb_pclk"; 2366 2367 in-ports { 2368 port { 2369 replicator_swao_in: endpoint { 2370 remote-endpoint = <&tmc_etf_swao_out>; 2371 }; 2372 }; 2373 }; 2374 2375 out-ports { 2376 #address-cells = <1>; 2377 #size-cells = <0>; 2378 2379 port@0 { 2380 reg = <0>; 2381 2382 replicator_swao_out0: endpoint { 2383 remote-endpoint = <&funnel_in1_in3>; 2384 }; 2385 }; 2386 2387 port@1 { 2388 reg = <1>; 2389 2390 replicator_swao_out1: endpoint { 2391 remote-endpoint = <&eud_in>; 2392 }; 2393 }; 2394 }; 2395 }; 2396 2397 cti@6b21000 { 2398 compatible = "arm,coresight-cti", "arm,primecell"; 2399 reg = <0x0 0x06b21000 0x0 0x1000>; 2400 2401 clocks = <&aoss_qmp>; 2402 clock-names = "apb_pclk"; 2403 }; 2404 2405 tpdm@6b48000 { 2406 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2407 reg = <0x0 0x06b48000 0x0 0x1000>; 2408 2409 clocks = <&aoss_qmp>; 2410 clock-names = "apb_pclk"; 2411 2412 qcom,dsb-element-bits = <32>; 2413 qcom,dsb-msrs-num = <32>; 2414 2415 out-ports { 2416 port { 2417 tpdm_west_out: endpoint { 2418 remote-endpoint = <&tpda_qdss_in12>; 2419 }; 2420 }; 2421 }; 2422 }; 2423 2424 cti@6c13000 { 2425 compatible = "arm,coresight-cti", "arm,primecell"; 2426 reg = <0x0 0x06c13000 0x0 0x1000>; 2427 2428 clocks = <&aoss_qmp>; 2429 clock-names = "apb_pclk"; 2430 }; 2431 2432 cti@6c20000 { 2433 compatible = "arm,coresight-cti", "arm,primecell"; 2434 reg = <0x0 0x06c20000 0x0 0x1000>; 2435 2436 clocks = <&aoss_qmp>; 2437 clock-names = "apb_pclk"; 2438 status = "disabled"; 2439 }; 2440 2441 tpdm@6c28000 { 2442 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2443 reg = <0x0 0x06c28000 0x0 0x1000>; 2444 2445 clocks = <&aoss_qmp>; 2446 clock-names = "apb_pclk"; 2447 2448 qcom,dsb-element-bits = <32>; 2449 qcom,dsb-msrs-num = <32>; 2450 2451 out-ports { 2452 port { 2453 tpdm_center_out: endpoint { 2454 remote-endpoint = <&tpda_qdss_in0>; 2455 }; 2456 }; 2457 }; 2458 }; 2459 2460 cti@6c29000 { 2461 compatible = "arm,coresight-cti", "arm,primecell"; 2462 reg = <0x0 0x06c29000 0x0 0x1000>; 2463 2464 clocks = <&aoss_qmp>; 2465 clock-names = "apb_pclk"; 2466 }; 2467 2468 cti@6c2a000 { 2469 compatible = "arm,coresight-cti", "arm,primecell"; 2470 reg = <0x0 0x06c2a000 0x0 0x1000>; 2471 2472 clocks = <&aoss_qmp>; 2473 clock-names = "apb_pclk"; 2474 }; 2475 2476 cti@7020000 { 2477 compatible = "arm,coresight-cti", "arm,primecell"; 2478 reg = <0x0 0x07020000 0x0 0x1000>; 2479 2480 clocks = <&aoss_qmp>; 2481 clock-names = "apb_pclk"; 2482 }; 2483 2484 etm@7040000 { 2485 compatible = "arm,primecell"; 2486 reg = <0x0 0x07040000 0x0 0x1000>; 2487 cpu = <&cpu0>; 2488 2489 clocks = <&aoss_qmp>; 2490 clock-names = "apb_pclk"; 2491 2492 arm,coresight-loses-context-with-cpu; 2493 qcom,skip-power-up; 2494 2495 out-ports { 2496 port { 2497 etm0_out: endpoint { 2498 remote-endpoint = <&funnel_apss_in0>; 2499 }; 2500 }; 2501 }; 2502 }; 2503 2504 cti@7120000 { 2505 compatible = "arm,coresight-cti", "arm,primecell"; 2506 reg = <0x0 0x07120000 0x0 0x1000>; 2507 2508 clocks = <&aoss_qmp>; 2509 clock-names = "apb_pclk"; 2510 }; 2511 2512 etm@7140000 { 2513 compatible = "arm,primecell"; 2514 reg = <0x0 0x07140000 0x0 0x1000>; 2515 cpu = <&cpu1>; 2516 2517 clocks = <&aoss_qmp>; 2518 clock-names = "apb_pclk"; 2519 2520 arm,coresight-loses-context-with-cpu; 2521 qcom,skip-power-up; 2522 2523 out-ports { 2524 port { 2525 etm1_out: endpoint { 2526 remote-endpoint = <&funnel_apss_in1>; 2527 }; 2528 }; 2529 }; 2530 }; 2531 2532 cti@7220000 { 2533 compatible = "arm,coresight-cti", "arm,primecell"; 2534 reg = <0x0 0x07220000 0x0 0x1000>; 2535 2536 clocks = <&aoss_qmp>; 2537 clock-names = "apb_pclk"; 2538 }; 2539 2540 etm@7240000 { 2541 compatible = "arm,primecell"; 2542 reg = <0x0 0x07240000 0x0 0x1000>; 2543 cpu = <&cpu2>; 2544 2545 clocks = <&aoss_qmp>; 2546 clock-names = "apb_pclk"; 2547 2548 arm,coresight-loses-context-with-cpu; 2549 qcom,skip-power-up; 2550 2551 out-ports { 2552 port { 2553 etm2_out: endpoint { 2554 remote-endpoint = <&funnel_apss_in2>; 2555 }; 2556 }; 2557 }; 2558 }; 2559 2560 cti@7320000 { 2561 compatible = "arm,coresight-cti", "arm,primecell"; 2562 reg = <0x0 0x07320000 0x0 0x1000>; 2563 2564 clocks = <&aoss_qmp>; 2565 clock-names = "apb_pclk"; 2566 }; 2567 2568 etm@7340000 { 2569 compatible = "arm,primecell"; 2570 reg = <0x0 0x07340000 0x0 0x1000>; 2571 cpu = <&cpu3>; 2572 2573 clocks = <&aoss_qmp>; 2574 clock-names = "apb_pclk"; 2575 2576 arm,coresight-loses-context-with-cpu; 2577 qcom,skip-power-up; 2578 2579 out-ports { 2580 port { 2581 etm3_out: endpoint { 2582 remote-endpoint = <&funnel_apss_in3>; 2583 }; 2584 }; 2585 }; 2586 }; 2587 2588 cti@7420000 { 2589 compatible = "arm,coresight-cti", "arm,primecell"; 2590 reg = <0x0 0x07420000 0x0 0x1000>; 2591 2592 clocks = <&aoss_qmp>; 2593 clock-names = "apb_pclk"; 2594 }; 2595 2596 etm@7440000 { 2597 compatible = "arm,primecell"; 2598 reg = <0x0 0x07440000 0x0 0x1000>; 2599 cpu = <&cpu4>; 2600 2601 clocks = <&aoss_qmp>; 2602 clock-names = "apb_pclk"; 2603 2604 arm,coresight-loses-context-with-cpu; 2605 qcom,skip-power-up; 2606 2607 out-ports { 2608 port { 2609 etm4_out: endpoint { 2610 remote-endpoint = <&funnel_apss_in4>; 2611 }; 2612 }; 2613 }; 2614 }; 2615 2616 cti@7520000 { 2617 compatible = "arm,coresight-cti", "arm,primecell"; 2618 reg = <0x0 0x07520000 0x0 0x1000>; 2619 2620 clocks = <&aoss_qmp>; 2621 clock-names = "apb_pclk"; 2622 }; 2623 2624 etm@7540000 { 2625 compatible = "arm,primecell"; 2626 reg = <0x0 0x07540000 0x0 0x1000>; 2627 cpu = <&cpu5>; 2628 2629 clocks = <&aoss_qmp>; 2630 clock-names = "apb_pclk"; 2631 2632 arm,coresight-loses-context-with-cpu; 2633 qcom,skip-power-up; 2634 2635 out-ports { 2636 port { 2637 etm5_out: endpoint { 2638 remote-endpoint = <&funnel_apss_in5>; 2639 }; 2640 }; 2641 }; 2642 }; 2643 2644 cti@7620000 { 2645 compatible = "arm,coresight-cti", "arm,primecell"; 2646 reg = <0x0 0x07620000 0x0 0x1000>; 2647 2648 clocks = <&aoss_qmp>; 2649 clock-names = "apb_pclk"; 2650 }; 2651 2652 etm@7640000 { 2653 compatible = "arm,primecell"; 2654 reg = <0x0 0x07640000 0x0 0x1000>; 2655 cpu = <&cpu6>; 2656 2657 clocks = <&aoss_qmp>; 2658 clock-names = "apb_pclk"; 2659 2660 arm,coresight-loses-context-with-cpu; 2661 qcom,skip-power-up; 2662 2663 out-ports { 2664 port { 2665 etm6_out: endpoint { 2666 remote-endpoint = <&funnel_apss_in6>; 2667 }; 2668 }; 2669 }; 2670 }; 2671 2672 cti@7720000 { 2673 compatible = "arm,coresight-cti", "arm,primecell"; 2674 reg = <0x0 0x07720000 0x0 0x1000>; 2675 2676 clocks = <&aoss_qmp>; 2677 clock-names = "apb_pclk"; 2678 }; 2679 2680 etm@7740000 { 2681 compatible = "arm,primecell"; 2682 reg = <0x0 0x07740000 0x0 0x1000>; 2683 cpu = <&cpu7>; 2684 2685 clocks = <&aoss_qmp>; 2686 clock-names = "apb_pclk"; 2687 2688 arm,coresight-loses-context-with-cpu; 2689 qcom,skip-power-up; 2690 2691 out-ports { 2692 port { 2693 etm7_out: endpoint { 2694 remote-endpoint = <&funnel_apss_in7>; 2695 }; 2696 }; 2697 }; 2698 }; 2699 2700 funnel@7800000 { 2701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2702 reg = <0x0 0x07800000 0x0 0x1000>; 2703 2704 clocks = <&aoss_qmp>; 2705 clock-names = "apb_pclk"; 2706 2707 in-ports { 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 2711 port@0 { 2712 reg = <0>; 2713 2714 funnel_apss_in0: endpoint { 2715 remote-endpoint = <&etm0_out>; 2716 }; 2717 }; 2718 2719 port@1 { 2720 reg = <1>; 2721 2722 funnel_apss_in1: endpoint { 2723 remote-endpoint = <&etm1_out>; 2724 }; 2725 }; 2726 2727 port@2 { 2728 reg = <2>; 2729 2730 funnel_apss_in2: endpoint { 2731 remote-endpoint = <&etm2_out>; 2732 }; 2733 }; 2734 2735 port@3 { 2736 reg = <3>; 2737 2738 funnel_apss_in3: endpoint { 2739 remote-endpoint = <&etm3_out>; 2740 }; 2741 }; 2742 2743 port@4 { 2744 reg = <4>; 2745 2746 funnel_apss_in4: endpoint { 2747 remote-endpoint = <&etm4_out>; 2748 }; 2749 }; 2750 2751 port@5 { 2752 reg = <5>; 2753 2754 funnel_apss_in5: endpoint { 2755 remote-endpoint = <&etm5_out>; 2756 }; 2757 }; 2758 2759 port@6 { 2760 reg = <6>; 2761 2762 funnel_apss_in6: endpoint { 2763 remote-endpoint = <&etm6_out>; 2764 }; 2765 }; 2766 2767 port@7 { 2768 reg = <7>; 2769 2770 funnel_apss_in7: endpoint { 2771 remote-endpoint = <&etm7_out>; 2772 }; 2773 }; 2774 }; 2775 2776 out-ports { 2777 port { 2778 funnel_apss_out: endpoint { 2779 remote-endpoint = <&funnel_apss_merg_in0>; 2780 }; 2781 }; 2782 }; 2783 }; 2784 2785 funnel@7810000 { 2786 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2787 reg = <0x0 0x07810000 0x0 0x1000>; 2788 2789 clocks = <&aoss_qmp>; 2790 clock-names = "apb_pclk"; 2791 2792 in-ports { 2793 #address-cells = <1>; 2794 #size-cells = <0>; 2795 2796 port@0 { 2797 reg = <0>; 2798 2799 funnel_apss_merg_in0: endpoint { 2800 remote-endpoint = <&funnel_apss_out>; 2801 }; 2802 }; 2803 2804 port@2 { 2805 reg = <2>; 2806 2807 funnel_apss_merg_in2: endpoint { 2808 remote-endpoint = <&tpda_olc_out>; 2809 }; 2810 }; 2811 2812 port@3 { 2813 reg = <3>; 2814 2815 funnel_apss_merg_in3: endpoint { 2816 remote-endpoint = <&tpda_llm_silver_out>; 2817 }; 2818 }; 2819 2820 port@4 { 2821 reg = <4>; 2822 2823 funnel_apss_merg_in4: endpoint { 2824 remote-endpoint = <&tpda_llm_gold_out>; 2825 }; 2826 }; 2827 2828 port@5 { 2829 reg = <5>; 2830 2831 funnel_apss_merg_in5: endpoint { 2832 remote-endpoint = <&tpda_apss_out>; 2833 }; 2834 }; 2835 }; 2836 2837 out-ports { 2838 port { 2839 funnel_apss_merg_out: endpoint { 2840 remote-endpoint = <&funnel_in1_in7>; 2841 }; 2842 }; 2843 }; 2844 }; 2845 2846 tpdm@7830000 { 2847 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2848 reg = <0x0 0x07830000 0x0 0x1000>; 2849 2850 clocks = <&aoss_qmp>; 2851 clock-names = "apb_pclk"; 2852 2853 qcom,cmb-element-bits = <64>; 2854 qcom,cmb-msrs-num = <32>; 2855 2856 out-ports { 2857 port { 2858 tpdm_olc_out: endpoint { 2859 remote-endpoint = <&tpda_olc_in>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 2865 tpda@7832000 { 2866 compatible = "qcom,coresight-tpda", "arm,primecell"; 2867 reg = <0x0 0x07832000 0x0 0x1000>; 2868 2869 clocks = <&aoss_qmp>; 2870 clock-names = "apb_pclk"; 2871 2872 in-ports { 2873 port { 2874 tpda_olc_in: endpoint { 2875 remote-endpoint = <&tpdm_olc_out>; 2876 }; 2877 }; 2878 }; 2879 2880 out-ports { 2881 port { 2882 tpda_olc_out: endpoint { 2883 remote-endpoint = <&funnel_apss_merg_in2>; 2884 }; 2885 }; 2886 }; 2887 }; 2888 2889 tpdm@7860000 { 2890 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2891 reg = <0x0 0x07860000 0x0 0x1000>; 2892 2893 clocks = <&aoss_qmp>; 2894 clock-names = "apb_pclk"; 2895 2896 qcom,dsb-element-bits = <32>; 2897 qcom,dsb-msrs-num = <32>; 2898 2899 out-ports { 2900 port { 2901 tpdm_apss_out: endpoint { 2902 remote-endpoint = <&tpda_apss_in>; 2903 }; 2904 }; 2905 }; 2906 }; 2907 2908 tpda@7862000 { 2909 compatible = "qcom,coresight-tpda", "arm,primecell"; 2910 reg = <0x0 0x07862000 0x0 0x1000>; 2911 2912 clocks = <&aoss_qmp>; 2913 clock-names = "apb_pclk"; 2914 2915 in-ports { 2916 port { 2917 tpda_apss_in: endpoint { 2918 remote-endpoint = <&tpdm_apss_out>; 2919 }; 2920 }; 2921 }; 2922 2923 out-ports { 2924 port { 2925 tpda_apss_out: endpoint { 2926 remote-endpoint = <&funnel_apss_merg_in5>; 2927 }; 2928 }; 2929 }; 2930 }; 2931 2932 tpdm@78a0000 { 2933 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2934 reg = <0x0 0x078a0000 0x0 0x1000>; 2935 2936 clocks = <&aoss_qmp>; 2937 clock-names = "apb_pclk"; 2938 2939 qcom,cmb-element-bits = <32>; 2940 qcom,cmb-msrs-num = <32>; 2941 2942 out-ports { 2943 port { 2944 tpdm_llm_silver_out: endpoint { 2945 remote-endpoint = <&tpda_llm_silver_in>; 2946 }; 2947 }; 2948 }; 2949 }; 2950 2951 tpdm@78b0000 { 2952 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2953 reg = <0x0 0x078b0000 0x0 0x1000>; 2954 2955 clocks = <&aoss_qmp>; 2956 clock-names = "apb_pclk"; 2957 2958 qcom,cmb-element-bits = <32>; 2959 qcom,cmb-msrs-num = <32>; 2960 2961 out-ports { 2962 port { 2963 tpdm_llm_gold_out: endpoint { 2964 remote-endpoint = <&tpda_llm_gold_in>; 2965 }; 2966 }; 2967 }; 2968 }; 2969 2970 tpda@78c0000 { 2971 compatible = "qcom,coresight-tpda", "arm,primecell"; 2972 reg = <0x0 0x078c0000 0x0 0x1000>; 2973 2974 clocks = <&aoss_qmp>; 2975 clock-names = "apb_pclk"; 2976 2977 in-ports { 2978 port { 2979 tpda_llm_silver_in: endpoint { 2980 remote-endpoint = <&tpdm_llm_silver_out>; 2981 }; 2982 }; 2983 }; 2984 2985 out-ports { 2986 port { 2987 tpda_llm_silver_out: endpoint { 2988 remote-endpoint = <&funnel_apss_merg_in3>; 2989 }; 2990 }; 2991 }; 2992 }; 2993 2994 tpda@78d0000 { 2995 compatible = "qcom,coresight-tpda", "arm,primecell"; 2996 reg = <0x0 0x078d0000 0x0 0x1000>; 2997 2998 clocks = <&aoss_qmp>; 2999 clock-names = "apb_pclk"; 3000 3001 in-ports { 3002 port { 3003 tpda_llm_gold_in: endpoint { 3004 remote-endpoint = <&tpdm_llm_gold_out>; 3005 }; 3006 }; 3007 }; 3008 3009 out-ports { 3010 port { 3011 tpda_llm_gold_out: endpoint { 3012 remote-endpoint = <&funnel_apss_merg_in4>; 3013 }; 3014 }; 3015 }; 3016 }; 3017 3018 cti@78e0000 { 3019 compatible = "arm,coresight-cti", "arm,primecell"; 3020 reg = <0x0 0x078e0000 0x0 0x1000>; 3021 3022 clocks = <&aoss_qmp>; 3023 clock-names = "apb_pclk"; 3024 }; 3025 3026 cti@78f0000 { 3027 compatible = "arm,coresight-cti", "arm,primecell"; 3028 reg = <0x0 0x078f0000 0x0 0x1000>; 3029 3030 clocks = <&aoss_qmp>; 3031 clock-names = "apb_pclk"; 3032 }; 3033 3034 cti@7900000 { 3035 compatible = "arm,coresight-cti", "arm,primecell"; 3036 reg = <0x0 0x07900000 0x0 0x1000>; 3037 3038 clocks = <&aoss_qmp>; 3039 clock-names = "apb_pclk"; 3040 }; 3041 3042 pmu@90b6300 { 3043 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3044 reg = <0x0 0x090b6300 0x0 0x600>; 3045 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3046 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3047 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3048 3049 operating-points-v2 = <&cpu_bwmon_opp_table>; 3050 3051 cpu_bwmon_opp_table: opp-table { 3052 compatible = "operating-points-v2"; 3053 3054 opp-0 { 3055 opp-peak-kBps = <12896000>; 3056 }; 3057 3058 opp-1 { 3059 opp-peak-kBps = <14928000>; 3060 }; 3061 }; 3062 }; 3063 3064 pmu@90cd000 { 3065 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3066 reg = <0x0 0x090cd000 0x0 0x1000>; 3067 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>; 3068 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3069 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3070 3071 operating-points-v2 = <&llcc_bwmon_opp_table>; 3072 3073 llcc_bwmon_opp_table: opp-table { 3074 compatible = "operating-points-v2"; 3075 3076 opp-0 { 3077 opp-peak-kBps = <800000>; 3078 }; 3079 3080 opp-1 { 3081 opp-peak-kBps = <1200000>; 3082 }; 3083 3084 opp-2 { 3085 opp-peak-kBps = <1804800>; 3086 }; 3087 3088 opp-3 { 3089 opp-peak-kBps = <2188800>; 3090 }; 3091 3092 opp-4 { 3093 opp-peak-kBps = <2726400>; 3094 }; 3095 3096 opp-5 { 3097 opp-peak-kBps = <3072000>; 3098 }; 3099 3100 opp-6 { 3101 opp-peak-kBps = <4070400>; 3102 }; 3103 3104 opp-7 { 3105 opp-peak-kBps = <5414400>; 3106 }; 3107 3108 opp-8 { 3109 opp-peak-kBps = <6220800>; 3110 }; 3111 }; 3112 }; 3113 3114 sdhc_2: mmc@8804000 { 3115 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3116 reg = <0x0 0x08804000 0x0 0x1000>; 3117 reg-names = "hc"; 3118 3119 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3121 interrupt-names = "hc_irq", 3122 "pwr_irq"; 3123 3124 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3125 <&gcc GCC_SDCC2_APPS_CLK>, 3126 <&rpmhcc RPMH_CXO_CLK>; 3127 clock-names = "iface", 3128 "core", 3129 "xo"; 3130 3131 power-domains = <&rpmhpd RPMHPD_CX>; 3132 operating-points-v2 = <&sdhc2_opp_table>; 3133 iommus = <&apps_smmu 0x02a0 0x0>; 3134 resets = <&gcc GCC_SDCC2_BCR>; 3135 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3137 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3138 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3139 interconnect-names = "sdhc-ddr", 3140 "cpu-sdhc"; 3141 3142 qcom,dll-config = <0x0007642c>; 3143 qcom,ddr-config = <0x80040868>; 3144 dma-coherent; 3145 3146 status = "disabled"; 3147 3148 sdhc2_opp_table: opp-table { 3149 compatible = "operating-points-v2"; 3150 3151 opp-50000000 { 3152 opp-hz = /bits/ 64 <50000000>; 3153 required-opps = <&rpmhpd_opp_low_svs>; 3154 }; 3155 3156 opp-100000000 { 3157 opp-hz = /bits/ 64 <100000000>; 3158 required-opps = <&rpmhpd_opp_svs>; 3159 }; 3160 3161 opp-202000000 { 3162 opp-hz = /bits/ 64 <202000000>; 3163 required-opps = <&rpmhpd_opp_nom>; 3164 }; 3165 }; 3166 }; 3167 3168 dc_noc: interconnect@9160000 { 3169 reg = <0x0 0x09160000 0x0 0x3200>; 3170 compatible = "qcom,qcs615-dc-noc"; 3171 #interconnect-cells = <2>; 3172 qcom,bcm-voters = <&apps_bcm_voter>; 3173 }; 3174 3175 llcc: system-cache-controller@9200000 { 3176 compatible = "qcom,qcs615-llcc"; 3177 reg = <0x0 0x09200000 0x0 0x50000>, 3178 <0x0 0x09600000 0x0 0x50000>; 3179 reg-names = "llcc0_base", 3180 "llcc_broadcast_base"; 3181 }; 3182 3183 gem_noc: interconnect@9680000 { 3184 reg = <0x0 0x09680000 0x0 0x3e200>; 3185 compatible = "qcom,qcs615-gem-noc"; 3186 #interconnect-cells = <2>; 3187 qcom,bcm-voters = <&apps_bcm_voter>; 3188 }; 3189 3190 pdc: interrupt-controller@b220000 { 3191 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 3192 reg = <0x0 0x0b220000 0x0 0x30000>, 3193 <0x0 0x17c000f0 0x0 0x64>; 3194 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3195 interrupt-parent = <&intc>; 3196 #interrupt-cells = <2>; 3197 interrupt-controller; 3198 }; 3199 3200 aoss_qmp: power-controller@c300000 { 3201 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 3202 reg = <0x0 0x0c300000 0x0 0x400>; 3203 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3204 mboxes = <&apss_shared 0>; 3205 3206 #clock-cells = <0>; 3207 #power-domain-cells = <1>; 3208 }; 3209 3210 sram@c3f0000 { 3211 compatible = "qcom,rpmh-stats"; 3212 reg = <0x0 0x0c3f0000 0x0 0x400>; 3213 }; 3214 3215 apps_smmu: iommu@15000000 { 3216 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3217 reg = <0x0 0x15000000 0x0 0x80000>; 3218 #iommu-cells = <2>; 3219 #global-interrupts = <1>; 3220 dma-coherent; 3221 3222 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 3287 }; 3288 3289 spmi_bus: spmi@c440000 { 3290 compatible = "qcom,spmi-pmic-arb"; 3291 reg = <0x0 0x0c440000 0x0 0x1100>, 3292 <0x0 0x0c600000 0x0 0x2000000>, 3293 <0x0 0x0e600000 0x0 0x100000>, 3294 <0x0 0x0e700000 0x0 0xa0000>, 3295 <0x0 0x0c40a000 0x0 0x26000>; 3296 reg-names = "core", 3297 "chnls", 3298 "obsrvr", 3299 "intr", 3300 "cnfg"; 3301 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3302 interrupt-names = "periph_irq"; 3303 interrupt-controller; 3304 #interrupt-cells = <4>; 3305 #address-cells = <2>; 3306 #size-cells = <0>; 3307 cell-index = <0>; 3308 qcom,channel = <0>; 3309 qcom,ee = <0>; 3310 }; 3311 3312 intc: interrupt-controller@17a00000 { 3313 compatible = "arm,gic-v3"; 3314 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3315 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3316 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3317 #interrupt-cells = <3>; 3318 interrupt-controller; 3319 #redistributor-regions = <1>; 3320 redistributor-stride = <0x0 0x20000>; 3321 }; 3322 3323 apss_shared: mailbox@17c00000 { 3324 compatible = "qcom,qcs615-apss-shared", 3325 "qcom,sdm845-apss-shared"; 3326 reg = <0x0 0x17c00000 0x0 0x1000>; 3327 #mbox-cells = <1>; 3328 }; 3329 3330 watchdog: watchdog@17c10000 { 3331 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 3332 reg = <0x0 0x17c10000 0x0 0x1000>; 3333 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3334 }; 3335 3336 timer@17c20000 { 3337 compatible = "arm,armv7-timer-mem"; 3338 reg = <0x0 0x17c20000 0x0 0x1000>; 3339 ranges = <0 0 0 0x20000000>; 3340 #address-cells = <1>; 3341 #size-cells = <1>; 3342 3343 frame@17c21000 { 3344 reg = <0x17c21000 0x1000>, 3345 <0x17c22000 0x1000>; 3346 frame-number = <0>; 3347 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3349 }; 3350 3351 frame@17c23000 { 3352 reg = <0x17c23000 0x1000>; 3353 frame-number = <1>; 3354 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3355 status = "disabled"; 3356 }; 3357 3358 frame@17c25000 { 3359 reg = <0x17c25000 0x1000>; 3360 frame-number = <2>; 3361 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3362 status = "disabled"; 3363 }; 3364 3365 frame@17c27000 { 3366 reg = <0x17c27000 0x1000>; 3367 frame-number = <3>; 3368 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3369 status = "disabled"; 3370 }; 3371 3372 frame@17c29000 { 3373 reg = <0x17c29000 0x1000>; 3374 frame-number = <4>; 3375 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3376 status = "disabled"; 3377 }; 3378 3379 frame@17c2b000 { 3380 reg = <0x17c2b000 0x1000>; 3381 frame-number = <5>; 3382 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3383 status = "disabled"; 3384 }; 3385 3386 frame@17c2d000 { 3387 reg = <0x17c2d000 0x1000>; 3388 frame-number = <6>; 3389 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3390 status = "disabled"; 3391 }; 3392 }; 3393 3394 apps_rsc: rsc@18200000 { 3395 compatible = "qcom,rpmh-rsc"; 3396 reg = <0x0 0x18200000 0x0 0x10000>, 3397 <0x0 0x18210000 0x0 0x10000>, 3398 <0x0 0x18220000 0x0 0x10000>; 3399 reg-names = "drv-0", 3400 "drv-1", 3401 "drv-2"; 3402 3403 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3406 3407 qcom,drv-id = <2>; 3408 qcom,tcs-offset = <0xd00>; 3409 qcom,tcs-config = <ACTIVE_TCS 2>, 3410 <SLEEP_TCS 3>, 3411 <WAKE_TCS 3>, 3412 <CONTROL_TCS 1>; 3413 3414 label = "apps_rsc"; 3415 power-domains = <&cluster_pd>; 3416 3417 apps_bcm_voter: bcm-voter { 3418 compatible = "qcom,bcm-voter"; 3419 }; 3420 3421 rpmhcc: clock-controller { 3422 compatible = "qcom,qcs615-rpmh-clk"; 3423 clock-names = "xo"; 3424 3425 #clock-cells = <1>; 3426 }; 3427 3428 rpmhpd: power-controller { 3429 compatible = "qcom,qcs615-rpmhpd"; 3430 #power-domain-cells = <1>; 3431 operating-points-v2 = <&rpmhpd_opp_table>; 3432 3433 rpmhpd_opp_table: opp-table { 3434 compatible = "operating-points-v2"; 3435 3436 rpmhpd_opp_ret: opp-0 { 3437 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3438 }; 3439 3440 rpmhpd_opp_min_svs: opp-1 { 3441 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3442 }; 3443 3444 rpmhpd_opp_low_svs: opp-2 { 3445 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3446 }; 3447 3448 rpmhpd_opp_svs: opp-3 { 3449 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3450 }; 3451 3452 rpmhpd_opp_svs_l1: opp-4 { 3453 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3454 }; 3455 3456 rpmhpd_opp_nom: opp-5 { 3457 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3458 }; 3459 3460 rpmhpd_opp_nom_l1: opp-6 { 3461 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3462 }; 3463 3464 rpmhpd_opp_nom_l2: opp-7 { 3465 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3466 }; 3467 3468 rpmhpd_opp_turbo: opp-8 { 3469 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3470 }; 3471 3472 rpmhpd_opp_turbo_l1: opp-9 { 3473 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3474 }; 3475 }; 3476 }; 3477 }; 3478 3479 usb_1_hsphy: phy@88e2000 { 3480 compatible = "qcom,qcs615-qusb2-phy"; 3481 reg = <0x0 0x88e2000 0x0 0x180>; 3482 3483 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 3484 clock-names = "cfg_ahb", "ref"; 3485 3486 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3487 nvmem-cells = <&qusb2_hstx_trim>; 3488 3489 #phy-cells = <0>; 3490 3491 status = "disabled"; 3492 }; 3493 3494 usb_hsphy_2: phy@88e3000 { 3495 compatible = "qcom,qcs615-qusb2-phy"; 3496 reg = <0x0 0x088e3000 0x0 0x180>; 3497 3498 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 3499 <&rpmhcc RPMH_CXO_CLK>; 3500 clock-names = "cfg_ahb", 3501 "ref"; 3502 3503 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3504 3505 #phy-cells = <0>; 3506 3507 status = "disabled"; 3508 }; 3509 3510 usb_qmpphy: phy@88e6000 { 3511 compatible = "qcom,qcs615-qmp-usb3-phy"; 3512 reg = <0x0 0x88e6000 0x0 0x1000>; 3513 3514 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3515 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3516 <&gcc GCC_AHB2PHY_WEST_CLK>, 3517 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3518 clock-names = "aux", 3519 "ref", 3520 "cfg_ahb", 3521 "pipe"; 3522 3523 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 3524 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 3525 reset-names = "phy", "phy_phy"; 3526 3527 qcom,tcsr-reg = <&tcsr 0xb244>; 3528 3529 clock-output-names = "usb3_phy_pipe_clk_src"; 3530 #clock-cells = <0>; 3531 3532 #phy-cells = <0>; 3533 3534 status = "disabled"; 3535 }; 3536 3537 usb_1: usb@a6f8800 { 3538 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 3539 reg = <0x0 0x0a6f8800 0x0 0x400>; 3540 3541 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3542 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3543 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3544 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3545 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3546 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 3547 clock-names = "cfg_noc", 3548 "core", 3549 "iface", 3550 "sleep", 3551 "mock_utmi", 3552 "xo"; 3553 3554 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3555 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3556 assigned-clock-rates = <19200000>, <200000000>; 3557 3558 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3559 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3560 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3561 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3562 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3563 interrupt-names = "pwr_event", 3564 "hs_phy_irq", 3565 "dp_hs_phy_irq", 3566 "dm_hs_phy_irq", 3567 "ss_phy_irq"; 3568 3569 power-domains = <&gcc USB30_PRIM_GDSC>; 3570 required-opps = <&rpmhpd_opp_nom>; 3571 3572 resets = <&gcc GCC_USB30_PRIM_BCR>; 3573 3574 #address-cells = <2>; 3575 #size-cells = <2>; 3576 ranges; 3577 3578 status = "disabled"; 3579 3580 usb_1_dwc3: usb@a600000 { 3581 compatible = "snps,dwc3"; 3582 reg = <0x0 0x0a600000 0x0 0xcd00>; 3583 3584 iommus = <&apps_smmu 0x140 0x0>; 3585 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3586 3587 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 3588 phy-names = "usb2-phy", "usb3-phy"; 3589 3590 snps,dis-u1-entry-quirk; 3591 snps,dis-u2-entry-quirk; 3592 snps,dis_u2_susphy_quirk; 3593 snps,dis_enblslpm_quirk; 3594 snps,has-lpm-erratum; 3595 snps,hird-threshold = /bits/ 8 <0x10>; 3596 snps,usb3_lpm_capable; 3597 }; 3598 }; 3599 3600 usb_2: usb@a8f8800 { 3601 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 3602 reg = <0x0 0x0a8f8800 0x0 0x400>; 3603 3604 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 3605 <&gcc GCC_USB20_SEC_MASTER_CLK>, 3606 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 3607 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 3608 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 3609 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 3610 clock-names = "cfg_noc", 3611 "core", 3612 "iface", 3613 "sleep", 3614 "mock_utmi", 3615 "xo"; 3616 3617 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 3618 <&gcc GCC_USB20_SEC_MASTER_CLK>; 3619 assigned-clock-rates = <19200000>, <200000000>; 3620 3621 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, 3622 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3623 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3624 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 3625 interrupt-names = "pwr_event", 3626 "hs_phy_irq", 3627 "dp_hs_phy_irq", 3628 "dm_hs_phy_irq"; 3629 3630 power-domains = <&gcc USB20_SEC_GDSC>; 3631 required-opps = <&rpmhpd_opp_nom>; 3632 3633 resets = <&gcc GCC_USB20_SEC_BCR>; 3634 3635 qcom,select-utmi-as-pipe-clk; 3636 3637 #address-cells = <2>; 3638 #size-cells = <2>; 3639 ranges; 3640 3641 status = "disabled"; 3642 3643 usb_2_dwc3: usb@a800000 { 3644 compatible = "snps,dwc3"; 3645 reg = <0x0 0x0a800000 0x0 0xcd00>; 3646 3647 iommus = <&apps_smmu 0xe0 0x0>; 3648 interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>; 3649 3650 phys = <&usb_hsphy_2>; 3651 phy-names = "usb2-phy"; 3652 3653 snps,dis_u2_susphy_quirk; 3654 snps,dis_enblslpm_quirk; 3655 snps,has-lpm-erratum; 3656 snps,hird-threshold = /bits/ 8 <0x10>; 3657 3658 maximum-speed = "high-speed"; 3659 }; 3660 }; 3661 }; 3662 3663 arch_timer: timer { 3664 compatible = "arm,armv8-timer"; 3665 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3666 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3667 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3668 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3669 }; 3670}; 3671