1// SPDX-License-Identifier: GPL-2.0-only 2 3#include <dt-bindings/clock/qcom,gcc-msm8917.h> 4#include <dt-bindings/clock/qcom,rpmcc.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/power/qcom-rpmpd.h> 7#include <dt-bindings/thermal/thermal.h> 8 9/ { 10 interrupt-parent = <&intc>; 11 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 chosen { }; 16 17 clocks { 18 sleep_clk: sleep-clk { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 }; 22 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@100 { 34 compatible = "arm,cortex-a53"; 35 reg = <0x100>; 36 device_type = "cpu"; 37 next-level-cache = <&l2_0>; 38 enable-method = "psci"; 39 clocks = <&apcs>; 40 operating-points-v2 = <&cpu_opp_table>; 41 #cooling-cells = <2>; 42 power-domains = <&cpu_pd0>; 43 power-domain-names = "psci"; 44 45 l2_0: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-unified; 49 }; 50 }; 51 52 cpu1: cpu@101 { 53 compatible = "arm,cortex-a53"; 54 reg = <0x101>; 55 device_type = "cpu"; 56 next-level-cache = <&l2_0>; 57 enable-method = "psci"; 58 clocks = <&apcs>; 59 operating-points-v2 = <&cpu_opp_table>; 60 #cooling-cells = <2>; 61 power-domains = <&cpu_pd1>; 62 power-domain-names = "psci"; 63 }; 64 65 cpu2: cpu@102 { 66 compatible = "arm,cortex-a53"; 67 reg = <0x102>; 68 device_type = "cpu"; 69 next-level-cache = <&l2_0>; 70 enable-method = "psci"; 71 clocks = <&apcs>; 72 operating-points-v2 = <&cpu_opp_table>; 73 #cooling-cells = <2>; 74 power-domains = <&cpu_pd2>; 75 power-domain-names = "psci"; 76 }; 77 78 cpu3: cpu@103 { 79 compatible = "arm,cortex-a53"; 80 reg = <0x103>; 81 device_type = "cpu"; 82 next-level-cache = <&l2_0>; 83 enable-method = "psci"; 84 clocks = <&apcs>; 85 operating-points-v2 = <&cpu_opp_table>; 86 #cooling-cells = <2>; 87 power-domains = <&cpu_pd3>; 88 power-domain-names = "psci"; 89 }; 90 91 cpu-map { 92 cluster0 { 93 core0 { 94 cpu = <&cpu0>; 95 }; 96 97 core1 { 98 cpu = <&cpu1>; 99 }; 100 101 core2 { 102 cpu = <&cpu2>; 103 }; 104 105 core3 { 106 cpu = <&cpu3>; 107 }; 108 }; 109 }; 110 111 domain-idle-states { 112 cluster_sleep_0: cluster-sleep-0 { 113 compatible = "domain-idle-state"; 114 arm,psci-suspend-param = <0x41000053>; 115 entry-latency-us = <700>; 116 exit-latency-us = <1000>; 117 min-residency-us = <6500>; 118 }; 119 }; 120 121 idle-states { 122 entry-method = "psci"; 123 124 cpu_sleep_0: cpu-sleep-0 { 125 compatible = "arm,idle-state"; 126 idle-state-name = "standalone-power-collapse"; 127 arm,psci-suspend-param = <0x40000003>; 128 entry-latency-us = <125>; 129 exit-latency-us = <180>; 130 min-residency-us = <595>; 131 local-timer-stop; 132 }; 133 }; 134 135 cpu_opp_table: opp-table-cpu { 136 compatible = "operating-points-v2"; 137 opp-shared; 138 139 opp-960000000 { 140 opp-hz = /bits/ 64 <960000000>; 141 }; 142 143 opp-1094400000 { 144 opp-hz = /bits/ 64 <1094400000>; 145 }; 146 147 opp-1248000000 { 148 opp-hz = /bits/ 64 <1248000000>; 149 }; 150 151 opp-1401600000 { 152 opp-hz = /bits/ 64 <1401600000>; 153 }; 154 }; 155 }; 156 157 firmware { 158 scm: scm { 159 compatible = "qcom,scm-msm8916", "qcom,scm"; 160 clocks = <&gcc GCC_CRYPTO_CLK>, 161 <&gcc GCC_CRYPTO_AXI_CLK>, 162 <&gcc GCC_CRYPTO_AHB_CLK>; 163 clock-names = "core", "bus", "iface"; 164 #reset-cells = <1>; 165 166 qcom,dload-mode = <&tcsr 0x6100>; 167 }; 168 }; 169 170 memory@80000000 { 171 /* We expect the bootloader to fill in the reg */ 172 reg = <0 0x80000000 0 0>; 173 device_type = "memory"; 174 }; 175 176 pmu { 177 compatible = "arm,cortex-a53-pmu"; 178 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 179 }; 180 181 psci { 182 compatible = "arm,psci-1.0"; 183 method = "smc"; 184 185 cluster_pd: power-domain-cluster { 186 #power-domain-cells = <0>; 187 domain-idle-states = <&cluster_sleep_0>; 188 }; 189 190 cpu_pd0: power-domain-cpu0 { 191 #power-domain-cells = <0>; 192 power-domains = <&cluster_pd>; 193 domain-idle-states = <&cpu_sleep_0>; 194 }; 195 196 cpu_pd1: power-domain-cpu1 { 197 #power-domain-cells = <0>; 198 power-domains = <&cluster_pd>; 199 domain-idle-states = <&cpu_sleep_0>; 200 }; 201 202 cpu_pd2: power-domain-cpu2 { 203 #power-domain-cells = <0>; 204 power-domains = <&cluster_pd>; 205 domain-idle-states = <&cpu_sleep_0>; 206 }; 207 208 cpu_pd3: power-domain-cpu3 { 209 #power-domain-cells = <0>; 210 power-domains = <&cluster_pd>; 211 domain-idle-states = <&cpu_sleep_0>; 212 }; 213 }; 214 215 rpm: remoteproc { 216 compatible = "qcom,msm8917-rpm-proc", "qcom,rpm-proc"; 217 218 smd-edge { 219 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 220 qcom,ipc = <&apcs 8 0>; 221 qcom,smd-edge = <15>; 222 223 rpm_requests: rpm-requests { 224 compatible = "qcom,rpm-msm8917", "qcom,smd-rpm"; 225 qcom,smd-channels = "rpm_requests"; 226 227 rpmcc: clock-controller { 228 compatible = "qcom,rpmcc-msm8917", "qcom,rpmcc"; 229 #clock-cells = <1>; 230 clocks = <&xo_board>; 231 clock-names = "xo"; 232 }; 233 234 rpmpd: power-controller { 235 compatible = "qcom,msm8917-rpmpd"; 236 #power-domain-cells = <1>; 237 operating-points-v2 = <&rpmpd_opp_table>; 238 239 rpmpd_opp_table: opp-table { 240 compatible = "operating-points-v2"; 241 242 rpmpd_opp_ret: opp1 { 243 opp-level = <RPM_SMD_LEVEL_RETENTION>; 244 }; 245 246 rpmpd_opp_ret_plus: opp2 { 247 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 248 }; 249 250 rpmpd_opp_min_svs: opp3 { 251 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 252 }; 253 254 rpmpd_opp_low_svs: opp4 { 255 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 256 }; 257 258 rpmpd_opp_svs: opp5 { 259 opp-level = <RPM_SMD_LEVEL_SVS>; 260 }; 261 262 rpmpd_opp_svs_plus: opp6 { 263 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 264 }; 265 266 rpmpd_opp_nom: opp7 { 267 opp-level = <RPM_SMD_LEVEL_NOM>; 268 }; 269 270 rpmpd_opp_nom_plus: opp8 { 271 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 272 }; 273 274 rpmpd_opp_turbo: opp9 { 275 opp-level = <RPM_SMD_LEVEL_TURBO>; 276 }; 277 }; 278 }; 279 }; 280 }; 281 }; 282 283 reserved-memory { 284 ranges; 285 #address-cells = <2>; 286 #size-cells = <2>; 287 288 qseecom_mem: qseecom@85b00000 { 289 reg = <0x0 0x85b00000 0x0 0x800000>; 290 no-map; 291 }; 292 293 smem@86300000 { 294 compatible = "qcom,smem"; 295 reg = <0x0 0x86300000 0x0 0x100000>; 296 no-map; 297 298 hwlocks = <&tcsr_mutex 3>; 299 qcom,rpm-msg-ram = <&rpm_msg_ram>; 300 }; 301 302 reserved@86400000 { 303 reg = <0x0 0x86400000 0x0 0x400000>; 304 no-map; 305 }; 306 307 rmtfs@92100000 { 308 compatible = "qcom,rmtfs-mem"; 309 reg = <0x0 0x92100000 0x0 0x180000>; 310 no-map; 311 312 qcom,client-id = <1>; 313 }; 314 315 adsp_mem: adsp { 316 size = <0x0 0x1100000>; 317 alignment = <0x0 0x100000>; 318 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 319 no-map; 320 status = "disabled"; 321 }; 322 323 mba_mem: mba { 324 size = <0x0 0x100000>; 325 alignment = <0x0 0x100000>; 326 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 327 no-map; 328 status = "disabled"; 329 }; 330 331 venus_mem: venus { 332 size = <0x0 0x400000>; 333 alignment = <0x0 0x100000>; 334 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 335 no-map; 336 status = "disabled"; 337 }; 338 339 wcnss_mem: wcnss { 340 size = <0x0 0x700000>; 341 alignment = <0x0 0x100000>; 342 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 343 no-map; 344 status = "disabled"; 345 }; 346 }; 347 348 smp2p-adsp { 349 compatible = "qcom,smp2p"; 350 qcom,smem = <443>, <429>; 351 352 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 353 354 mboxes = <&apcs 10>; 355 356 qcom,local-pid = <0>; 357 qcom,remote-pid = <2>; 358 359 adsp_smp2p_out: master-kernel { 360 qcom,entry-name = "master-kernel"; 361 362 #qcom,smem-state-cells = <1>; 363 }; 364 365 adsp_smp2p_in: slave-kernel { 366 qcom,entry-name = "slave-kernel"; 367 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 }; 372 373 smp2p-modem { 374 compatible = "qcom,smp2p"; 375 qcom,smem = <435>, <428>; 376 377 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 378 379 mboxes = <&apcs 14>; 380 381 qcom,local-pid = <0>; 382 qcom,remote-pid = <1>; 383 384 modem_smp2p_out: master-kernel { 385 qcom,entry-name = "master-kernel"; 386 387 #qcom,smem-state-cells = <1>; 388 }; 389 390 modem_smp2p_in: slave-kernel { 391 qcom,entry-name = "slave-kernel"; 392 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 }; 397 398 smp2p-wcnss { 399 compatible = "qcom,smp2p"; 400 qcom,smem = <451>, <431>; 401 402 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 403 404 mboxes = <&apcs 18>; 405 406 qcom,local-pid = <0>; 407 qcom,remote-pid = <4>; 408 409 wcnss_smp2p_out: master-kernel { 410 qcom,entry-name = "master-kernel"; 411 412 #qcom,smem-state-cells = <1>; 413 }; 414 415 wcnss_smp2p_in: slave-kernel { 416 qcom,entry-name = "slave-kernel"; 417 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smsm { 424 compatible = "qcom,smsm"; 425 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; 430 431 apps_smsm: apps@0 { 432 reg = <0>; 433 434 #qcom,smem-state-cells = <1>; 435 }; 436 437 hexagon_smsm: hexagon@1 { 438 reg = <1>; 439 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 440 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 }; 444 445 wcnss_smsm: wcnss@6 { 446 reg = <6>; 447 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 448 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 }; 452 }; 453 454 soc: soc@0 { 455 compatible = "simple-bus"; 456 ranges = <0 0 0 0xffffffff>; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 460 rpm_msg_ram: sram@60000 { 461 compatible = "qcom,rpm-msg-ram"; 462 reg = <0x00060000 0x8000>; 463 }; 464 465 usb_hs_phy: phy@6c000 { 466 compatible = "qcom,usb-hs-28nm-femtophy"; 467 reg = <0x0006c000 0x200>; 468 #phy-cells = <0>; 469 clocks = <&xo_board>, 470 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 471 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 472 clock-names = "ref", "ahb", "sleep"; 473 resets = <&gcc GCC_QUSB2_PHY_BCR>, 474 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 475 reset-names = "phy", "por"; 476 status = "disabled"; 477 }; 478 479 qfprom: qfprom@a4000 { 480 compatible = "qcom,msm8917-qfprom", "qcom,qfprom"; 481 reg = <0x000a4000 0x1000>; 482 #address-cells = <1>; 483 #size-cells = <1>; 484 485 tsens_base1: base1@1d8 { 486 reg = <0x1d8 1>; 487 bits = <0 8>; 488 }; 489 490 tsens_s5_p1: s5-p1@1d9 { 491 reg = <0x1d9 1>; 492 bits = <0 6>; 493 }; 494 495 tsens_s5_p2: s5-p2@1d9 { 496 reg = <0x1d9 2>; 497 bits = <6 6>; 498 }; 499 500 tsens_s6_p1: s6-p1@1da { 501 reg = <0x1da 2>; 502 bits = <4 6>; 503 }; 504 505 tsens_s6_p2: s6-p2@1db { 506 reg = <0x1db 1>; 507 bits = <2 6>; 508 }; 509 510 tsens_s7_p1: s7-p1@1dc { 511 reg = <0x1dc 1>; 512 bits = <0 6>; 513 }; 514 515 tsens_s7_p2: s7-p2@1dc { 516 reg = <0x1dc 2>; 517 bits = <6 6>; 518 }; 519 520 tsens_s8_p1: s8-p1@1dd { 521 reg = <0x1dd 2>; 522 bits = <4 6>; 523 }; 524 525 tsens_s8_p2: s8-p2@1de { 526 reg = <0x1de 1>; 527 bits = <2 6>; 528 }; 529 530 tsens_base2: base2@1df { 531 reg = <0x1df 1>; 532 bits = <0 8>; 533 }; 534 535 tsens_mode: mode@210 { 536 reg = <0x210 1>; 537 bits = <0 3>; 538 }; 539 540 tsens_s0_p1: s0-p1@210 { 541 reg = <0x210 2>; 542 bits = <3 6>; 543 }; 544 545 tsens_s0_p2: s0-p2@211 { 546 reg = <0x211 1>; 547 bits = <1 6>; 548 }; 549 550 tsens_s1_p1: s1-p1@211 { 551 reg = <0x211 2>; 552 bits = <7 6>; 553 }; 554 555 tsens_s1_p2: s1-p2@212 { 556 reg = <0x212 2>; 557 bits = <5 6>; 558 }; 559 560 tsens_s2_p1: s2-p1@213 { 561 reg = <0x213 2>; 562 bits = <3 6>; 563 }; 564 565 tsens_s2_p2: s2-p2@214 { 566 reg = <0x214 1>; 567 bits = <1 6>; 568 }; 569 570 tsens_s3_p1: s3-p1@214 { 571 reg = <0x214 2>; 572 bits = <7 6>; 573 }; 574 575 tsens_s3_p2: s3-p2@215 { 576 reg = <0x215 2>; 577 bits = <5 6>; 578 }; 579 580 tsens_s4_p1: s4-p1@216 { 581 reg = <0x216 2>; 582 bits = <3 6>; 583 }; 584 585 tsens_s4_p2: s4-p2@217 { 586 reg = <0x217 1>; 587 bits = <1 6>; 588 }; 589 590 tsens_s9_p1: s9-p1@230{ 591 reg = <0x230 1>; 592 bits = <0 6>; 593 }; 594 595 tsens_s9_p2: s9-p2@230 { 596 reg = <0x230 2>; 597 bits = <6 6>; 598 }; 599 600 tsens_s10_p1: s10-p1@231 { 601 reg = <0x231 2>; 602 bits = <4 6>; 603 }; 604 605 tsens_s10_p2: s10-p2@232 { 606 reg = <0x232 1>; 607 bits = <2 6>; 608 }; 609 }; 610 611 rng@e3000 { 612 compatible = "qcom,prng"; 613 reg = <0x000e3000 0x1000>; 614 clocks = <&gcc GCC_PRNG_AHB_CLK>; 615 clock-names = "core"; 616 }; 617 618 tsens: thermal-sensor@4a9000 { 619 compatible = "qcom,msm8937-tsens", "qcom,tsens-v1"; 620 reg = <0x004a9000 0x1000>, 621 <0x004a8000 0x1000>; 622 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "uplow"; 624 nvmem-cells = <&tsens_mode>, 625 <&tsens_base1>, <&tsens_base2>, 626 <&tsens_s0_p1>, <&tsens_s0_p2>, 627 <&tsens_s1_p1>, <&tsens_s1_p2>, 628 <&tsens_s2_p1>, <&tsens_s2_p2>, 629 <&tsens_s3_p1>, <&tsens_s3_p2>, 630 <&tsens_s4_p1>, <&tsens_s4_p2>, 631 <&tsens_s5_p1>, <&tsens_s5_p2>, 632 <&tsens_s6_p1>, <&tsens_s6_p2>, 633 <&tsens_s7_p1>, <&tsens_s7_p2>, 634 <&tsens_s8_p1>, <&tsens_s8_p2>, 635 <&tsens_s9_p1>, <&tsens_s9_p2>, 636 <&tsens_s10_p1>, <&tsens_s10_p2>; 637 nvmem-cell-names = "mode", 638 "base1", "base2", 639 "s0_p1", "s0_p2", 640 "s1_p1", "s1_p2", 641 "s2_p1", "s2_p2", 642 "s3_p1", "s3_p2", 643 "s4_p1", "s4_p2", 644 "s5_p1", "s5_p2", 645 "s6_p1", "s6_p2", 646 "s7_p1", "s7_p2", 647 "s8_p1", "s8_p2", 648 "s9_p1", "s9_p2", 649 "s10_p1", "s10_p2"; 650 #qcom,sensors = <11>; 651 #thermal-sensor-cells = <1>; 652 }; 653 654 restart@4ab000 { 655 compatible = "qcom,pshold"; 656 reg = <0x004ab000 0x4>; 657 }; 658 659 tlmm: pinctrl@1000000 { 660 compatible = "qcom,msm8917-pinctrl"; 661 reg = <0x01000000 0x300000>; 662 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 663 gpio-controller; 664 gpio-ranges = <&tlmm 0 0 134>; 665 #gpio-cells = <2>; 666 interrupt-controller; 667 #interrupt-cells = <2>; 668 669 blsp1_i2c2_default: blsp1-i2c2-default-state { 670 pins = "gpio6", "gpio7"; 671 function = "blsp_i2c2"; 672 drive-strength = <2>; 673 bias-disable; 674 }; 675 676 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 677 pins = "gpio6", "gpio7"; 678 function = "gpio"; 679 drive-strength = <2>; 680 bias-disable; 681 }; 682 683 blsp1_i2c3_default: blsp1-i2c3-default-state { 684 pins = "gpio10", "gpio11"; 685 function = "blsp_i2c3"; 686 drive-strength = <2>; 687 bias-disable; 688 }; 689 690 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 691 pins = "gpio10", "gpio11"; 692 function = "gpio"; 693 drive-strength = <2>; 694 bias-disable; 695 }; 696 697 blsp1_i2c4_default: blsp1-i2c4-default-state { 698 pins = "gpio14", "gpio15"; 699 function = "blsp_i2c4"; 700 drive-strength = <2>; 701 bias-disable; 702 }; 703 704 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 705 pins = "gpio14", "gpio15"; 706 function = "gpio"; 707 drive-strength = <2>; 708 bias-disable; 709 }; 710 711 blsp2_i2c1_default: blsp2-i2c1-default-state { 712 pins = "gpio18", "gpio19"; 713 function = "blsp_i2c5"; 714 drive-strength = <2>; 715 bias-disable; 716 }; 717 718 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 719 pins = "gpio18", "gpio19"; 720 function = "gpio"; 721 drive-strength = <2>; 722 bias-disable; 723 }; 724 725 blsp1_spi3_default: blsp1-spi3-default-state { 726 cs-pins { 727 pins = "gpio10"; 728 function = "blsp_spi3"; 729 drive-strength = <2>; 730 bias-disable; 731 }; 732 733 spi-pins { 734 pins = "gpio8", "gpio9", "gpio11"; 735 function = "blsp_spi3"; 736 drive-strength = <12>; 737 bias-disable; 738 }; 739 }; 740 741 blsp1_spi3_sleep: blsp1-spi3-sleep-state { 742 cs-pins { 743 pins = "gpio10"; 744 function = "gpio"; 745 drive-strength = <2>; 746 bias-disable; 747 }; 748 749 spi-pins { 750 pins = "gpio8", "gpio9", "gpio11"; 751 function = "gpio"; 752 drive-strength = <2>; 753 bias-pull-down; 754 }; 755 }; 756 757 blsp2_spi2_default: blsp2-spi2-default-state { 758 cs0-pins { 759 pins = "gpio47"; 760 function = "blsp_spi6"; 761 drive-strength = <16>; 762 bias-disable; 763 }; 764 765 cs1-pins { 766 pins = "gpio22"; 767 function = "blsp_spi6"; 768 drive-strength = <16>; 769 bias-disable; 770 }; 771 772 spi-pins { 773 pins = "gpio20", "gpio21", "gpio23"; 774 function = "blsp_spi6"; 775 drive-strength = <16>; 776 bias-disable; 777 }; 778 }; 779 780 blsp2_spi2_sleep: blsp2-spi2-sleep-state { 781 cs0-pins { 782 pins = "gpio47"; 783 function = "gpio"; 784 drive-strength = <2>; 785 bias-disable; 786 }; 787 788 cs1-pins { 789 pins = "gpio22"; 790 function = "gpio"; 791 drive-strength = <2>; 792 bias-disable; 793 }; 794 795 spi-pins { 796 pins = "gpio20", "gpio21", "gpio23"; 797 function = "gpio"; 798 drive-strength = <2>; 799 bias-pull-down; 800 }; 801 }; 802 803 blsp1_uart1_default: blsp1-uart1-default-state { 804 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 805 function = "blsp_uart1"; 806 drive-strength = <2>; 807 bias-disable; 808 }; 809 810 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 811 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 812 function = "gpio"; 813 drive-strength = <2>; 814 bias-disable; 815 }; 816 817 blsp1_uart2_default: blsp1-uart2-default-state { 818 pins = "gpio4", "gpio5"; 819 function = "blsp_uart2"; 820 drive-strength = <2>; 821 bias-disable; 822 }; 823 824 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 825 pins = "gpio4", "gpio5"; 826 function = "gpio"; 827 drive-strength = <2>; 828 bias-pull-down; 829 }; 830 831 sdc1_default: sdc1-default-state { 832 clk-pins { 833 pins = "sdc1_clk"; 834 bias-disable; 835 drive-strength = <16>; 836 }; 837 838 cmd-pins { 839 pins = "sdc1_cmd"; 840 bias-pull-up; 841 drive-strength = <10>; 842 }; 843 844 data-pins { 845 pins = "sdc1_data"; 846 bias-pull-up; 847 drive-strength = <10>; 848 }; 849 850 rclk-pins { 851 pins = "sdc1_rclk"; 852 bias-pull-down; 853 }; 854 }; 855 856 sdc1_sleep: sdc1-sleep-state { 857 clk-pins { 858 pins = "sdc1_clk"; 859 bias-disable; 860 drive-strength = <2>; 861 }; 862 863 cmd-pins { 864 pins = "sdc1_cmd"; 865 bias-pull-up; 866 drive-strength = <2>; 867 }; 868 869 data-pins { 870 pins = "sdc1_data"; 871 bias-pull-up; 872 drive-strength = <2>; 873 }; 874 875 rclk-pins { 876 pins = "sdc1_rclk"; 877 bias-pull-down; 878 }; 879 }; 880 881 sdc2_default: sdc2-default-state { 882 clk-pins { 883 pins = "sdc2_clk"; 884 bias-disable; 885 drive-strength = <16>; 886 }; 887 888 cmd-pins { 889 pins = "sdc2_cmd"; 890 bias-pull-up; 891 drive-strength = <10>; 892 }; 893 894 data-pins { 895 pins = "sdc2_data"; 896 bias-pull-up; 897 drive-strength = <10>; 898 }; 899 }; 900 901 sdc2_sleep: sdc2-sleep-state { 902 clk-pins { 903 pins = "sdc2_clk"; 904 bias-disable; 905 drive-strength = <2>; 906 }; 907 908 cmd-pins { 909 pins = "sdc2_cmd"; 910 bias-pull-up; 911 drive-strength = <2>; 912 }; 913 914 data-pins { 915 pins = "sdc2_data"; 916 bias-pull-up; 917 drive-strength = <2>; 918 }; 919 }; 920 921 wcnss_pin_a: wcnss-active-state { 922 wcss-wlan-pins { 923 pins = "gpio79", "gpio80"; 924 function = "wcss_wlan"; 925 drive-strength = <6>; 926 bias-pull-up; 927 928 }; 929 930 wcss-wlan0-pins { 931 pins = "gpio78"; 932 function = "wcss_wlan0"; 933 drive-strength = <6>; 934 bias-pull-up; 935 936 }; 937 938 wcss-wlan1-pins { 939 pins = "gpio77"; 940 function = "wcss_wlan1"; 941 drive-strength = <6>; 942 bias-pull-up; 943 944 }; 945 946 wcss-wlan2-pins { 947 pins = "gpio76"; 948 function = "wcss_wlan2"; 949 drive-strength = <6>; 950 bias-pull-up; 951 952 }; 953 }; 954 }; 955 956 gcc: clock-controller@1800000 { 957 compatible = "qcom,gcc-msm8917"; 958 reg = <0x01800000 0x80000>; 959 #clock-cells = <1>; 960 #reset-cells = <1>; 961 #power-domain-cells = <1>; 962 clocks = <&xo_board>, 963 <&sleep_clk>, 964 <&mdss_dsi0_phy 1>, 965 <&mdss_dsi0_phy 0>; 966 clock-names = "xo", 967 "sleep_clk", 968 "dsi0pll", 969 "dsi0pllbyte"; 970 }; 971 972 tcsr_mutex: hwlock@1905000 { 973 compatible = "qcom,tcsr-mutex"; 974 reg = <0x01905000 0x20000>; 975 #hwlock-cells = <1>; 976 }; 977 978 tcsr: syscon@1937000 { 979 compatible = "qcom,tcsr-msm8917", "syscon"; 980 reg = <0x01937000 0x30000>; 981 }; 982 983 mdss: display-subsystem@1a00000 { 984 compatible = "qcom,mdss"; 985 reg = <0x01a00000 0x1000>, 986 <0x01ab0000 0x1040>; 987 reg-names = "mdss_phys", "vbif_phys"; 988 ranges; 989 990 power-domains = <&gcc MDSS_GDSC>; 991 992 clocks = <&gcc GCC_MDSS_AHB_CLK>, 993 <&gcc GCC_MDSS_AXI_CLK>, 994 <&gcc GCC_MDSS_VSYNC_CLK>; 995 clock-names = "iface", 996 "bus", 997 "vsync"; 998 999 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1000 1001 interrupt-controller; 1002 #interrupt-cells = <1>; 1003 1004 #address-cells = <1>; 1005 #size-cells = <1>; 1006 1007 status = "disabled"; 1008 1009 mdp: display-controller@1a01000 { 1010 compatible = "qcom,msm8917-mdp5", "qcom,mdp5"; 1011 reg = <0x01a01000 0x89000>; 1012 reg-names = "mdp_phys"; 1013 1014 interrupt-parent = <&mdss>; 1015 interrupts = <0>; 1016 1017 power-domains = <&gcc MDSS_GDSC>; 1018 1019 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1020 <&gcc GCC_MDSS_AXI_CLK>, 1021 <&gcc GCC_MDSS_MDP_CLK>, 1022 <&gcc GCC_MDSS_VSYNC_CLK>; 1023 clock-names = "iface", 1024 "bus", 1025 "core", 1026 "vsync"; 1027 1028 iommus = <&apps_iommu 0x15>; 1029 1030 ports { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 1034 port@0 { 1035 reg = <0>; 1036 1037 mdp5_intf1_out: endpoint { 1038 remote-endpoint = <&mdss_dsi0_in>; 1039 }; 1040 }; 1041 }; 1042 }; 1043 1044 mdss_dsi0: dsi@1a94000 { 1045 compatible = "qcom,mdss-dsi-ctrl"; 1046 reg = <0x01a94000 0x300>; 1047 reg-names = "dsi_ctrl"; 1048 1049 interrupt-parent = <&mdss>; 1050 interrupts = <4>; 1051 1052 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1053 <&gcc PCLK0_CLK_SRC>; 1054 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1055 <&mdss_dsi0_phy 1>; 1056 1057 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1058 <&gcc GCC_MDSS_AHB_CLK>, 1059 <&gcc GCC_MDSS_AXI_CLK>, 1060 <&gcc GCC_MDSS_BYTE0_CLK>, 1061 <&gcc GCC_MDSS_PCLK0_CLK>, 1062 <&gcc GCC_MDSS_ESC0_CLK>; 1063 clock-names = "mdp_core", 1064 "iface", 1065 "bus", 1066 "byte", 1067 "pixel", 1068 "core"; 1069 phys = <&mdss_dsi0_phy>; 1070 1071 operating-points-v2 = <&mdss_dsi0_opp_table>; 1072 power-domains = <&rpmpd MSM8917_VDDCX>; 1073 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 1077 ports { 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 1081 port@0 { 1082 reg = <0>; 1083 1084 mdss_dsi0_in: endpoint { 1085 remote-endpoint = <&mdp5_intf1_out>; 1086 }; 1087 }; 1088 1089 port@1 { 1090 reg = <1>; 1091 1092 mdss_dsi0_out: endpoint { 1093 }; 1094 }; 1095 }; 1096 1097 mdss_dsi0_opp_table: opp-table { 1098 compatible = "operating-points-v2"; 1099 1100 opp-125000000 { 1101 opp-hz = /bits/ 64 <125000000>; 1102 required-opps = <&rpmpd_opp_svs>; 1103 }; 1104 1105 opp-187500000 { 1106 opp-hz = /bits/ 64 <187500000>; 1107 required-opps = <&rpmpd_opp_nom>; 1108 }; 1109 }; 1110 }; 1111 1112 mdss_dsi0_phy: phy@1a94a00 { 1113 compatible = "qcom,dsi-phy-28nm-8937"; 1114 reg = <0x01a94a00 0xd4>, 1115 <0x01a94400 0x280>, 1116 <0x01a94b80 0x30>; 1117 reg-names = "dsi_pll", 1118 "dsi_phy", 1119 "dsi_phy_regulator"; 1120 1121 #clock-cells = <1>; 1122 #phy-cells = <0>; 1123 1124 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1125 <&xo_board>; 1126 clock-names = "iface", "ref"; 1127 }; 1128 }; 1129 1130 apps_iommu: iommu@1e20000 { 1131 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; 1132 ranges = <0 0x01e20000 0x20000>; 1133 #address-cells = <1>; 1134 #size-cells = <1>; 1135 #iommu-cells = <1>; 1136 1137 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1138 <&gcc GCC_APSS_TCU_CLK>; 1139 clock-names = "iface", "bus"; 1140 1141 qcom,iommu-secure-id = <17>; 1142 1143 /* VFE */ 1144 iommu-ctx@14000 { 1145 compatible = "qcom,msm-iommu-v1-ns"; 1146 reg = <0x14000 0x1000>; 1147 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1148 }; 1149 1150 /* MDP_0 */ 1151 iommu-ctx@15000 { 1152 compatible = "qcom,msm-iommu-v1-ns"; 1153 reg = <0x15000 0x1000>; 1154 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1155 }; 1156 1157 /* VENUS_NS */ 1158 iommu-ctx@16000 { 1159 compatible = "qcom,msm-iommu-v1-ns"; 1160 reg = <0x16000 0x1000>; 1161 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1162 }; 1163 }; 1164 1165 gpu_iommu: iommu@1f08000 { 1166 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; 1167 ranges = <0 0x01f08000 0x10000>; 1168 1169 #address-cells = <1>; 1170 #size-cells = <1>; 1171 #iommu-cells = <1>; 1172 1173 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1174 <&gcc GCC_GFX_TCU_CLK>; 1175 clock-names = "iface", "bus"; 1176 qcom,iommu-secure-id = <18>; 1177 1178 iommu-ctx@0 { 1179 compatible = "qcom,msm-iommu-v2-ns"; 1180 reg = <0 0x1000>; 1181 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1182 }; 1183 }; 1184 1185 gpu: gpu@1c00000 { 1186 compatible = "qcom,adreno-306.32", "qcom,adreno"; 1187 reg = <0x01c00000 0x20000>; 1188 reg-names = "kgsl_3d0_reg_memory"; 1189 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1190 interrupt-names = "kgsl_3d0_irq"; 1191 clock-names = "core", 1192 "iface", 1193 "mem_iface", 1194 "alt_mem_iface", 1195 "gfx3d"; 1196 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1197 <&gcc GCC_OXILI_AHB_CLK>, 1198 <&gcc GCC_BIMC_GFX_CLK>, 1199 <&gcc GCC_BIMC_GPU_CLK>, 1200 <&gcc GFX3D_CLK_SRC>; 1201 power-domains = <&gcc OXILI_GX_GDSC>; 1202 operating-points-v2 = <&gpu_opp_table>; 1203 #cooling-cells = <2>; 1204 1205 iommus = <&gpu_iommu 0>; 1206 1207 status = "disabled"; 1208 1209 gpu_opp_table: opp-table { 1210 compatible = "operating-points-v2"; 1211 1212 opp-19200000 { 1213 opp-hz = /bits/ 64 <19200000>; 1214 }; 1215 1216 opp-270000000 { 1217 opp-hz = /bits/ 64 <270000000>; 1218 }; 1219 1220 opp-400000000 { 1221 opp-hz = /bits/ 64 <400000000>; 1222 }; 1223 1224 opp-484800000 { 1225 opp-hz = /bits/ 64 <484800000>; 1226 }; 1227 1228 opp-523200000 { 1229 opp-hz = /bits/ 64 <523200000>; 1230 }; 1231 1232 opp-598000000 { 1233 opp-hz = /bits/ 64 <598000000>; 1234 }; 1235 }; 1236 }; 1237 1238 spmi_bus: spmi@200f000 { 1239 compatible = "qcom,spmi-pmic-arb"; 1240 reg = <0x0200f000 0x001000>, 1241 <0x02400000 0x800000>, 1242 <0x02c00000 0x800000>, 1243 <0x03800000 0x200000>, 1244 <0x0200a000 0x002100>; 1245 reg-names = "core", 1246 "chnls", 1247 "obsrvr", 1248 "intr", 1249 "cnfg"; 1250 interrupt-names = "periph_irq"; 1251 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1252 qcom,ee = <0>; 1253 qcom,channel = <0>; 1254 #address-cells = <2>; 1255 #size-cells = <0>; 1256 interrupt-controller; 1257 #interrupt-cells = <4>; 1258 }; 1259 1260 bam_dmux_dma: dma-controller@4044000 { 1261 compatible = "qcom,bam-v1.7.0"; 1262 reg = <0x04044000 0x19000>; 1263 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1264 #dma-cells = <1>; 1265 qcom,ee = <0>; 1266 1267 num-channels = <6>; 1268 qcom,num-ees = <1>; 1269 qcom,powered-remotely; 1270 1271 status = "disabled"; 1272 }; 1273 1274 sdhc_1: mmc@7824900 { 1275 compatible = "qcom,sdhci-msm-v4"; 1276 reg = <0x07824900 0x500>, 1277 <0x07824000 0x800>; 1278 reg-names = "hc", "core"; 1279 1280 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1282 interrupt-names = "hc_irq", "pwr_irq"; 1283 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1284 <&gcc GCC_SDCC1_APPS_CLK>, 1285 <&xo_board>; 1286 clock-names = "iface", "core", "xo"; 1287 pinctrl-0 = <&sdc1_default>; 1288 pinctrl-1 = <&sdc1_sleep>; 1289 pinctrl-names = "default", "sleep"; 1290 power-domains = <&rpmpd MSM8917_VDDCX>; 1291 mmc-hs200-1_8v; 1292 mmc-hs400-1_8v; 1293 mmc-ddr-1_8v; 1294 bus-width = <8>; 1295 non-removable; 1296 status = "disabled"; 1297 }; 1298 1299 sdhc_2: mmc@7864900 { 1300 compatible = "qcom,sdhci-msm-v4"; 1301 reg = <0x07864900 0x500>, 1302 <0x07864000 0x800>; 1303 reg-names = "hc", "core"; 1304 1305 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1307 interrupt-names = "hc_irq", "pwr_irq"; 1308 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1309 <&gcc GCC_SDCC2_APPS_CLK>, 1310 <&xo_board>; 1311 clock-names = "iface", "core", "xo"; 1312 pinctrl-0 = <&sdc2_default>; 1313 pinctrl-1 = <&sdc2_sleep>; 1314 pinctrl-names = "default", "sleep"; 1315 power-domains = <&rpmpd MSM8917_VDDCX>; 1316 bus-width = <4>; 1317 status = "disabled"; 1318 }; 1319 1320 blsp1_dma: dma-controller@7884000 { 1321 compatible = "qcom,bam-v1.7.0"; 1322 reg = <0x07884000 0x1f000>; 1323 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1324 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1325 clock-names = "bam_clk"; 1326 qcom,controlled-remotely; 1327 #dma-cells = <1>; 1328 num-channels = <12>; 1329 qcom,num-ees = <4>; 1330 qcom,ee = <0>; 1331 }; 1332 1333 blsp2_dma: dma-controller@7ac4000 { 1334 compatible = "qcom,bam-v1.7.0"; 1335 reg = <0x07ac4000 0x1d000>; 1336 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1338 clock-names = "bam_clk"; 1339 qcom,controlled-remotely; 1340 #dma-cells = <1>; 1341 num-channels = <10>; 1342 qcom,num-ees = <4>; 1343 qcom,ee = <0>; 1344 }; 1345 1346 blsp1_uart1: serial@78af000 { 1347 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1348 reg = <0x078af000 0x200>; 1349 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1351 <&gcc GCC_BLSP1_AHB_CLK>; 1352 clock-names = "core", "iface"; 1353 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1354 dma-names = "tx", "rx"; 1355 pinctrl-0 = <&blsp1_uart1_default>; 1356 pinctrl-1 = <&blsp1_uart1_sleep>; 1357 pinctrl-names = "default", "sleep"; 1358 status = "disabled"; 1359 }; 1360 1361 blsp1_uart2: serial@78b0000 { 1362 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1363 reg = <0x078b0000 0x200>; 1364 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1366 <&gcc GCC_BLSP1_AHB_CLK>; 1367 clock-names = "core", "iface"; 1368 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1369 dma-names = "tx", "rx"; 1370 pinctrl-0 = <&blsp1_uart2_default>; 1371 pinctrl-1 = <&blsp1_uart2_sleep>; 1372 pinctrl-names = "default", "sleep"; 1373 status = "disabled"; 1374 }; 1375 1376 blsp1_i2c2: i2c@78b6000 { 1377 compatible = "qcom,i2c-qup-v2.2.1"; 1378 reg = <0x078b6000 0x600>; 1379 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1381 <&gcc GCC_BLSP1_AHB_CLK>; 1382 clock-names = "core", "iface"; 1383 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1384 dma-names = "tx", "rx"; 1385 pinctrl-0 = <&blsp1_i2c2_default>; 1386 pinctrl-1 = <&blsp1_i2c2_sleep>; 1387 pinctrl-names = "default", "sleep"; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 status = "disabled"; 1391 }; 1392 1393 blsp1_i2c3: i2c@78b7000 { 1394 compatible = "qcom,i2c-qup-v2.2.1"; 1395 reg = <0x078b7000 0x600>; 1396 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1398 <&gcc GCC_BLSP1_AHB_CLK>; 1399 clock-names = "core", "iface"; 1400 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1401 dma-names = "tx", "rx"; 1402 pinctrl-0 = <&blsp1_i2c3_default>; 1403 pinctrl-1 = <&blsp1_i2c3_sleep>; 1404 pinctrl-names = "default", "sleep"; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 status = "disabled"; 1408 }; 1409 1410 blsp1_spi3: spi@78b7000 { 1411 compatible = "qcom,spi-qup-v2.2.1"; 1412 reg = <0x078b7000 0x600>; 1413 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1414 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1415 <&gcc GCC_BLSP1_AHB_CLK>; 1416 clock-names = "core", "iface"; 1417 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1418 dma-names = "tx", "rx"; 1419 pinctrl-0 = <&blsp1_spi3_default>; 1420 pinctrl-1 = <&blsp1_spi3_sleep>; 1421 pinctrl-names = "default", "sleep"; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 blsp1_i2c4: i2c@78b8000 { 1428 compatible = "qcom,i2c-qup-v2.2.1"; 1429 reg = <0x078b8000 0x500>; 1430 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1431 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1432 <&gcc GCC_BLSP1_AHB_CLK>; 1433 clock-names = "core", "iface"; 1434 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1435 dma-names = "tx", "rx"; 1436 pinctrl-0 = <&blsp1_i2c4_default>; 1437 pinctrl-1 = <&blsp1_i2c4_sleep>; 1438 pinctrl-names = "default", "sleep"; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 status = "disabled"; 1442 }; 1443 1444 blsp2_i2c1: i2c@7af5000 { 1445 compatible = "qcom,i2c-qup-v2.2.1"; 1446 reg = <0x07af5000 0x600>; 1447 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1448 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1449 <&gcc GCC_BLSP2_AHB_CLK>; 1450 clock-names = "core", "iface"; 1451 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1452 dma-names = "tx", "rx"; 1453 pinctrl-0 = <&blsp2_i2c1_default>; 1454 pinctrl-1 = <&blsp2_i2c1_sleep>; 1455 pinctrl-names = "default", "sleep"; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 status = "disabled"; 1459 }; 1460 1461 blsp2_spi2: spi@7af6000 { 1462 compatible = "qcom,spi-qup-v2.2.1"; 1463 reg = <0x07af6000 0x600>; 1464 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1465 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 1466 <&gcc GCC_BLSP2_AHB_CLK>; 1467 clock-names = "core", "iface"; 1468 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1469 dma-names = "tx", "rx"; 1470 pinctrl-0 = <&blsp2_spi2_default>; 1471 pinctrl-1 = <&blsp2_spi2_sleep>; 1472 pinctrl-names = "default", "sleep"; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 usb: usb@78db000 { 1479 compatible = "qcom,ci-hdrc"; 1480 reg = <0x078db000 0x200>, 1481 <0x078db200 0x200>; 1482 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1484 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1485 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1486 clock-names = "iface", "core"; 1487 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1488 assigned-clock-rates = <80000000>; 1489 resets = <&gcc GCC_USB_HS_BCR>; 1490 reset-names = "core"; 1491 phy_type = "ulpi"; 1492 dr_mode = "otg"; 1493 hnp-disable; 1494 srp-disable; 1495 adp-disable; 1496 ahb-burst-config = <0>; 1497 phy-names = "usb-phy"; 1498 phys = <&usb_hs_phy>; 1499 status = "disabled"; 1500 #reset-cells = <1>; 1501 }; 1502 1503 wcnss: remoteproc@a204000 { 1504 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1505 reg = <0x0a204000 0x2000>, 1506 <0x0a202000 0x1000>, 1507 <0x0a21b000 0x3000>; 1508 reg-names = "ccu", "dxe", "pmu"; 1509 1510 memory-region = <&wcnss_mem>; 1511 1512 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1513 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1514 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1515 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1516 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1517 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1518 1519 power-domains = <&rpmpd MSM8917_VDDCX>, 1520 <&rpmpd MSM8917_VDDMX>; 1521 power-domain-names = "cx", "mx"; 1522 1523 qcom,smem-states = <&wcnss_smp2p_out 0>; 1524 qcom,smem-state-names = "stop"; 1525 1526 pinctrl-0 = <&wcnss_pin_a>; 1527 pinctrl-names = "default"; 1528 1529 status = "disabled"; 1530 1531 wcnss_iris: iris { 1532 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1533 clock-names = "xo"; 1534 }; 1535 1536 smd-edge { 1537 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1538 1539 mboxes = <&apcs 17>; 1540 qcom,smd-edge = <6>; 1541 qcom,remote-pid = <4>; 1542 1543 label = "pronto"; 1544 1545 wcnss_ctrl: wcnss { 1546 compatible = "qcom,wcnss"; 1547 qcom,smd-channels = "WCNSS_CTRL"; 1548 1549 qcom,mmio = <&wcnss>; 1550 1551 wcnss_bt: bluetooth { 1552 compatible = "qcom,wcnss-bt"; 1553 }; 1554 1555 wcnss_wifi: wifi { 1556 compatible = "qcom,wcnss-wlan"; 1557 1558 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupt-names = "tx", "rx"; 1561 1562 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1563 qcom,smem-state-names = "tx-enable", 1564 "tx-rings-empty"; 1565 }; 1566 }; 1567 }; 1568 }; 1569 1570 intc: interrupt-controller@b000000 { 1571 compatible = "qcom,msm-qgic2"; 1572 reg = <0x0b000000 0x1000>, 1573 <0x0b002000 0x1000>; 1574 interrupt-controller; 1575 #interrupt-cells = <3>; 1576 }; 1577 1578 apcs: mailbox@b011000 { 1579 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 1580 reg = <0x0b011000 0x1000>; 1581 #mbox-cells = <1>; 1582 clocks = <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1583 clock-names = "pll", "aux", "ref"; 1584 #clock-cells = <0>; 1585 }; 1586 1587 a53pll: clock@b016000 { 1588 compatible = "qcom,msm8939-a53pll"; 1589 reg = <0x0b016000 0x40>; 1590 clocks = <&xo_board>; 1591 clock-names = "xo"; 1592 #clock-cells = <0>; 1593 operating-points-v2 = <&pll_opp_table>; 1594 1595 pll_opp_table: opp-table { 1596 compatible = "operating-points-v2"; 1597 1598 opp-960000000 { 1599 opp-hz = /bits/ 64 <960000000>; 1600 }; 1601 1602 opp-1094400000 { 1603 opp-hz = /bits/ 64 <1094400000>; 1604 }; 1605 1606 opp-1248000000 { 1607 opp-hz = /bits/ 64 <1248000000>; 1608 }; 1609 1610 opp-1401600000 { 1611 opp-hz = /bits/ 64 <1401600000>; 1612 }; 1613 }; 1614 }; 1615 1616 watchdog@b017000 { 1617 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1618 reg = <0x0b017000 0x1000>; 1619 clocks = <&sleep_clk>; 1620 }; 1621 1622 timer@b120000 { 1623 compatible = "arm,armv7-timer-mem"; 1624 reg = <0x0b120000 0x1000>; 1625 ranges; 1626 #address-cells = <1>; 1627 #size-cells = <1>; 1628 1629 frame@b121000 { 1630 reg = <0x0b121000 0x1000>, 1631 <0x0b122000 0x1000>; 1632 frame-number = <0>; 1633 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1635 }; 1636 1637 frame@b123000 { 1638 reg = <0x0b123000 0x1000>; 1639 frame-number = <1>; 1640 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1641 status = "disabled"; 1642 }; 1643 1644 frame@b124000 { 1645 reg = <0x0b124000 0x1000>; 1646 frame-number = <2>; 1647 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1648 status = "disabled"; 1649 }; 1650 1651 frame@b125000 { 1652 reg = <0x0b125000 0x1000>; 1653 frame-number = <3>; 1654 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1655 status = "disabled"; 1656 }; 1657 1658 frame@b126000 { 1659 reg = <0x0b126000 0x1000>; 1660 frame-number = <4>; 1661 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1662 status = "disabled"; 1663 }; 1664 1665 frame@b127000 { 1666 reg = <0x0b127000 0x1000>; 1667 frame-number = <5>; 1668 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1669 status = "disabled"; 1670 }; 1671 1672 frame@b128000 { 1673 reg = <0x0b128000 0x1000>; 1674 frame-number = <6>; 1675 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1676 status = "disabled"; 1677 }; 1678 }; 1679 }; 1680 1681 timer { 1682 compatible = "arm,armv8-timer"; 1683 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1684 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1685 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1686 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1687 }; 1688 1689 thermal_zones: thermal-zones { 1690 aoss-thermal { 1691 polling-delay-passive = <250>; 1692 1693 thermal-sensors = <&tsens 0>; 1694 1695 trips { 1696 aoss_alert0: trip-point0 { 1697 temperature = <85000>; 1698 hysteresis = <2000>; 1699 type = "hot"; 1700 }; 1701 }; 1702 }; 1703 1704 camera-thermal { 1705 polling-delay-passive = <250>; 1706 1707 thermal-sensors = <&tsens 3>; 1708 1709 trips { 1710 camera_alert0: trip-point0 { 1711 temperature = <85000>; 1712 hysteresis = <2000>; 1713 type = "hot"; 1714 }; 1715 }; 1716 }; 1717 1718 cpuss1-thermal { 1719 polling-delay-passive = <250>; 1720 1721 thermal-sensors = <&tsens 4>; 1722 1723 cooling-maps { 1724 map0 { 1725 trip = <&cpuss1_alert0>; 1726 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1727 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1728 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1729 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1730 }; 1731 }; 1732 1733 trips { 1734 cpuss1_alert0: trip-point0 { 1735 temperature = <75000>; 1736 hysteresis = <2000>; 1737 type = "passive"; 1738 }; 1739 1740 cpuss1_alert1: trip-point1 { 1741 temperature = <85000>; 1742 hysteresis = <2000>; 1743 type = "hot"; 1744 }; 1745 1746 cpuss1_crit: cpuss1-crit { 1747 temperature = <100000>; 1748 hysteresis = <2000>; 1749 type = "critical"; 1750 }; 1751 }; 1752 }; 1753 1754 cpu0-thermal { 1755 polling-delay-passive = <250>; 1756 1757 thermal-sensors = <&tsens 5>; 1758 1759 cooling-maps { 1760 map0 { 1761 trip = <&cpu0_alert1>; 1762 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1763 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1764 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1765 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1766 }; 1767 }; 1768 1769 trips { 1770 cpu0_alert0: trip-point0 { 1771 temperature = <75000>; 1772 hysteresis = <2000>; 1773 type = "passive"; 1774 }; 1775 1776 cpu0_alert1: trip-point1 { 1777 temperature = <85000>; 1778 hysteresis = <2000>; 1779 type = "hot"; 1780 }; 1781 1782 cpu0_crit: cpu-crit { 1783 temperature = <100000>; 1784 hysteresis = <2000>; 1785 type = "critical"; 1786 }; 1787 }; 1788 }; 1789 1790 cpu1-thermal { 1791 polling-delay-passive = <250>; 1792 1793 thermal-sensors = <&tsens 6>; 1794 1795 cooling-maps { 1796 map0 { 1797 trip = <&cpu1_alert1>; 1798 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1799 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1800 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1801 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1802 }; 1803 }; 1804 1805 trips { 1806 cpu1_alert0: trip-point0 { 1807 temperature = <75000>; 1808 hysteresis = <2000>; 1809 type = "hot"; 1810 }; 1811 1812 cpu1_alert1: trip-point1 { 1813 temperature = <85000>; 1814 hysteresis = <2000>; 1815 type = "passive"; 1816 }; 1817 1818 cpu1_crit: cpu-crit { 1819 temperature = <100000>; 1820 hysteresis = <2000>; 1821 type = "critical"; 1822 }; 1823 }; 1824 }; 1825 1826 cpu2-thermal { 1827 polling-delay-passive = <250>; 1828 1829 thermal-sensors = <&tsens 7>; 1830 1831 cooling-maps { 1832 map0 { 1833 trip = <&cpu2_alert1>; 1834 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1835 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1836 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1837 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1838 }; 1839 }; 1840 1841 trips { 1842 cpu2_alert0: trip-point0 { 1843 temperature = <75000>; 1844 hysteresis = <2000>; 1845 type = "hot"; 1846 }; 1847 1848 cpu2_alert1: trip-point1 { 1849 temperature = <85000>; 1850 hysteresis = <2000>; 1851 type = "passive"; 1852 }; 1853 1854 cpu2_crit: cpu-crit { 1855 temperature = <100000>; 1856 hysteresis = <2000>; 1857 type = "critical"; 1858 }; 1859 }; 1860 }; 1861 1862 cpu3-thermal { 1863 polling-delay-passive = <250>; 1864 1865 thermal-sensors = <&tsens 8>; 1866 1867 cooling-maps { 1868 map0 { 1869 trip = <&cpu3_alert1>; 1870 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1871 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1872 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1873 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1874 }; 1875 }; 1876 1877 trips { 1878 cpu3_alert0: trip-point0 { 1879 temperature = <75000>; 1880 hysteresis = <2000>; 1881 type = "hot"; 1882 }; 1883 1884 cpu3_alert1: trip-point1 { 1885 temperature = <85000>; 1886 hysteresis = <2000>; 1887 type = "passive"; 1888 }; 1889 1890 cpu3_crit: cpu-crit { 1891 temperature = <100000>; 1892 hysteresis = <2000>; 1893 type = "critical"; 1894 }; 1895 }; 1896 }; 1897 1898 gpu-thermal { 1899 polling-delay-passive = <250>; 1900 1901 thermal-sensors = <&tsens 9>; 1902 1903 cooling-maps { 1904 map0 { 1905 trip = <&gpu_alert>; 1906 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1907 }; 1908 }; 1909 1910 trips { 1911 gpu_alert: trip-point0 { 1912 temperature = <70000>; 1913 hysteresis = <2000>; 1914 type = "passive"; 1915 }; 1916 1917 gpu_crit: gpu-crit { 1918 temperature = <90000>; 1919 hysteresis = <2000>; 1920 type = "critical"; 1921 }; 1922 }; 1923 1924 }; 1925 1926 mdm-core-thermal { 1927 polling-delay-passive = <250>; 1928 1929 thermal-sensors = <&tsens 1>; 1930 1931 trips { 1932 mdm_core_alert0: trip-point0 { 1933 temperature = <85000>; 1934 hysteresis = <2000>; 1935 type = "hot"; 1936 }; 1937 }; 1938 }; 1939 1940 q6-thermal { 1941 polling-delay-passive = <250>; 1942 1943 thermal-sensors = <&tsens 2>; 1944 1945 trips { 1946 q6_alert0: trip-point0 { 1947 temperature = <85000>; 1948 hysteresis = <2000>; 1949 type = "hot"; 1950 }; 1951 }; 1952 }; 1953 }; 1954}; 1955