1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * IPQ5424 device tree source
4 *
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
11#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	#address-cells = <2>;
16	#size-cells = <2>;
17	interrupt-parent = <&intc>;
18
19	clocks {
20		sleep_clk: sleep-clk {
21			compatible = "fixed-clock";
22			#clock-cells = <0>;
23		};
24
25		xo_board: xo-board-clk {
26			compatible = "fixed-clock";
27			#clock-cells = <0>;
28		};
29	};
30
31	cpus: cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu0: cpu@0 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a55";
38			reg = <0x0>;
39			enable-method = "psci";
40			next-level-cache = <&l2_0>;
41			l2_0: l2-cache {
42				compatible = "cache";
43				cache-level = <2>;
44				cache-unified;
45				next-level-cache = <&l3_0>;
46
47				l3_0: l3-cache {
48					compatible = "cache";
49					cache-level = <3>;
50					cache-unified;
51				};
52			};
53		};
54
55		cpu1: cpu@100 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a55";
58			enable-method = "psci";
59			reg = <0x100>;
60			next-level-cache = <&l2_100>;
61
62			l2_100: l2-cache {
63				compatible = "cache";
64				cache-level = <2>;
65				cache-unified;
66				next-level-cache = <&l3_0>;
67			};
68		};
69
70		cpu2: cpu@200 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a55";
73			enable-method = "psci";
74			reg = <0x200>;
75			next-level-cache = <&l2_200>;
76
77			l2_200: l2-cache {
78				compatible = "cache";
79				cache-level = <2>;
80				cache-unified;
81				next-level-cache = <&l3_0>;
82			};
83		};
84
85		cpu3: cpu@300 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a55";
88			enable-method = "psci";
89			reg = <0x300>;
90			next-level-cache = <&l2_300>;
91
92			l2_300: l2-cache {
93				compatible = "cache";
94				cache-level = <2>;
95				cache-unified;
96				next-level-cache = <&l3_0>;
97			};
98		};
99	};
100
101	firmware {
102		scm {
103			compatible = "qcom,scm-ipq5424", "qcom,scm";
104			qcom,dload-mode = <&tcsr 0x25100>;
105		};
106	};
107
108	memory@80000000 {
109		device_type = "memory";
110		/* We expect the bootloader to fill in the size */
111		reg = <0x0 0x80000000 0x0 0x0>;
112	};
113
114	pmu-a55 {
115		compatible = "arm,cortex-a55-pmu";
116		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
117	};
118
119	pmu-dsu {
120		compatible = "arm,dsu-pmu";
121		interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
122		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
123	};
124
125	psci {
126		compatible = "arm,psci-1.0";
127		method = "smc";
128	};
129
130	reserved-memory {
131		#address-cells = <2>;
132		#size-cells = <2>;
133		ranges;
134
135		tz@8a600000 {
136			reg = <0x0 0x8a600000 0x0 0x200000>;
137			no-map;
138		};
139
140		smem@8a800000 {
141			compatible = "qcom,smem";
142			reg = <0x0 0x8a800000 0x0 0x32000>;
143			no-map;
144
145			hwlocks = <&tcsr_mutex 3>;
146		};
147	};
148
149	soc@0 {
150		compatible = "simple-bus";
151		#address-cells = <2>;
152		#size-cells = <2>;
153		ranges = <0 0 0 0 0x10 0>;
154
155		rng: rng@4c3000 {
156			compatible = "qcom,ipq5424-trng", "qcom,trng";
157			reg = <0 0x004c3000 0 0x1000>;
158			clocks = <&gcc GCC_PRNG_AHB_CLK>;
159			clock-names = "core";
160		};
161
162		system-cache-controller@800000 {
163			compatible = "qcom,ipq5424-llcc";
164			reg = <0 0x00800000 0 0x200000>;
165			reg-names = "llcc0_base";
166			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
167		};
168
169		tlmm: pinctrl@1000000 {
170			compatible = "qcom,ipq5424-tlmm";
171			reg = <0 0x01000000 0 0x300000>;
172			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
173			gpio-controller;
174			#gpio-cells = <2>;
175			gpio-ranges = <&tlmm 0 0 50>;
176			interrupt-controller;
177			#interrupt-cells = <2>;
178
179			uart1_pins: uart1-state {
180				pins = "gpio43", "gpio44";
181				function = "uart1";
182				drive-strength = <8>;
183				bias-pull-up;
184			};
185		};
186
187		gcc: clock-controller@1800000 {
188			compatible = "qcom,ipq5424-gcc";
189			reg = <0 0x01800000 0 0x40000>;
190			clocks = <&xo_board>,
191				 <&sleep_clk>,
192				 <0>,
193				 <0>,
194				 <0>,
195				 <0>,
196				 <0>;
197			#clock-cells = <1>;
198			#reset-cells = <1>;
199			#interconnect-cells = <1>;
200		};
201
202		tcsr_mutex: hwlock@1905000 {
203			compatible = "qcom,tcsr-mutex";
204			reg = <0 0x01905000 0 0x20000>;
205			#hwlock-cells = <1>;
206		};
207
208		tcsr: syscon@1937000 {
209			compatible = "qcom,tcsr-ipq5424", "syscon";
210			reg = <0 0x01937000 0 0x2a000>;
211		};
212
213		qupv3: geniqup@1ac0000 {
214			compatible = "qcom,geni-se-qup";
215			reg = <0 0x01ac0000 0 0x2000>;
216			ranges;
217			clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
218				 <&gcc GCC_QUPV3_AHB_SLV_CLK>;
219			clock-names = "m-ahb", "s-ahb";
220			#address-cells = <2>;
221			#size-cells = <2>;
222
223			uart1: serial@1a84000 {
224				compatible = "qcom,geni-debug-uart";
225				reg = <0 0x01a84000 0 0x4000>;
226				clocks = <&gcc GCC_QUPV3_UART1_CLK>;
227				clock-names = "se";
228				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
229			};
230
231			spi0: spi@1a90000 {
232				compatible = "qcom,geni-spi";
233				reg = <0 0x01a90000 0 0x4000>;
234				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
235				clock-names = "se";
236				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
237				#address-cells = <1>;
238				#size-cells = <0>;
239				status = "disabled";
240			};
241
242			spi1: spi@1a94000 {
243				compatible = "qcom,geni-spi";
244				reg = <0 0x01a94000 0 0x4000>;
245				clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
246				clock-names = "se";
247				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
248				#address-cells = <1>;
249				#size-cells = <0>;
250				status = "disabled";
251			};
252		};
253
254		sdhc: mmc@7804000 {
255			compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
256			reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
257			reg-names = "hc", "cqhci";
258
259			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
260				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
261			interrupt-names = "hc_irq", "pwr_irq";
262
263			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
264				 <&gcc GCC_SDCC1_APPS_CLK>,
265				 <&xo_board>;
266			clock-names = "iface", "core", "xo";
267
268			status = "disabled";
269		};
270
271		intc: interrupt-controller@f200000 {
272			compatible = "arm,gic-v3";
273			reg = <0 0xf200000 0 0x10000>, /* GICD */
274			      <0 0xf240000 0 0x80000>; /* GICR * 4 regions */
275			#interrupt-cells = <0x3>;
276			interrupt-controller;
277			#redistributor-regions = <1>;
278			redistributor-stride = <0x0 0x20000>;
279			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
280			mbi-ranges = <672 128>;
281			msi-controller;
282		};
283
284		watchdog@f410000 {
285			compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
286			reg = <0 0x0f410000 0 0x1000>;
287			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
288			clocks = <&sleep_clk>;
289		};
290
291		qusb_phy_1: phy@71000 {
292			compatible = "qcom,ipq5424-qusb2-phy";
293			reg = <0 0x00071000 0 0x180>;
294			#phy-cells = <0>;
295
296			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
297				<&xo_board>;
298			clock-names = "cfg_ahb", "ref";
299
300			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
301			status = "disabled";
302		};
303
304		usb2: usb2@1e00000 {
305			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
306			reg = <0 0x01ef8800 0 0x400>;
307			#address-cells = <2>;
308			#size-cells = <2>;
309			ranges;
310
311			clocks = <&gcc GCC_USB1_MASTER_CLK>,
312				 <&gcc GCC_USB1_SLEEP_CLK>,
313				 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
314				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
315				 <&gcc GCC_CNOC_USB_CLK>;
316
317			clock-names = "core",
318				      "sleep",
319				      "mock_utmi",
320				      "iface",
321				      "cfg_noc";
322
323			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
324					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
325			assigned-clock-rates = <200000000>,
326					       <24000000>;
327
328			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
329					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
330					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
331					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
332			interrupt-names = "pwr_event",
333					  "qusb2_phy",
334					  "dm_hs_phy_irq",
335					  "dp_hs_phy_irq";
336
337			resets = <&gcc GCC_USB1_BCR>;
338			qcom,select-utmi-as-pipe-clk;
339			status = "disabled";
340
341			dwc_1: usb@1e00000 {
342				compatible = "snps,dwc3";
343				reg = <0 0x01e00000 0 0xe000>;
344				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
345				clock-names = "ref";
346				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
347				phys = <&qusb_phy_1>;
348				phy-names = "usb2-phy";
349				tx-fifo-resize;
350				snps,is-utmi-l1-suspend;
351				snps,hird-threshold = /bits/ 8 <0x0>;
352				snps,dis_u2_susphy_quirk;
353				snps,dis_u3_susphy_quirk;
354			};
355		};
356
357		qusb_phy_0: phy@7b000 {
358			compatible = "qcom,ipq5424-qusb2-phy";
359			reg = <0 0x0007b000 0 0x180>;
360			#phy-cells = <0>;
361
362			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
363				<&xo_board>;
364			clock-names = "cfg_ahb", "ref";
365
366			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
367			status = "disabled";
368		};
369
370		ssphy_0: phy@7d000 {
371			compatible = "qcom,ipq5424-qmp-usb3-phy";
372			reg = <0 0x0007d000 0 0xa00>;
373			#phy-cells = <0>;
374
375			clocks = <&gcc GCC_USB0_AUX_CLK>,
376				 <&xo_board>,
377				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
378				 <&gcc GCC_USB0_PIPE_CLK>;
379			clock-names = "aux",
380				      "ref",
381				      "cfg_ahb",
382				      "pipe";
383
384			resets = <&gcc GCC_USB0_PHY_BCR>,
385				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
386			reset-names = "phy",
387				      "phy_phy";
388
389			#clock-cells = <0>;
390			clock-output-names = "usb0_pipe_clk";
391
392			status = "disabled";
393		};
394
395		usb3: usb3@8a00000 {
396			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
397			reg = <0 0x08af8800 0 0x400>;
398
399			#address-cells = <2>;
400			#size-cells = <2>;
401			ranges;
402
403			clocks = <&gcc GCC_USB0_MASTER_CLK>,
404				 <&gcc GCC_USB0_SLEEP_CLK>,
405				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
406				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
407				 <&gcc GCC_CNOC_USB_CLK>;
408
409			clock-names = "core",
410				      "sleep",
411				      "mock_utmi",
412				      "iface",
413				      "cfg_noc";
414
415			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
416					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
417			assigned-clock-rates = <200000000>,
418					       <24000000>;
419
420			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
421					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
422					      <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
423					      <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
424			interrupt-names = "pwr_event",
425					  "qusb2_phy",
426					  "dm_hs_phy_irq",
427					  "dp_hs_phy_irq";
428
429			resets = <&gcc GCC_USB_BCR>;
430			status = "disabled";
431
432			dwc_0: usb@8a00000 {
433				compatible = "snps,dwc3";
434				reg = <0 0x08a00000 0 0xcd00>;
435				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
436				clock-names = "ref";
437				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
438				phys = <&qusb_phy_0>, <&ssphy_0>;
439				phy-names = "usb2-phy", "usb3-phy";
440				tx-fifo-resize;
441				snps,is-utmi-l1-suspend;
442				snps,hird-threshold = /bits/ 8 <0x0>;
443				snps,dis_u2_susphy_quirk;
444				snps,dis_u3_susphy_quirk;
445				snps,dis-u1-entry-quirk;
446				snps,dis-u2-entry-quirk;
447			};
448		};
449
450		timer@f420000 {
451			compatible = "arm,armv7-timer-mem";
452			reg = <0 0xf420000 0 0x1000>;
453			ranges = <0 0 0 0x10000000>;
454			#address-cells = <1>;
455			#size-cells = <1>;
456
457			frame@f421000 {
458				reg = <0xf421000 0x1000>,
459				      <0xf422000 0x1000>;
460				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
461					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
462				frame-number = <0>;
463			};
464
465			frame@f423000 {
466				reg = <0xf423000 0x1000>;
467				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
468				frame-number = <1>;
469				status = "disabled";
470			};
471
472			frame@f425000 {
473				reg = <0xf425000 0x1000>,
474				      <0xf426000 0x1000>;
475				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
476				frame-number = <2>;
477				status = "disabled";
478			};
479
480			frame@f427000 {
481				reg = <0xf427000 0x1000>;
482				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
483				frame-number = <3>;
484				status = "disabled";
485			};
486
487			frame@f429000 {
488				reg = <0xf429000 0x1000>;
489				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
490				frame-number = <4>;
491				status = "disabled";
492			};
493
494			frame@f42b000 {
495				reg = <0xf42b000 0x1000>;
496				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
497				frame-number = <5>;
498				status = "disabled";
499			};
500
501			frame@f42d000 {
502				reg = <0xf42d000 0x1000>;
503				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
504				frame-number = <6>;
505				status = "disabled";
506			};
507		};
508
509	};
510
511	timer {
512		compatible = "arm,armv8-timer";
513		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
514			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
515			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
516			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
517			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
518	};
519};
520