1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Copyright (c) 2019 BayLibre, SAS. 5 * Author: Fabien Parent <[email protected]> 6 */ 7 8#include <dt-bindings/clock/mt8516-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12 13#include "mt8516-pinfunc.h" 14 15/ { 16 compatible = "mediatek,mt8516"; 17 interrupt-parent = <&sysirq>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cluster0_opp: opp-table-0 { 22 compatible = "operating-points-v2"; 23 opp-shared; 24 opp-598000000 { 25 opp-hz = /bits/ 64 <598000000>; 26 opp-microvolt = <1150000>; 27 }; 28 opp-747500000 { 29 opp-hz = /bits/ 64 <747500000>; 30 opp-microvolt = <1150000>; 31 }; 32 opp-1040000000 { 33 opp-hz = /bits/ 64 <1040000000>; 34 opp-microvolt = <1200000>; 35 }; 36 opp-1196000000 { 37 opp-hz = /bits/ 64 <1196000000>; 38 opp-microvolt = <1250000>; 39 }; 40 opp-1300000000 { 41 opp-hz = /bits/ 64 <1300000000>; 42 opp-microvolt = <1300000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a35"; 53 reg = <0x0>; 54 enable-method = "psci"; 55 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 56 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 58 <&topckgen CLK_TOP_MAINPLL_D2>; 59 clock-names = "cpu", "intermediate"; 60 operating-points-v2 = <&cluster0_opp>; 61 }; 62 63 cpu1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a35"; 66 reg = <0x1>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 69 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 70 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 71 <&topckgen CLK_TOP_MAINPLL_D2>; 72 clock-names = "cpu", "intermediate"; 73 operating-points-v2 = <&cluster0_opp>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a35"; 79 reg = <0x2>; 80 enable-method = "psci"; 81 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 82 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 83 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 84 <&topckgen CLK_TOP_MAINPLL_D2>; 85 clock-names = "cpu", "intermediate"; 86 operating-points-v2 = <&cluster0_opp>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a35"; 92 reg = <0x3>; 93 enable-method = "psci"; 94 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 95 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 96 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 97 <&topckgen CLK_TOP_MAINPLL_D2>; 98 clock-names = "cpu", "intermediate", "armpll"; 99 operating-points-v2 = <&cluster0_opp>; 100 }; 101 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0_0: cpu-sleep-0-0 { 106 compatible = "arm,idle-state"; 107 entry-latency-us = <600>; 108 exit-latency-us = <600>; 109 min-residency-us = <1200>; 110 arm,psci-suspend-param = <0x0010000>; 111 }; 112 113 CLUSTER_SLEEP_0: cluster-sleep-0 { 114 compatible = "arm,idle-state"; 115 entry-latency-us = <800>; 116 exit-latency-us = <1000>; 117 min-residency-us = <2000>; 118 arm,psci-suspend-param = <0x2010000>; 119 }; 120 }; 121 }; 122 123 psci { 124 compatible = "arm,psci-1.0"; 125 method = "smc"; 126 }; 127 128 clk26m: clk26m { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <26000000>; 132 clock-output-names = "clk26m"; 133 }; 134 135 clk32k: clk32k { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <32000>; 139 clock-output-names = "clk32k"; 140 }; 141 142 reserved-memory { 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges; 146 147 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 148 bl31_secmon_reserved: secmon@43000000 { 149 no-map; 150 reg = <0 0x43000000 0 0x30000>; 151 }; 152 }; 153 154 timer { 155 compatible = "arm,armv8-timer"; 156 interrupt-parent = <&gic>; 157 interrupts = <GIC_PPI 13 158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 14 160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 11 162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 10 164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 165 }; 166 167 pmu { 168 compatible = "arm,cortex-a35-pmu"; 169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, 170 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, 171 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, 172 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; 173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 174 }; 175 176 soc { 177 #address-cells = <2>; 178 #size-cells = <2>; 179 compatible = "simple-bus"; 180 ranges; 181 182 topckgen: topckgen@10000000 { 183 compatible = "mediatek,mt8516-topckgen", "syscon"; 184 reg = <0 0x10000000 0 0x1000>; 185 #clock-cells = <1>; 186 }; 187 188 infracfg: infracfg@10001000 { 189 compatible = "mediatek,mt8516-infracfg", "syscon"; 190 reg = <0 0x10001000 0 0x1000>; 191 #clock-cells = <1>; 192 }; 193 194 pericfg: pericfg@10003050 { 195 compatible = "mediatek,mt8516-pericfg", "syscon"; 196 reg = <0 0x10003050 0 0x1000>; 197 }; 198 199 apmixedsys: apmixedsys@10018000 { 200 compatible = "mediatek,mt8516-apmixedsys", "syscon"; 201 reg = <0 0x10018000 0 0x710>; 202 #clock-cells = <1>; 203 }; 204 205 watchdog@10007000 { 206 compatible = "mediatek,mt8516-wdt", 207 "mediatek,mt6589-wdt"; 208 reg = <0 0x10007000 0 0x1000>; 209 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 210 #reset-cells = <1>; 211 }; 212 213 timer: timer@10008000 { 214 compatible = "mediatek,mt8516-timer", 215 "mediatek,mt6577-timer"; 216 reg = <0 0x10008000 0 0x1000>; 217 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 218 clocks = <&topckgen CLK_TOP_CLK26M_D2>, 219 <&topckgen CLK_TOP_APXGPT>; 220 clock-names = "clk13m", "bus"; 221 }; 222 223 keypad: keypad@10002000 { 224 compatible = "mediatek,mt8516-keypad", 225 "mediatek,mt6779-keypad"; 226 reg = <0 0x10002000 0 0x1000>; 227 wakeup-source; 228 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_FALLING>; 229 clocks = <&clk26m>; 230 clock-names = "kpd"; 231 status = "disabled"; 232 }; 233 234 syscfg_pctl: syscfg-pctl@10005000 { 235 compatible = "syscon"; 236 reg = <0 0x10005000 0 0x1000>; 237 }; 238 239 pio: pinctrl@1000b000 { 240 compatible = "mediatek,mt8516-pinctrl"; 241 reg = <0 0x1000b000 0 0x1000>; 242 mediatek,pctl-regmap = <&syscfg_pctl>; 243 gpio-controller; 244 #gpio-cells = <2>; 245 interrupt-controller; 246 #interrupt-cells = <2>; 247 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 248 }; 249 250 efuse: efuse@10009000 { 251 compatible = "mediatek,mt8516-efuse", "mediatek,efuse"; 252 reg = <0 0x10009000 0 0x1000>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 }; 256 257 pwrap: pwrap@1000f000 { 258 compatible = "mediatek,mt8516-pwrap"; 259 reg = <0 0x1000f000 0 0x1000>; 260 reg-names = "pwrap"; 261 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 262 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, 263 <&topckgen CLK_TOP_PMICWRAP_AP>; 264 clock-names = "spi", "wrap"; 265 }; 266 267 sysirq: interrupt-controller@10200620 { 268 compatible = "mediatek,mt8516-sysirq", 269 "mediatek,mt6577-sysirq"; 270 interrupt-controller; 271 #interrupt-cells = <3>; 272 interrupt-parent = <&gic>; 273 reg = <0 0x10200620 0 0x20>; 274 }; 275 276 gic: interrupt-controller@10310000 { 277 compatible = "arm,gic-400"; 278 #interrupt-cells = <3>; 279 interrupt-parent = <&gic>; 280 interrupt-controller; 281 reg = <0 0x10310000 0 0x1000>, 282 <0 0x1032f000 0 0x2000>, 283 <0 0x10340000 0 0x2000>, 284 <0 0x10360000 0 0x2000>; 285 interrupts = <GIC_PPI 9 286 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 287 }; 288 289 apdma: dma-controller@11000480 { 290 compatible = "mediatek,mt8516-uart-dma", 291 "mediatek,mt6577-uart-dma"; 292 reg = <0 0x11000480 0 0x80>, 293 <0 0x11000500 0 0x80>, 294 <0 0x11000580 0 0x80>, 295 <0 0x11000600 0 0x80>, 296 <0 0x11000980 0 0x80>, 297 <0 0x11000a00 0 0x80>; 298 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>, 299 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>, 300 <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>, 301 <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>, 302 <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>, 303 <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>; 304 dma-requests = <6>; 305 clocks = <&topckgen CLK_TOP_APDMA>; 306 clock-names = "apdma"; 307 #dma-cells = <1>; 308 }; 309 310 uart0: serial@11005000 { 311 compatible = "mediatek,mt8516-uart", 312 "mediatek,mt6577-uart"; 313 reg = <0 0x11005000 0 0x1000>; 314 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 315 clocks = <&topckgen CLK_TOP_UART0_SEL>, 316 <&topckgen CLK_TOP_UART0>; 317 clock-names = "baud", "bus"; 318 dmas = <&apdma 0 319 &apdma 1>; 320 dma-names = "tx", "rx"; 321 status = "disabled"; 322 }; 323 324 uart1: serial@11006000 { 325 compatible = "mediatek,mt8516-uart", 326 "mediatek,mt6577-uart"; 327 reg = <0 0x11006000 0 0x1000>; 328 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 329 clocks = <&topckgen CLK_TOP_UART1_SEL>, 330 <&topckgen CLK_TOP_UART1>; 331 clock-names = "baud", "bus"; 332 dmas = <&apdma 2 333 &apdma 3>; 334 dma-names = "tx", "rx"; 335 status = "disabled"; 336 }; 337 338 uart2: serial@11007000 { 339 compatible = "mediatek,mt8516-uart", 340 "mediatek,mt6577-uart"; 341 reg = <0 0x11007000 0 0x1000>; 342 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; 343 clocks = <&topckgen CLK_TOP_UART2_SEL>, 344 <&topckgen CLK_TOP_UART2>; 345 clock-names = "baud", "bus"; 346 dmas = <&apdma 4 347 &apdma 5>; 348 dma-names = "tx", "rx"; 349 status = "disabled"; 350 }; 351 352 i2c0: i2c@11009000 { 353 compatible = "mediatek,mt8516-i2c", 354 "mediatek,mt2712-i2c"; 355 reg = <0 0x11009000 0 0x90>, 356 <0 0x11000180 0 0x80>; 357 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 358 clock-div = <2>; 359 clocks = <&topckgen CLK_TOP_I2C0>, 360 <&topckgen CLK_TOP_APDMA>; 361 clock-names = "main", "dma"; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 status = "disabled"; 365 }; 366 367 i2c1: i2c@1100a000 { 368 compatible = "mediatek,mt8516-i2c", 369 "mediatek,mt2712-i2c"; 370 reg = <0 0x1100a000 0 0x90>, 371 <0 0x11000200 0 0x80>; 372 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 373 clock-div = <2>; 374 clocks = <&topckgen CLK_TOP_I2C1>, 375 <&topckgen CLK_TOP_APDMA>; 376 clock-names = "main", "dma"; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 status = "disabled"; 380 }; 381 382 i2c2: i2c@1100b000 { 383 compatible = "mediatek,mt8516-i2c", 384 "mediatek,mt2712-i2c"; 385 reg = <0 0x1100b000 0 0x90>, 386 <0 0x11000280 0 0x80>; 387 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 388 clock-div = <2>; 389 clocks = <&topckgen CLK_TOP_I2C2>, 390 <&topckgen CLK_TOP_APDMA>; 391 clock-names = "main", "dma"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 spi: spi@1100c000 { 398 compatible = "mediatek,mt8516-spi", 399 "mediatek,mt2712-spi"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 reg = <0 0x1100c000 0 0x1000>; 403 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 404 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, 405 <&topckgen CLK_TOP_SPI_SEL>, 406 <&topckgen CLK_TOP_SPI>; 407 clock-names = "parent-clk", "sel-clk", "spi-clk"; 408 status = "disabled"; 409 }; 410 411 mmc0: mmc@11120000 { 412 compatible = "mediatek,mt8516-mmc"; 413 reg = <0 0x11120000 0 0x1000>; 414 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 415 clocks = <&topckgen CLK_TOP_MSDC0>, 416 <&topckgen CLK_TOP_AHB_INFRA_SEL>, 417 <&topckgen CLK_TOP_MSDC0_INFRA>; 418 clock-names = "source", "hclk", "source_cg"; 419 status = "disabled"; 420 }; 421 422 mmc1: mmc@11130000 { 423 compatible = "mediatek,mt8516-mmc"; 424 reg = <0 0x11130000 0 0x1000>; 425 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 426 clocks = <&topckgen CLK_TOP_MSDC1>, 427 <&topckgen CLK_TOP_AHB_INFRA_SEL>, 428 <&topckgen CLK_TOP_MSDC1_INFRA>; 429 clock-names = "source", "hclk", "source_cg"; 430 status = "disabled"; 431 }; 432 433 mmc2: mmc@11170000 { 434 compatible = "mediatek,mt8516-mmc"; 435 reg = <0 0x11170000 0 0x1000>; 436 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>; 437 clocks = <&topckgen CLK_TOP_MSDC2>, 438 <&topckgen CLK_TOP_RG_MSDC2>, 439 <&topckgen CLK_TOP_MSDC2_INFRA>; 440 clock-names = "source", "hclk", "source_cg"; 441 status = "disabled"; 442 }; 443 444 ethernet: ethernet@11180000 { 445 compatible = "mediatek,mt8516-eth"; 446 reg = <0 0x11180000 0 0x1000>; 447 mediatek,pericfg = <&pericfg>; 448 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; 449 clocks = <&topckgen CLK_TOP_RG_ETH>, 450 <&topckgen CLK_TOP_66M_ETH>, 451 <&topckgen CLK_TOP_133M_ETH>; 452 clock-names = "core", "reg", "trans"; 453 status = "disabled"; 454 }; 455 456 rng: rng@1020c000 { 457 compatible = "mediatek,mt8516-rng", 458 "mediatek,mt7623-rng"; 459 reg = <0 0x1020c000 0 0x100>; 460 clocks = <&topckgen CLK_TOP_TRNG>; 461 clock-names = "rng"; 462 }; 463 464 pwm: pwm@11008000 { 465 compatible = "mediatek,mt8516-pwm"; 466 reg = <0 0x11008000 0 0x1000>; 467 #pwm-cells = <2>; 468 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 469 clocks = <&topckgen CLK_TOP_PWM>, 470 <&topckgen CLK_TOP_PWM_B>, 471 <&topckgen CLK_TOP_PWM1_FB>, 472 <&topckgen CLK_TOP_PWM2_FB>, 473 <&topckgen CLK_TOP_PWM3_FB>, 474 <&topckgen CLK_TOP_PWM4_FB>, 475 <&topckgen CLK_TOP_PWM5_FB>; 476 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 477 "pwm4", "pwm5"; 478 }; 479 480 usb0: usb@11100000 { 481 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; 482 reg = <0 0x11100000 0 0x1000>; 483 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 484 interrupt-names = "mc"; 485 phys = <&usb0_port PHY_TYPE_USB2>; 486 clocks = <&topckgen CLK_TOP_USB>, 487 <&topckgen CLK_TOP_USBIF>, 488 <&topckgen CLK_TOP_USB_1P>; 489 clock-names = "main","mcu","univpll"; 490 status = "disabled"; 491 }; 492 493 usb1: usb@11190000 { 494 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; 495 reg = <0 0x11190000 0 0x1000>; 496 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; 497 interrupt-names = "mc"; 498 phys = <&usb1_port PHY_TYPE_USB2>; 499 clocks = <&topckgen CLK_TOP_USB>, 500 <&topckgen CLK_TOP_USBIF>, 501 <&topckgen CLK_TOP_USB_1P>; 502 clock-names = "main","mcu","univpll"; 503 dr_mode = "host"; 504 status = "disabled"; 505 }; 506 507 usb_phy: t-phy@11110000 { 508 compatible = "mediatek,mt8516-tphy", 509 "mediatek,generic-tphy-v1"; 510 reg = <0 0x11110000 0 0x800>; 511 #address-cells = <2>; 512 #size-cells = <2>; 513 ranges; 514 status = "disabled"; 515 516 usb0_port: usb-phy@11110800 { 517 reg = <0 0x11110800 0 0x100>; 518 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 519 clock-names = "ref"; 520 #phy-cells = <1>; 521 }; 522 523 usb1_port: usb-phy@11110900 { 524 reg = <0 0x11110900 0 0x100>; 525 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 526 clock-names = "ref"; 527 #phy-cells = <1>; 528 }; 529 }; 530 531 auxadc: adc@11003000 { 532 compatible = "mediatek,mt8516-auxadc", 533 "mediatek,mt8173-auxadc"; 534 reg = <0 0x11003000 0 0x1000>; 535 clocks = <&topckgen CLK_TOP_AUX_ADC>; 536 clock-names = "main"; 537 #io-channel-cells = <1>; 538 status = "disabled"; 539 }; 540 }; 541}; 542