1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2024 Kontron Europe GmbH 4 * 5 * Author: Michael Walle <[email protected]> 6 */ 7/dts-v1/; 8 9#include "mt8195.dtsi" 10#include "mt6359.dtsi" 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/leds/common.h> 15#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 16#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> 17#include <dt-bindings/spmi/spmi.h> 18 19/ { 20 model = "Kontron 3.5\"-SBC-i1200"; 21 compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195"; 22 23 aliases { 24 mmc0 = &mmc0; 25 mmc1 = &mmc1; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart0; 31 }; 32 33 chosen { 34 stdout-path = "serial0:115200n8"; 35 }; 36 37 firmware { 38 optee { 39 compatible = "linaro,optee-tz"; 40 method = "smc"; 41 }; 42 }; 43 44 gpio-keys { 45 compatible = "gpio-keys"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&gpio_keys_pins>; 48 49 key-0 { 50 gpios = <&pio 106 GPIO_ACTIVE_LOW>; 51 label = "volume_up"; 52 linux,code = <KEY_VOLUMEUP>; 53 wakeup-source; 54 debounce-interval = <15>; 55 }; 56 }; 57 58 leds { 59 compatible = "gpio-leds"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&led_pins>; 62 63 led-0 { 64 gpios = <&pio 107 GPIO_ACTIVE_HIGH>; 65 default-state = "keep"; 66 function = LED_FUNCTION_POWER; 67 color = <LED_COLOR_ID_GREEN>; 68 }; 69 }; 70 71 memory@40000000 { 72 device_type = "memory"; 73 reg = <0 0x40000000 0x0 0x80000000>; 74 }; 75 76 vsys: regulator-vsys { 77 compatible = "regulator-fixed"; 78 regulator-name = "vsys"; 79 regulator-always-on; 80 regulator-boot-on; 81 regulator-min-microvolt = <5000000>; 82 regulator-max-microvolt = <5000000>; 83 }; 84 85 reserved-memory { 86 #address-cells = <2>; 87 #size-cells = <2>; 88 ranges; 89 90 /* 91 * 12 MiB reserved for OP-TEE (BL32) 92 * +-----------------------+ 0x43e0_0000 93 * | SHMEM 2MiB | 94 * +-----------------------+ 0x43c0_0000 95 * | | TA_RAM 8MiB | 96 * + TZDRAM +--------------+ 0x4340_0000 97 * | | TEE_RAM 2MiB | 98 * +-----------------------+ 0x4320_0000 99 */ 100 optee_reserved: optee@43200000 { 101 no-map; 102 reg = <0 0x43200000 0 0x00c00000>; 103 }; 104 105 scp_mem: memory@50000000 { 106 compatible = "shared-dma-pool"; 107 reg = <0 0x50000000 0 0x2900000>; 108 no-map; 109 }; 110 111 vpu_mem: memory@53000000 { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ 114 }; 115 116 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 117 bl31_secmon_mem: memory@54600000 { 118 no-map; 119 reg = <0 0x54600000 0x0 0x200000>; 120 }; 121 122 snd_dma_mem: memory@60000000 { 123 compatible = "shared-dma-pool"; 124 reg = <0 0x60000000 0 0x1100000>; 125 no-map; 126 }; 127 128 apu_mem: memory@62000000 { 129 compatible = "shared-dma-pool"; 130 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ 131 }; 132 }; 133 134 thermal_sensor0: thermal-sensor-0 { 135 compatible = "generic-adc-thermal"; 136 #thermal-sensor-cells = <0>; 137 io-channels = <&auxadc 0>; 138 io-channel-names = "sensor-channel"; 139 temperature-lookup-table = <(-25000) 1474 140 (-20000) 1374 141 (-15000) 1260 142 (-10000) 1134 143 (-5000) 1004 144 0 874 145 5000 750 146 10000 635 147 15000 532 148 20000 443 149 25000 367 150 30000 303 151 35000 250 152 40000 206 153 45000 170 154 50000 141 155 55000 117 156 60000 97 157 65000 81 158 70000 68 159 75000 57 160 80000 48 161 85000 41 162 90000 35 163 95000 30 164 100000 25 165 105000 22 166 110000 19 167 115000 16 168 120000 14 169 125000 12 170 130000 10 171 135000 9 172 140000 8 173 145000 7 174 150000 6>; 175 }; 176 177 thermal_sensor1: thermal-sensor-1 { 178 compatible = "generic-adc-thermal"; 179 #thermal-sensor-cells = <0>; 180 io-channels = <&auxadc 1>; 181 io-channel-names = "sensor-channel"; 182 temperature-lookup-table = <(-25000) 1474 183 (-20000) 1374 184 (-15000) 1260 185 (-10000) 1134 186 (-5000) 1004 187 0 874 188 5000 750 189 10000 635 190 15000 532 191 20000 443 192 25000 367 193 30000 303 194 35000 250 195 40000 206 196 45000 170 197 50000 141 198 55000 117 199 60000 97 200 65000 81 201 70000 68 202 75000 57 203 80000 48 204 85000 41 205 90000 35 206 95000 30 207 100000 25 208 105000 22 209 110000 19 210 115000 16 211 120000 14 212 125000 12 213 130000 10 214 135000 9 215 140000 8 216 145000 7 217 150000 6>; 218 }; 219 220 thermal_sensor2: thermal-sensor-2 { 221 compatible = "generic-adc-thermal"; 222 #thermal-sensor-cells = <0>; 223 io-channels = <&auxadc 2>; 224 io-channel-names = "sensor-channel"; 225 temperature-lookup-table = <(-25000) 1474 226 (-20000) 1374 227 (-15000) 1260 228 (-10000) 1134 229 (-5000) 1004 230 0 874 231 5000 750 232 10000 635 233 15000 532 234 20000 443 235 25000 367 236 30000 303 237 35000 250 238 40000 206 239 45000 170 240 50000 141 241 55000 117 242 60000 97 243 65000 81 244 70000 68 245 75000 57 246 80000 48 247 85000 41 248 90000 35 249 95000 30 250 100000 25 251 105000 22 252 110000 19 253 115000 16 254 120000 14 255 125000 12 256 130000 10 257 135000 9 258 140000 8 259 145000 7 260 150000 6>; 261 }; 262}; 263 264&auxadc { 265 status = "okay"; 266}; 267 268ð { 269 phy-mode ="rgmii-id"; 270 phy-handle = <ðernet_phy0>; 271 pinctrl-names = "default", "sleep"; 272 pinctrl-0 = <ð_default_pins>; 273 pinctrl-1 = <ð_sleep_pins>; 274 mediatek,mac-wol; 275 status = "okay"; 276 277 mdio { 278 ethernet_phy0: ethernet-phy@1 { 279 compatible = "ethernet-phy-id001c.c916"; 280 reg = <0x1>; 281 interrupts-extended = <&pio 94 IRQ_TYPE_LEVEL_LOW>; 282 reset-assert-us = <10000>; 283 reset-deassert-us = <80000>; 284 reset-gpios = <&pio 93 GPIO_ACTIVE_HIGH>; 285 }; 286 }; 287}; 288 289&gpu { 290 status = "okay"; 291 mali-supply = <&mt6315_7_vbuck1>; 292}; 293 294/* CSI1/CSI2 connector */ 295&i2c0 { 296 pinctrl-names = "default"; 297 pinctrl-0 = <&i2c0_pins>; 298 clock-frequency = <100000>; 299 status = "okay"; 300}; 301 302/* CSI3 connector */ 303&i2c1 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&i2c1_pins>; 306 clock-frequency = <100000>; 307 status = "okay"; 308}; 309 310&i2c2 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&i2c2_pins>; 313 clock-frequency = <400000>; 314 status = "okay"; 315 316 /* LVDS bridge @f */ 317}; 318 319/* Touch panel connector */ 320&i2c3 { 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c3_pins>; 323 clock-frequency = <100000>; 324 status = "okay"; 325}; 326 327/* B2B connector */ 328&i2c4 { 329 clock-frequency = <100000>; 330 pinctrl-0 = <&i2c4_pins>; 331 pinctrl-names = "default"; 332 status = "okay"; 333}; 334 335&i2c6 { 336 clock-frequency = <400000>; 337 pinctrl-0 = <&i2c6_pins>; 338 pinctrl-names = "default"; 339 status = "okay"; 340 341 mt6360: pmic@34 { 342 compatible = "mediatek,mt6360"; 343 reg = <0x34>; 344 interrupt-controller; 345 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; 346 interrupt-names = "IRQB"; 347 #interrupt-cells = <1>; 348 349 regulator { 350 compatible = "mediatek,mt6360-regulator"; 351 LDO_VIN1-supply = <&vsys>; 352 LDO_VIN2-supply = <&vsys>; 353 LDO_VIN3-supply = <&vsys>; 354 355 mt6360_buck1: BUCK1 { 356 regulator-name = "emi_vdd2"; 357 regulator-min-microvolt = <600000>; 358 regulator-max-microvolt = <1800000>; 359 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 360 MT6360_OPMODE_LP 361 MT6360_OPMODE_ULP>; 362 regulator-always-on; 363 }; 364 365 mt6360_buck2: BUCK2 { 366 regulator-name = "emi_vddq"; 367 regulator-min-microvolt = <300000>; 368 regulator-max-microvolt = <1300000>; 369 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 370 MT6360_OPMODE_LP 371 MT6360_OPMODE_ULP>; 372 regulator-always-on; 373 }; 374 375 mt6360_ldo1: LDO1 { 376 regulator-name = "mt6360_ldo1"; /* Test point */ 377 regulator-min-microvolt = <1200000>; 378 regulator-max-microvolt = <3600000>; 379 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 380 MT6360_OPMODE_LP>; 381 }; 382 383 mt6360_ldo2: LDO2 { 384 regulator-name = "panel1_p1v8"; 385 regulator-min-microvolt = <1800000>; 386 regulator-max-microvolt = <1800000>; 387 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 388 MT6360_OPMODE_LP>; 389 }; 390 391 mt6360_ldo3: LDO3 { 392 regulator-name = "vmc_pmu"; 393 regulator-min-microvolt = <1800000>; 394 regulator-max-microvolt = <3300000>; 395 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 396 MT6360_OPMODE_LP>; 397 }; 398 399 mt6360_ldo5: LDO5 { 400 regulator-name = "vmch_pmu"; 401 regulator-min-microvolt = <3300000>; 402 regulator-max-microvolt = <3300000>; 403 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 404 MT6360_OPMODE_LP>; 405 }; 406 407 mt6360_ldo6: LDO6 { 408 regulator-name = "mt6360_ldo6"; /* Test point */ 409 regulator-min-microvolt = <500000>; 410 regulator-max-microvolt = <2100000>; 411 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 412 MT6360_OPMODE_LP>; 413 }; 414 415 mt6360_ldo7: LDO7 { 416 regulator-name = "emi_vmddr_en"; 417 regulator-min-microvolt = <1800000>; 418 regulator-max-microvolt = <1800000>; 419 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 420 MT6360_OPMODE_LP>; 421 regulator-always-on; 422 }; 423 }; 424 }; 425}; 426 427&mmc0 { 428 pinctrl-names = "default", "state_uhs"; 429 pinctrl-0 = <&mmc0_default_pins>; 430 pinctrl-1 = <&mmc0_uhs_pins>; 431 bus-width = <8>; 432 max-frequency = <200000000>; 433 hs400-ds-delay = <0x14c11>; 434 cap-mmc-highspeed; 435 cap-mmc-hw-reset; 436 mmc-hs200-1_8v; 437 mmc-hs400-1_8v; 438 no-sdio; 439 no-sd; 440 non-removable; 441 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 442 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 443 status = "okay"; 444}; 445 446&mmc1 { 447 pinctrl-names = "default", "state_uhs"; 448 pinctrl-0 = <&mmc1_default_pins>, <&mmc1_detect_pins>; 449 pinctrl-1 = <&mmc1_default_pins>; 450 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; 451 bus-width = <4>; 452 max-frequency = <200000000>; 453 cap-sd-highspeed; 454 sd-uhs-sdr50; 455 sd-uhs-sdr104; 456 no-mmc; 457 vmmc-supply = <&mt6360_ldo5>; 458 vqmmc-supply = <&mt6360_ldo3>; 459 status = "okay"; 460}; 461 462&mt6359_vbbck_ldo_reg { 463 regulator-always-on; 464}; 465 466&mt6359_vcore_buck_reg { 467 regulator-always-on; 468}; 469 470&mt6359_vgpu11_buck_reg { 471 regulator-always-on; 472}; 473 474&mt6359_vproc1_buck_reg { 475 regulator-always-on; 476}; 477 478&mt6359_vproc2_buck_reg { 479 regulator-always-on; 480}; 481 482&mt6359_vpu_buck_reg { 483 regulator-always-on; 484}; 485 486&mt6359_vrf12_ldo_reg { 487 regulator-always-on; 488}; 489 490&mt6359_vsram_md_ldo_reg { 491 regulator-always-on; 492}; 493 494&mt6359_vsram_others_ldo_reg { 495 regulator-always-on; 496}; 497 498&nor_flash { 499 pinctrl-names = "default"; 500 pinctrl-0 = <&nor_pins_default>; 501 status = "okay"; 502 503 flash@0 { 504 compatible = "jedec,spi-nor"; 505 reg = <0>; 506 spi-max-frequency = <52000000>; 507 spi-rx-bus-width = <2>; 508 spi-tx-bus-width = <2>; 509 }; 510}; 511 512&pcie0 { 513 pinctrl-names = "default"; 514 pinctrl-0 = <&pcie0_pins_default>; 515 status = "okay"; 516}; 517 518&pcie1 { 519 pinctrl-names = "default"; 520 pinctrl-0 = <&pcie1_pins_default>; 521 status = "okay"; 522}; 523 524&pciephy { 525 status = "okay"; 526}; 527 528&pio { 529 eth_default_pins: eth-default-pins { 530 pins-txd { 531 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, 532 <PINMUX_GPIO78__FUNC_GBE_TXD2>, 533 <PINMUX_GPIO79__FUNC_GBE_TXD1>, 534 <PINMUX_GPIO80__FUNC_GBE_TXD0>; 535 drive-strength = <8>; 536 }; 537 538 pins-rxd { 539 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, 540 <PINMUX_GPIO82__FUNC_GBE_RXD2>, 541 <PINMUX_GPIO83__FUNC_GBE_RXD1>, 542 <PINMUX_GPIO84__FUNC_GBE_RXD0>; 543 }; 544 545 pins-cc { 546 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, 547 <PINMUX_GPIO86__FUNC_GBE_RXC>, 548 <PINMUX_GPIO87__FUNC_GBE_RXDV>, 549 <PINMUX_GPIO88__FUNC_GBE_TXEN>; 550 drive-strength = <8>; 551 }; 552 553 pins-mdio { 554 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, 555 <PINMUX_GPIO90__FUNC_GBE_MDIO>; 556 input-enable; 557 }; 558 559 pins-power { 560 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, 561 <PINMUX_GPIO92__FUNC_GPIO92>; 562 output-high; 563 }; 564 565 pins-reset { 566 pinmux = <PINMUX_GPIO93__FUNC_GPIO93>; 567 output-high; 568 }; 569 570 pins-interrupt { 571 pinmux = <PINMUX_GPIO94__FUNC_GPIO94>; 572 input-enable; 573 }; 574 }; 575 576 eth_sleep_pins: eth-sleep-pins { 577 pins-txd { 578 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 579 <PINMUX_GPIO78__FUNC_GPIO78>, 580 <PINMUX_GPIO79__FUNC_GPIO79>, 581 <PINMUX_GPIO80__FUNC_GPIO80>; 582 }; 583 584 pins-cc { 585 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, 586 <PINMUX_GPIO88__FUNC_GPIO88>, 587 <PINMUX_GPIO87__FUNC_GPIO87>, 588 <PINMUX_GPIO86__FUNC_GPIO86>; 589 }; 590 591 pins-rxd { 592 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, 593 <PINMUX_GPIO82__FUNC_GPIO82>, 594 <PINMUX_GPIO83__FUNC_GPIO83>, 595 <PINMUX_GPIO84__FUNC_GPIO84>; 596 }; 597 598 pins-mdio { 599 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, 600 <PINMUX_GPIO90__FUNC_GPIO90>; 601 input-disable; 602 bias-disable; 603 }; 604 }; 605 606 gpio_keys_pins: gpio-keys-pins { 607 pins { 608 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; 609 input-enable; 610 }; 611 }; 612 613 i2c0_pins: i2c0-pins { 614 pins { 615 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 616 <PINMUX_GPIO9__FUNC_SCL0>; 617 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 618 drive-strength-microamp = <1000>; 619 }; 620 }; 621 622 i2c1_pins: i2c1-pins { 623 pins { 624 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 625 <PINMUX_GPIO11__FUNC_SCL1>; 626 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 627 drive-strength-microamp = <1000>; 628 }; 629 }; 630 631 i2c2_pins: i2c2-default-pins { 632 pins-bus { 633 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 634 <PINMUX_GPIO13__FUNC_SCL2>; 635 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 636 drive-strength-microamp = <1000>; 637 }; 638 }; 639 640 i2c3_pins: i2c3-pins { 641 pins { 642 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 643 <PINMUX_GPIO15__FUNC_SCL3>; 644 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 645 drive-strength-microamp = <1000>; 646 }; 647 }; 648 649 i2c4_pins: i2c4-pins { 650 pins { 651 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 652 <PINMUX_GPIO17__FUNC_SCL4>; 653 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 654 drive-strength-microamp = <1000>; 655 }; 656 }; 657 658 i2c6_pins: i2c6-pins { 659 pins { 660 pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 661 <PINMUX_GPIO26__FUNC_SCL6>; 662 bias-pull-up; 663 drive-strength-microamp = <1000>; 664 }; 665 }; 666 667 mmc0_default_pins: mmc0-default-pins { 668 pins-clk { 669 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 670 drive-strength = <6>; 671 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 672 }; 673 674 pins-cmd-dat { 675 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 676 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 677 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 678 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 679 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 680 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 681 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 682 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 683 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 684 input-enable; 685 drive-strength = <6>; 686 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 687 }; 688 689 pins-rst { 690 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 691 drive-strength = <6>; 692 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 693 }; 694 }; 695 696 mmc0_uhs_pins: mmc0-uhs-pins { 697 pins-clk { 698 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 699 drive-strength = <8>; 700 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 701 }; 702 703 pins-cmd-dat { 704 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 705 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 706 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 707 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 708 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 709 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 710 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 711 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 712 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 713 input-enable; 714 drive-strength = <8>; 715 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 716 }; 717 718 pins-ds { 719 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 720 drive-strength = <8>; 721 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 722 }; 723 724 pins-rst { 725 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 726 drive-strength = <8>; 727 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 728 }; 729 }; 730 731 mmc1_default_pins: mmc1-default-pins { 732 pins-clk { 733 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 734 drive-strength = <8>; 735 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 736 }; 737 738 pins-cmd-dat { 739 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 740 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 741 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 742 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 743 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 744 input-enable; 745 drive-strength = <8>; 746 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 747 }; 748 }; 749 750 mmc1_detect_pins: mmc1-detect-pins { 751 pins-insert { 752 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 753 bias-pull-up; 754 }; 755 }; 756 757 nor_pins_default: nor-default-pins { 758 pins-ck-io { 759 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 760 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 761 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 762 drive-strength = <6>; 763 bias-pull-down; 764 }; 765 766 pins-cs { 767 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 768 drive-strength = <6>; 769 bias-pull-up; 770 }; 771 }; 772 773 pcie0_pins_default: pcie0-default-pins { 774 pins-bus { 775 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 776 <PINMUX_GPIO20__FUNC_PERSTN>, 777 <PINMUX_GPIO21__FUNC_CLKREQN>; 778 bias-pull-up; 779 }; 780 }; 781 782 pcie1_pins_default: pcie1-default-pins { 783 pins-bus { 784 pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>, 785 <PINMUX_GPIO1__FUNC_CLKREQN_1>, 786 <PINMUX_GPIO2__FUNC_WAKEN_1>; 787 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 788 }; 789 }; 790 791 led_pins: led-pins { 792 pins-power-en { 793 pinmux = <PINMUX_GPIO107__FUNC_GPIO107>; 794 output-high; 795 }; 796 }; 797 798 spi0_pins: spi0-default-pins { 799 pins-cs-mosi-clk { 800 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 801 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 802 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 803 bias-disable; 804 }; 805 806 pins-miso { 807 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 808 bias-pull-down; 809 }; 810 }; 811 812 spi1_pins: spi1-default-pins { 813 pins-cs-mosi-clk { 814 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, 815 <PINMUX_GPIO138__FUNC_SPIM1_MO>, 816 <PINMUX_GPIO137__FUNC_SPIM1_CLK>; 817 bias-disable; 818 }; 819 820 pins-miso { 821 pinmux = <PINMUX_GPIO139__FUNC_SPIM1_MI>; 822 bias-pull-down; 823 }; 824 }; 825 826 uart0_pins: uart0-pins { 827 pins-rx { 828 pinmux = <PINMUX_GPIO99__FUNC_URXD0>; 829 input-enable; 830 bias-pull-up; 831 }; 832 833 pins-tx { 834 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>; 835 }; 836 }; 837 838 uart1_pins: uart1-pins { 839 pins-rx { 840 pinmux = <PINMUX_GPIO103__FUNC_URXD1>; 841 input-enable; 842 bias-pull-up; 843 }; 844 845 pins-tx { 846 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>; 847 }; 848 849 pins-rts { 850 pinmux = <PINMUX_GPIO100__FUNC_URTS1>; 851 }; 852 853 pins-cts { 854 pinmux = <PINMUX_GPIO101__FUNC_UCTS1>; 855 input-enable; 856 }; 857 }; 858 859 uart2_pins: uart2-pins { 860 pins-rx { 861 pinmux = <PINMUX_GPIO68__FUNC_URXD2>; 862 input-enable; 863 bias-pull-up; 864 }; 865 866 pins-tx { 867 pinmux = <PINMUX_GPIO67__FUNC_UTXD2>; 868 }; 869 870 pins-rts { 871 pinmux = <PINMUX_GPIO66__FUNC_URTS2>; 872 }; 873 874 pins-cts { 875 pinmux = <PINMUX_GPIO65__FUNC_UCTS2>; 876 input-enable; 877 }; 878 }; 879 880 uart3_pins: uart3-pins { 881 pins-rx { 882 pinmux = <PINMUX_GPIO5__FUNC_URXD3>; 883 input-enable; 884 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 885 }; 886 887 pins-tx { 888 pinmux = <PINMUX_GPIO4__FUNC_UTXD3>; 889 }; 890 }; 891 892 uart4_pins: uart4-pins { 893 pins-rx { 894 pinmux = <PINMUX_GPIO7__FUNC_URXD4>; 895 input-enable; 896 bias-pull-up; 897 }; 898 899 pins-tx { 900 pinmux = <PINMUX_GPIO6__FUNC_UTXD4>; 901 }; 902 }; 903}; 904 905&pmic { 906 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 907}; 908 909&scp { 910 memory-region = <&scp_mem>; 911 firmware-name = "mediatek/mt8195/scp.img"; 912 status = "okay"; 913}; 914 915&spmi { 916 #address-cells = <2>; 917 #size-cells = <0>; 918 919 mt6315@6 { 920 compatible = "mediatek,mt6315-regulator"; 921 reg = <0x6 SPMI_USID>; 922 923 regulators { 924 mt6315_6_vbuck1: vbuck1 { 925 regulator-name = "Vbcpu"; 926 regulator-min-microvolt = <300000>; 927 regulator-max-microvolt = <1193750>; 928 regulator-enable-ramp-delay = <256>; 929 regulator-ramp-delay = <6250>; 930 regulator-allowed-modes = <0 1 2>; 931 regulator-always-on; 932 }; 933 }; 934 }; 935 936 mt6315@7 { 937 compatible = "mediatek,mt6315-regulator"; 938 reg = <0x7 SPMI_USID>; 939 940 regulators { 941 mt6315_7_vbuck1: vbuck1 { 942 regulator-name = "Vgpu"; 943 regulator-min-microvolt = <625000>; 944 regulator-max-microvolt = <1193750>; 945 regulator-enable-ramp-delay = <256>; 946 regulator-ramp-delay = <6250>; 947 regulator-allowed-modes = <0 1 2>; 948 regulator-always-on; 949 }; 950 }; 951 }; 952}; 953 954/* USB3.2 front port */ 955&ssusb0 { 956 dr_mode = "host"; 957 vusb33-supply = <&mt6359_vusb_ldo_reg>; 958 status = "okay"; 959}; 960 961/* USB2.0 M.2 Key-E */ 962&ssusb2 { 963 vusb33-supply = <&mt6359_vusb_ldo_reg>; 964 status = "okay"; 965}; 966 967/* USB2.0 to on-board usb hub */ 968&ssusb3 { 969 vusb33-supply = <&mt6359_vusb_ldo_reg>; 970 status = "okay"; 971}; 972 973&spi0 { 974 pinctrl-names = "default"; 975 pinctrl-0 = <&spi0_pins>; 976 mediatek,pad-select = <0>; 977 status = "okay"; 978 979 tpm: tpm@0 { 980 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 981 reg = <0>; 982 spi-max-frequency = <18500000>; 983 }; 984}; 985 986/* B2B connector */ 987&spi1 { 988 pinctrl-names = "default"; 989 pinctrl-0 = <&spi1_pins>; 990 mediatek,pad-select = <0>; 991 status = "okay"; 992}; 993 994&thermal_zones { 995 cpu-thermal { 996 polling-delay = <1000>; /* milliseconds */ 997 polling-delay-passive = <0>; /* milliseconds */ 998 thermal-sensors = <&thermal_sensor0>; 999 1000 trips { 1001 trip-alert { 1002 temperature = <85000>; 1003 hysteresis = <2000>; 1004 type = "passive"; 1005 }; 1006 1007 trip-crit { 1008 temperature = <95000>; 1009 hysteresis = <2000>; 1010 type = "critical"; 1011 }; 1012 }; 1013 }; 1014 1015 pcb-top-thermal { 1016 polling-delay = <1000>; /* milliseconds */ 1017 polling-delay-passive = <0>; /* milliseconds */ 1018 thermal-sensors = <&thermal_sensor1>; 1019 1020 trips { 1021 trip-alert { 1022 temperature = <75000>; 1023 hysteresis = <2000>; 1024 type = "passive"; 1025 }; 1026 1027 trip-crit { 1028 temperature = <85000>; 1029 hysteresis = <2000>; 1030 type = "critical"; 1031 }; 1032 }; 1033 }; 1034 1035 pcb-bottom-thermal { 1036 polling-delay = <1000>; /* milliseconds */ 1037 polling-delay-passive = <0>; /* milliseconds */ 1038 thermal-sensors = <&thermal_sensor2>; 1039 1040 trips { 1041 trip-alert { 1042 temperature = <75000>; 1043 hysteresis = <2000>; 1044 type = "passive"; 1045 }; 1046 1047 trip-crit { 1048 temperature = <85000>; 1049 hysteresis = <2000>; 1050 type = "critical"; 1051 }; 1052 }; 1053 }; 1054}; 1055 1056&uart0 { 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&uart0_pins>; 1059 status = "okay"; 1060}; 1061 1062&uart1 { 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&uart1_pins>; 1065 uart-has-rtscts; 1066 status = "okay"; 1067}; 1068 1069&uart2 { 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&uart2_pins>; 1072 uart-has-rtscts; 1073 status = "okay"; 1074}; 1075 1076&uart3 { 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&uart3_pins>; 1079 status = "okay"; 1080}; 1081 1082&uart4 { 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&uart4_pins>; 1085 status = "okay"; 1086}; 1087 1088/* USB3 */ 1089&u3phy0 { 1090 status = "okay"; 1091}; 1092 1093/* PCIe1/USB2 */ 1094&u3phy1 { 1095 status = "okay"; 1096}; 1097 1098/* USB2 */ 1099&u3phy2 { 1100 status = "okay"; 1101}; 1102 1103/* USB2 */ 1104&u3phy3 { 1105 status = "okay"; 1106}; 1107 1108/* USB3.2 front port */ 1109&xhci0 { 1110 status = "okay"; 1111}; 1112 1113/* USB2.0 M.2 Key-B */ 1114&xhci1 { 1115 phys = <&u2port1 PHY_TYPE_USB2>; 1116 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1117 mediatek,u3p-dis-msk = <0x01>; 1118 status = "okay"; 1119}; 1120 1121/* USB2.0 M.2 Key-E */ 1122&xhci2 { 1123 status = "okay"; 1124}; 1125 1126/* USB2.0 to on-board usb hub */ 1127&xhci3 { 1128 status = "okay"; 1129}; 1130