1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Authors: Fabien Parent <[email protected]> 6 * Bernhard Rosenkränzer <[email protected]> 7 * Alexandre Mergnat <[email protected]> 8 */ 9 10#include <dt-bindings/clock/mediatek,mt8365-clk.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/power/mediatek,mt8365-power.h> 15 16/ { 17 compatible = "mediatek,mt8365"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cluster0_opp: opp-table-0 { 27 compatible = "operating-points-v2"; 28 opp-shared; 29 30 opp-850000000 { 31 opp-hz = /bits/ 64 <850000000>; 32 opp-microvolt = <650000>; 33 }; 34 35 opp-918000000 { 36 opp-hz = /bits/ 64 <918000000>; 37 opp-microvolt = <668750>; 38 }; 39 40 opp-987000000 { 41 opp-hz = /bits/ 64 <987000000>; 42 opp-microvolt = <687500>; 43 }; 44 45 opp-1056000000 { 46 opp-hz = /bits/ 64 <1056000000>; 47 opp-microvolt = <706250>; 48 }; 49 50 opp-1125000000 { 51 opp-hz = /bits/ 64 <1125000000>; 52 opp-microvolt = <725000>; 53 }; 54 55 opp-1216000000 { 56 opp-hz = /bits/ 64 <1216000000>; 57 opp-microvolt = <750000>; 58 }; 59 60 opp-1308000000 { 61 opp-hz = /bits/ 64 <1308000000>; 62 opp-microvolt = <775000>; 63 }; 64 65 opp-1400000000 { 66 opp-hz = /bits/ 64 <1400000000>; 67 opp-microvolt = <800000>; 68 }; 69 70 opp-1466000000 { 71 opp-hz = /bits/ 64 <1466000000>; 72 opp-microvolt = <825000>; 73 }; 74 75 opp-1533000000 { 76 opp-hz = /bits/ 64 <1533000000>; 77 opp-microvolt = <850000>; 78 }; 79 80 opp-1633000000 { 81 opp-hz = /bits/ 64 <1633000000>; 82 opp-microvolt = <887500>; 83 }; 84 85 opp-1700000000 { 86 opp-hz = /bits/ 64 <1700000000>; 87 opp-microvolt = <912500>; 88 }; 89 90 opp-1767000000 { 91 opp-hz = /bits/ 64 <1767000000>; 92 opp-microvolt = <937500>; 93 }; 94 95 opp-1834000000 { 96 opp-hz = /bits/ 64 <1834000000>; 97 opp-microvolt = <962500>; 98 }; 99 100 opp-1917000000 { 101 opp-hz = /bits/ 64 <1917000000>; 102 opp-microvolt = <993750>; 103 }; 104 105 opp-2001000000 { 106 opp-hz = /bits/ 64 <2001000000>; 107 opp-microvolt = <1025000>; 108 }; 109 }; 110 111 cpu-map { 112 cluster0 { 113 core0 { 114 cpu = <&cpu0>; 115 }; 116 core1 { 117 cpu = <&cpu1>; 118 }; 119 core2 { 120 cpu = <&cpu2>; 121 }; 122 core3 { 123 cpu = <&cpu3>; 124 }; 125 }; 126 }; 127 128 cpu0: cpu@0 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53"; 131 reg = <0x0>; 132 #cooling-cells = <2>; 133 enable-method = "psci"; 134 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 135 i-cache-size = <0x8000>; 136 i-cache-line-size = <64>; 137 i-cache-sets = <256>; 138 d-cache-size = <0x8000>; 139 d-cache-line-size = <64>; 140 d-cache-sets = <256>; 141 next-level-cache = <&l2>; 142 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 143 <&apmixedsys CLK_APMIXED_MAINPLL>; 144 clock-names = "cpu", "intermediate"; 145 operating-points-v2 = <&cluster0_opp>; 146 }; 147 148 cpu1: cpu@1 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53"; 151 reg = <0x1>; 152 #cooling-cells = <2>; 153 enable-method = "psci"; 154 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 155 i-cache-size = <0x8000>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <256>; 158 d-cache-size = <0x8000>; 159 d-cache-line-size = <64>; 160 d-cache-sets = <256>; 161 next-level-cache = <&l2>; 162 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 163 <&apmixedsys CLK_APMIXED_MAINPLL>; 164 clock-names = "cpu", "intermediate", "armpll"; 165 operating-points-v2 = <&cluster0_opp>; 166 }; 167 168 cpu2: cpu@2 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a53"; 171 reg = <0x2>; 172 #cooling-cells = <2>; 173 enable-method = "psci"; 174 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 175 i-cache-size = <0x8000>; 176 i-cache-line-size = <64>; 177 i-cache-sets = <256>; 178 d-cache-size = <0x8000>; 179 d-cache-line-size = <64>; 180 d-cache-sets = <256>; 181 next-level-cache = <&l2>; 182 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 183 <&apmixedsys CLK_APMIXED_MAINPLL>; 184 clock-names = "cpu", "intermediate", "armpll"; 185 operating-points-v2 = <&cluster0_opp>; 186 }; 187 188 cpu3: cpu@3 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a53"; 191 reg = <0x3>; 192 #cooling-cells = <2>; 193 enable-method = "psci"; 194 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 195 i-cache-size = <0x8000>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <0x8000>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2>; 202 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 203 <&apmixedsys CLK_APMIXED_MAINPLL>; 204 clock-names = "cpu", "intermediate", "armpll"; 205 operating-points-v2 = <&cluster0_opp>; 206 }; 207 208 idle-states { 209 entry-method = "psci"; 210 211 CPU_MCDI: cpu-mcdi { 212 compatible = "arm,idle-state"; 213 local-timer-stop; 214 arm,psci-suspend-param = <0x00010001>; 215 entry-latency-us = <300>; 216 exit-latency-us = <200>; 217 min-residency-us = <1000>; 218 }; 219 220 CLUSTER_MCDI: cluster-mcdi { 221 compatible = "arm,idle-state"; 222 local-timer-stop; 223 arm,psci-suspend-param = <0x01010001>; 224 entry-latency-us = <350>; 225 exit-latency-us = <250>; 226 min-residency-us = <1200>; 227 }; 228 229 CLUSTER_DPIDLE: cluster-dpidle { 230 compatible = "arm,idle-state"; 231 local-timer-stop; 232 arm,psci-suspend-param = <0x01010004>; 233 entry-latency-us = <300>; 234 exit-latency-us = <800>; 235 min-residency-us = <3300>; 236 }; 237 }; 238 239 l2: l2-cache { 240 compatible = "cache"; 241 cache-level = <2>; 242 cache-size = <0x80000>; 243 cache-line-size = <64>; 244 cache-sets = <512>; 245 cache-unified; 246 }; 247 }; 248 249 clk26m: oscillator { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <26000000>; 253 clock-output-names = "clk26m"; 254 }; 255 256 psci { 257 compatible = "arm,psci-1.0"; 258 method = "smc"; 259 }; 260 261 soc { 262 #address-cells = <2>; 263 #size-cells = <2>; 264 compatible = "simple-bus"; 265 ranges; 266 267 gic: interrupt-controller@c000000 { 268 compatible = "arm,gic-v3"; 269 #interrupt-cells = <3>; 270 interrupt-parent = <&gic>; 271 interrupt-controller; 272 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 273 <0 0x0c080000 0 0x80000>, /* GICR */ 274 <0 0x0c400000 0 0x2000>, /* GICC */ 275 <0 0x0c410000 0 0x1000>, /* GICH */ 276 <0 0x0c420000 0 0x2000>; /* GICV */ 277 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 topckgen: syscon@10000000 { 282 compatible = "mediatek,mt8365-topckgen", "syscon"; 283 reg = <0 0x10000000 0 0x1000>; 284 #clock-cells = <1>; 285 }; 286 287 infracfg: syscon@10001000 { 288 compatible = "mediatek,mt8365-infracfg", "syscon"; 289 reg = <0 0x10001000 0 0x1000>; 290 #clock-cells = <1>; 291 }; 292 293 pericfg: syscon@10003000 { 294 compatible = "mediatek,mt8365-pericfg", "syscon"; 295 reg = <0 0x10003000 0 0x1000>; 296 #clock-cells = <1>; 297 }; 298 299 syscfg_pctl: syscfg-pctl@10005000 { 300 compatible = "mediatek,mt8365-syscfg", "syscon"; 301 reg = <0 0x10005000 0 0x1000>; 302 }; 303 304 scpsys: syscon@10006000 { 305 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; 306 reg = <0 0x10006000 0 0x1000>; 307 308 /* System Power Manager */ 309 spm: power-controller { 310 compatible = "mediatek,mt8365-power-controller"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 #power-domain-cells = <1>; 314 315 /* power domains of the SoC */ 316 power-domain@MT8365_POWER_DOMAIN_MM { 317 reg = <MT8365_POWER_DOMAIN_MM>; 318 clocks = <&topckgen CLK_TOP_MM_SEL>, 319 <&mmsys CLK_MM_MM_SMI_COMMON>, 320 <&mmsys CLK_MM_MM_SMI_COMM0>, 321 <&mmsys CLK_MM_MM_SMI_COMM1>, 322 <&mmsys CLK_MM_MM_SMI_LARB0>; 323 clock-names = "mm", "mm-0", "mm-1", 324 "mm-2", "mm-3"; 325 #power-domain-cells = <0>; 326 mediatek,infracfg = <&infracfg>; 327 mediatek,infracfg-nao = <&infracfg_nao>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 power-domain@MT8365_POWER_DOMAIN_CAM { 332 reg = <MT8365_POWER_DOMAIN_CAM>; 333 clocks = <&camsys CLK_CAM_LARB2>, 334 <&camsys CLK_CAM_SENIF>, 335 <&camsys CLK_CAMSV0>, 336 <&camsys CLK_CAMSV1>, 337 <&camsys CLK_CAM_FDVT>, 338 <&camsys CLK_CAM_WPE>; 339 clock-names = "cam-0", "cam-1", 340 "cam-2", "cam-3", 341 "cam-4", "cam-5"; 342 #power-domain-cells = <0>; 343 mediatek,infracfg = <&infracfg>; 344 mediatek,smi = <&smi_common>; 345 }; 346 347 power-domain@MT8365_POWER_DOMAIN_VDEC { 348 reg = <MT8365_POWER_DOMAIN_VDEC>; 349 #power-domain-cells = <0>; 350 mediatek,smi = <&smi_common>; 351 }; 352 353 power-domain@MT8365_POWER_DOMAIN_VENC { 354 reg = <MT8365_POWER_DOMAIN_VENC>; 355 #power-domain-cells = <0>; 356 mediatek,smi = <&smi_common>; 357 }; 358 359 power-domain@MT8365_POWER_DOMAIN_APU { 360 reg = <MT8365_POWER_DOMAIN_APU>; 361 clocks = <&infracfg CLK_IFR_APU_AXI>, 362 <&apu CLK_APU_IPU_CK>, 363 <&apu CLK_APU_AXI>, 364 <&apu CLK_APU_JTAG>, 365 <&apu CLK_APU_IF_CK>, 366 <&apu CLK_APU_EDMA>, 367 <&apu CLK_APU_AHB>; 368 clock-names = "apu", "apu-0", 369 "apu-1", "apu-2", 370 "apu-3", "apu-4", 371 "apu-5"; 372 #power-domain-cells = <0>; 373 mediatek,infracfg = <&infracfg>; 374 mediatek,smi = <&smi_common>; 375 }; 376 }; 377 378 power-domain@MT8365_POWER_DOMAIN_CONN { 379 reg = <MT8365_POWER_DOMAIN_CONN>; 380 clocks = <&topckgen CLK_TOP_CONN_32K>, 381 <&topckgen CLK_TOP_CONN_26M>; 382 clock-names = "conn", "conn1"; 383 #power-domain-cells = <0>; 384 mediatek,infracfg = <&infracfg>; 385 }; 386 387 power-domain@MT8365_POWER_DOMAIN_MFG { 388 reg = <MT8365_POWER_DOMAIN_MFG>; 389 clocks = <&topckgen CLK_TOP_MFG_SEL>; 390 clock-names = "mfg"; 391 #power-domain-cells = <0>; 392 mediatek,infracfg = <&infracfg>; 393 }; 394 395 power-domain@MT8365_POWER_DOMAIN_AUDIO { 396 reg = <MT8365_POWER_DOMAIN_AUDIO>; 397 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 398 <&infracfg CLK_IFR_AUDIO>, 399 <&infracfg CLK_IFR_AUD_26M_BK>; 400 clock-names = "audio", "audio1", "audio2"; 401 #power-domain-cells = <0>; 402 mediatek,infracfg = <&infracfg>; 403 }; 404 405 power-domain@MT8365_POWER_DOMAIN_DSP { 406 reg = <MT8365_POWER_DOMAIN_DSP>; 407 clocks = <&topckgen CLK_TOP_DSP_SEL>, 408 <&topckgen CLK_TOP_DSP_26M>; 409 clock-names = "dsp", "dsp1"; 410 #power-domain-cells = <0>; 411 mediatek,infracfg = <&infracfg>; 412 }; 413 }; 414 }; 415 416 watchdog: watchdog@10007000 { 417 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 418 reg = <0 0x10007000 0 0x100>; 419 #reset-cells = <1>; 420 }; 421 422 pio: pinctrl@1000b000 { 423 compatible = "mediatek,mt8365-pinctrl"; 424 reg = <0 0x1000b000 0 0x1000>; 425 mediatek,pctl-regmap = <&syscfg_pctl>; 426 gpio-controller; 427 #gpio-cells = <2>; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 431 }; 432 433 apmixedsys: syscon@1000c000 { 434 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 435 reg = <0 0x1000c000 0 0x1000>; 436 #clock-cells = <1>; 437 }; 438 439 pwrap: pwrap@1000d000 { 440 compatible = "mediatek,mt8365-pwrap"; 441 reg = <0 0x1000d000 0 0x1000>; 442 reg-names = "pwrap"; 443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 445 <&infracfg CLK_IFR_PMIC_AP>, 446 <&infracfg CLK_IFR_PWRAP_SYS>, 447 <&infracfg CLK_IFR_PWRAP_TMR>; 448 clock-names = "spi", "wrap", "sys", "tmr"; 449 }; 450 451 keypad: keypad@10010000 { 452 compatible = "mediatek,mt8365-keypad", 453 "mediatek,mt6779-keypad"; 454 reg = <0 0x10010000 0 0x1000>; 455 wakeup-source; 456 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 457 clocks = <&clk26m>; 458 clock-names = "kpd"; 459 status = "disabled"; 460 }; 461 462 mcucfg: syscon@10200000 { 463 compatible = "mediatek,mt8365-mcucfg", "syscon"; 464 reg = <0 0x10200000 0 0x2000>; 465 #clock-cells = <1>; 466 }; 467 468 sysirq: interrupt-controller@10200a80 { 469 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 470 interrupt-controller; 471 #interrupt-cells = <3>; 472 interrupt-parent = <&gic>; 473 reg = <0 0x10200a80 0 0x20>; 474 }; 475 476 iommu: iommu@10205000 { 477 compatible = "mediatek,mt8365-m4u"; 478 reg = <0 0x10205000 0 0x1000>; 479 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; 480 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; 481 #iommu-cells = <1>; 482 }; 483 484 infracfg_nao: infracfg@1020e000 { 485 compatible = "mediatek,mt8365-infracfg", "syscon"; 486 reg = <0 0x1020e000 0 0x1000>; 487 #clock-cells = <1>; 488 }; 489 490 rng: rng@1020f000 { 491 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 492 reg = <0 0x1020f000 0 0x100>; 493 clocks = <&infracfg CLK_IFR_TRNG>; 494 clock-names = "rng"; 495 }; 496 497 apdma: dma-controller@11000280 { 498 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 499 reg = <0 0x11000280 0 0x80>, 500 <0 0x11000300 0 0x80>, 501 <0 0x11000380 0 0x80>, 502 <0 0x11000400 0 0x80>, 503 <0 0x11000580 0 0x80>, 504 <0 0x11000600 0 0x80>; 505 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 506 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 507 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 508 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 509 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 510 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 511 dma-requests = <6>; 512 clocks = <&infracfg CLK_IFR_AP_DMA>; 513 clock-names = "apdma"; 514 #dma-cells = <1>; 515 }; 516 517 uart0: serial@11002000 { 518 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 519 reg = <0 0x11002000 0 0x1000>; 520 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 521 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 522 clock-names = "baud", "bus"; 523 dmas = <&apdma 0>, <&apdma 1>; 524 dma-names = "tx", "rx"; 525 status = "disabled"; 526 }; 527 528 uart1: serial@11003000 { 529 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 530 reg = <0 0x11003000 0 0x1000>; 531 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 532 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 533 clock-names = "baud", "bus"; 534 dmas = <&apdma 2>, <&apdma 3>; 535 dma-names = "tx", "rx"; 536 status = "disabled"; 537 }; 538 539 uart2: serial@11004000 { 540 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 541 reg = <0 0x11004000 0 0x1000>; 542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 543 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 544 clock-names = "baud", "bus"; 545 dmas = <&apdma 4>, <&apdma 5>; 546 dma-names = "tx", "rx"; 547 status = "disabled"; 548 }; 549 550 pwm: pwm@11006000 { 551 compatible = "mediatek,mt8365-pwm"; 552 reg = <0 0x11006000 0 0x1000>; 553 #pwm-cells = <2>; 554 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 555 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 556 <&infracfg CLK_IFR_PWM>, 557 <&infracfg CLK_IFR_PWM1>, 558 <&infracfg CLK_IFR_PWM2>, 559 <&infracfg CLK_IFR_PWM3>; 560 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 561 }; 562 563 i2c0: i2c@11007000 { 564 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 565 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 566 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 567 clock-div = <1>; 568 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 569 clock-names = "main", "dma"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 status = "disabled"; 573 }; 574 575 i2c1: i2c@11008000 { 576 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 577 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 578 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 579 clock-div = <1>; 580 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 581 clock-names = "main", "dma"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 i2c2: i2c@11009000 { 588 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 589 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 590 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 591 clock-div = <1>; 592 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 593 clock-names = "main", "dma"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 status = "disabled"; 597 }; 598 599 spi: spi@1100a000 { 600 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 601 reg = <0 0x1100a000 0 0x100>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 605 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 606 <&topckgen CLK_TOP_SPI_SEL>, 607 <&infracfg CLK_IFR_SPI0>; 608 clock-names = "parent-clk", "sel-clk", "spi-clk"; 609 status = "disabled"; 610 }; 611 612 i2c3: i2c@1100f000 { 613 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 614 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 615 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 616 clock-div = <1>; 617 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 618 clock-names = "main", "dma"; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 status = "disabled"; 622 }; 623 624 ssusb: usb@11201000 { 625 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 626 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 627 reg-names = "mac", "ippc"; 628 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 629 phys = <&u2port0 PHY_TYPE_USB2>, 630 <&u2port1 PHY_TYPE_USB2>; 631 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 632 <&infracfg CLK_IFR_SSUSB_REF>, 633 <&infracfg CLK_IFR_SSUSB_SYS>, 634 <&infracfg CLK_IFR_ICUSB>; 635 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges; 639 status = "disabled"; 640 641 usb_host: usb@11200000 { 642 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 643 reg = <0 0x11200000 0 0x1000>; 644 reg-names = "mac"; 645 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 646 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 647 <&infracfg CLK_IFR_SSUSB_REF>, 648 <&infracfg CLK_IFR_SSUSB_SYS>, 649 <&infracfg CLK_IFR_ICUSB>, 650 <&infracfg CLK_IFR_SSUSB_XHCI>; 651 clock-names = "sys_ck", "ref_ck", "mcu_ck", 652 "dma_ck", "xhci_ck"; 653 status = "disabled"; 654 }; 655 }; 656 657 mmc0: mmc@11230000 { 658 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 659 reg = <0 0x11230000 0 0x1000>, 660 <0 0x11cd0000 0 0x1000>; 661 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 662 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 663 <&infracfg CLK_IFR_MSDC0_HCLK>, 664 <&infracfg CLK_IFR_MSDC0_SRC>; 665 clock-names = "source", "hclk", "source_cg"; 666 status = "disabled"; 667 }; 668 669 mmc1: mmc@11240000 { 670 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 671 reg = <0 0x11240000 0 0x1000>, 672 <0 0x11c90000 0 0x1000>; 673 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 674 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 675 <&infracfg CLK_IFR_MSDC1_HCLK>, 676 <&infracfg CLK_IFR_MSDC1_SRC>; 677 clock-names = "source", "hclk", "source_cg"; 678 status = "disabled"; 679 }; 680 681 mmc2: mmc@11250000 { 682 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 683 reg = <0 0x11250000 0 0x1000>, 684 <0 0x11c60000 0 0x1000>; 685 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 686 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 687 <&infracfg CLK_IFR_MSDC2_HCLK>, 688 <&infracfg CLK_IFR_MSDC2_SRC>, 689 <&infracfg CLK_IFR_MSDC2_BK>, 690 <&infracfg CLK_IFR_AP_MSDC0>; 691 clock-names = "source", "hclk", "source_cg", 692 "bus_clk", "sys_cg"; 693 status = "disabled"; 694 }; 695 696 ethernet: ethernet@112a0000 { 697 compatible = "mediatek,mt8365-eth"; 698 reg = <0 0x112a0000 0 0x1000>; 699 mediatek,pericfg = <&infracfg>; 700 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&topckgen CLK_TOP_ETH_SEL>, 702 <&infracfg CLK_IFR_NIC_AXI>, 703 <&infracfg CLK_IFR_NIC_SLV_AXI>; 704 clock-names = "core", "reg", "trans"; 705 status = "disabled"; 706 }; 707 708 u3phy: t-phy@11cc0000 { 709 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 ranges = <0 0 0x11cc0000 0x9000>; 713 714 u2port0: usb-phy@0 { 715 reg = <0x0 0x400>; 716 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 717 <&topckgen CLK_TOP_USB20_48M_EN>; 718 clock-names = "ref", "da_ref"; 719 #phy-cells = <1>; 720 }; 721 722 u2port1: usb-phy@1000 { 723 reg = <0x1000 0x400>; 724 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 725 <&topckgen CLK_TOP_USB20_48M_EN>; 726 clock-names = "ref", "da_ref"; 727 #phy-cells = <1>; 728 }; 729 }; 730 731 mmsys: syscon@14000000 { 732 compatible = "mediatek,mt8365-mmsys", "syscon"; 733 reg = <0 0x14000000 0 0x1000>; 734 #clock-cells = <1>; 735 }; 736 737 smi_common: smi@14002000 { 738 compatible = "mediatek,mt8365-smi-common"; 739 reg = <0 0x14002000 0 0x1000>; 740 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, 741 <&mmsys CLK_MM_MM_SMI_COMMON>, 742 <&mmsys CLK_MM_MM_SMI_COMM0>, 743 <&mmsys CLK_MM_MM_SMI_COMM1>; 744 clock-names = "apb", "smi", "gals0", "gals1"; 745 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 746 }; 747 748 larb0: larb@14003000 { 749 compatible = "mediatek,mt8365-smi-larb", 750 "mediatek,mt8186-smi-larb"; 751 reg = <0 0x14003000 0 0x1000>; 752 mediatek,smi = <&smi_common>; 753 clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, 754 <&mmsys CLK_MM_MM_SMI_LARB0>; 755 clock-names = "apb", "smi"; 756 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 757 mediatek,larb-id = <0>; 758 }; 759 760 camsys: syscon@15000000 { 761 compatible = "mediatek,mt8365-imgsys", "syscon"; 762 reg = <0 0x15000000 0 0x1000>; 763 #clock-cells = <1>; 764 }; 765 766 larb2: larb@15001000 { 767 compatible = "mediatek,mt8365-smi-larb", 768 "mediatek,mt8186-smi-larb"; 769 reg = <0 0x15001000 0 0x1000>; 770 mediatek,smi = <&smi_common>; 771 clocks = <&mmsys CLK_MM_MM_SMI_IMG>, 772 <&camsys CLK_CAM_LARB2>; 773 clock-names = "apb", "smi"; 774 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; 775 mediatek,larb-id = <2>; 776 }; 777 778 vdecsys: syscon@16000000 { 779 compatible = "mediatek,mt8365-vdecsys", "syscon"; 780 reg = <0 0x16000000 0 0x1000>; 781 #clock-cells = <1>; 782 }; 783 784 larb3: larb@16010000 { 785 compatible = "mediatek,mt8365-smi-larb", 786 "mediatek,mt8186-smi-larb"; 787 reg = <0 0x16010000 0 0x1000>; 788 mediatek,smi = <&smi_common>; 789 clocks = <&vdecsys CLK_VDEC_LARB1>, 790 <&vdecsys CLK_VDEC_LARB1>; 791 clock-names = "apb", "smi"; 792 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; 793 mediatek,larb-id = <3>; 794 }; 795 796 vencsys: syscon@17000000 { 797 compatible = "mediatek,mt8365-vencsys", "syscon"; 798 reg = <0 0x17000000 0 0x1000>; 799 #clock-cells = <1>; 800 }; 801 802 larb1: larb@17010000 { 803 compatible = "mediatek,mt8365-smi-larb", 804 "mediatek,mt8186-smi-larb"; 805 reg = <0 0x17010000 0 0x1000>; 806 mediatek,smi = <&smi_common>; 807 clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; 808 clock-names = "apb", "smi"; 809 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; 810 mediatek,larb-id = <1>; 811 }; 812 813 apu: syscon@19020000 { 814 compatible = "mediatek,mt8365-apu", "syscon"; 815 reg = <0 0x19020000 0 0x1000>; 816 #clock-cells = <1>; 817 }; 818 819 afe: audio-controller@11220000 { 820 compatible = "mediatek,mt8365-afe-pcm"; 821 reg = <0 0x11220000 0 0x1000>; 822 #sound-dai-cells = <0>; 823 clocks = <&clk26m>, 824 <&topckgen CLK_TOP_AUDIO_SEL>, 825 <&topckgen CLK_TOP_AUD_I2S0_M>, 826 <&topckgen CLK_TOP_AUD_I2S1_M>, 827 <&topckgen CLK_TOP_AUD_I2S2_M>, 828 <&topckgen CLK_TOP_AUD_I2S3_M>, 829 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 830 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 831 <&topckgen CLK_TOP_AUD_1_SEL>, 832 <&topckgen CLK_TOP_AUD_2_SEL>, 833 <&topckgen CLK_TOP_APLL_I2S0_SEL>, 834 <&topckgen CLK_TOP_APLL_I2S1_SEL>, 835 <&topckgen CLK_TOP_APLL_I2S2_SEL>, 836 <&topckgen CLK_TOP_APLL_I2S3_SEL>; 837 clock-names = "top_clk26m_clk", 838 "top_audio_sel", 839 "audio_i2s0_m", 840 "audio_i2s1_m", 841 "audio_i2s2_m", 842 "audio_i2s3_m", 843 "engen1", 844 "engen2", 845 "aud1", 846 "aud2", 847 "i2s0_m_sel", 848 "i2s1_m_sel", 849 "i2s2_m_sel", 850 "i2s3_m_sel"; 851 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 852 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>; 853 status = "disabled"; 854 }; 855 }; 856 857 timer { 858 compatible = "arm,armv8-timer"; 859 interrupt-parent = <&gic>; 860 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 861 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 862 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 863 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 864 }; 865 866 system_clk: dummy13m { 867 compatible = "fixed-clock"; 868 clock-frequency = <13000000>; 869 #clock-cells = <0>; 870 }; 871 872 systimer: timer@10017000 { 873 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 874 reg = <0 0x10017000 0 0x100>; 875 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&system_clk>; 877 clock-names = "clk13m"; 878 }; 879}; 880