1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 BayLibre, SAS.
4 * Author: Fabien Parent <[email protected]>
5 */
6/dts-v1/;
7
8#include "mt8195.dtsi"
9#include "mt6359.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
15
16/ {
17	model = "MediaTek MT8195 demo board";
18	compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:921600n8";
26	};
27
28	firmware {
29		optee {
30			compatible = "linaro,optee-tz";
31			method = "smc";
32		};
33	};
34
35	gpio-keys {
36		compatible = "gpio-keys";
37		pinctrl-names = "default";
38		pinctrl-0 = <&gpio_keys_pins>;
39
40		key-0 {
41			gpios = <&pio 106 GPIO_ACTIVE_LOW>;
42			label = "volume_up";
43			linux,code = <KEY_VOLUMEUP>;
44			wakeup-source;
45			debounce-interval = <15>;
46		};
47	};
48
49	memory@40000000 {
50		device_type = "memory";
51		reg = <0 0x40000000 0x2 0x00000000>;
52	};
53
54	reserved-memory {
55		#address-cells = <2>;
56		#size-cells = <2>;
57		ranges;
58
59		/*
60		 * 12 MiB reserved for OP-TEE (BL32)
61		 * +-----------------------+ 0x43e0_0000
62		 * |      SHMEM 2MiB       |
63		 * +-----------------------+ 0x43c0_0000
64		 * |        | TA_RAM  8MiB |
65		 * + TZDRAM +--------------+ 0x4340_0000
66		 * |        | TEE_RAM 2MiB |
67		 * +-----------------------+ 0x4320_0000
68		 */
69		optee_reserved: optee@43200000 {
70			no-map;
71			reg = <0 0x43200000 0 0x00c00000>;
72		};
73
74		scp_mem: memory@50000000 {
75			compatible = "shared-dma-pool";
76			reg = <0 0x50000000 0 0x2900000>;
77			no-map;
78		};
79
80		vpu_mem: memory@53000000 {
81			compatible = "shared-dma-pool";
82			reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
83		};
84
85		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
86		bl31_secmon_mem: memory@54600000 {
87			no-map;
88			reg = <0 0x54600000 0x0 0x200000>;
89		};
90
91		snd_dma_mem: memory@60000000 {
92			compatible = "shared-dma-pool";
93			reg = <0 0x60000000 0 0x1100000>;
94			no-map;
95		};
96
97		apu_mem: memory@62000000 {
98			compatible = "shared-dma-pool";
99			reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
100		};
101	};
102};
103
104&eth {
105	phy-mode = "rgmii-id";
106	phy-handle = <&ethernet_phy0>;
107	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
108	snps,reset-delays-us = <0 10000 80000>;
109	pinctrl-names = "default", "sleep";
110	pinctrl-0 = <&eth_default_pins>;
111	pinctrl-1 = <&eth_sleep_pins>;
112	mediatek,mac-wol;
113	status = "okay";
114
115	mdio {
116		ethernet_phy0: ethernet-phy@1 {
117			reg = <0x1>;
118		};
119	};
120};
121
122&i2c6 {
123	clock-frequency = <400000>;
124	pinctrl-0 = <&i2c6_pins>;
125	pinctrl-names = "default";
126	status = "okay";
127
128	mt6360: pmic@34 {
129		compatible = "mediatek,mt6360";
130		reg = <0x34>;
131		interrupt-controller;
132		#interrupt-cells = <1>;
133		interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
134		interrupt-names = "IRQB";
135
136		charger {
137			compatible = "mediatek,mt6360-chg";
138			richtek,vinovp-microvolt = <14500000>;
139
140			otg_vbus_regulator: usb-otg-vbus-regulator {
141				regulator-name = "usb-otg-vbus";
142				regulator-min-microvolt = <4425000>;
143				regulator-max-microvolt = <5825000>;
144			};
145		};
146
147		regulator {
148			compatible = "mediatek,mt6360-regulator";
149			LDO_VIN3-supply = <&mt6360_buck2>;
150
151			mt6360_buck1: buck1 {
152				regulator-name = "mt6360,buck1";
153				regulator-min-microvolt = <300000>;
154				regulator-max-microvolt = <1300000>;
155				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
156							   MT6360_OPMODE_LP
157							   MT6360_OPMODE_ULP>;
158				regulator-always-on;
159			};
160
161			mt6360_buck2: buck2 {
162				regulator-name = "mt6360,buck2";
163				regulator-min-microvolt = <300000>;
164				regulator-max-microvolt = <1300000>;
165				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
166							   MT6360_OPMODE_LP
167							   MT6360_OPMODE_ULP>;
168				regulator-always-on;
169			};
170
171			mt6360_ldo1: ldo1 {
172				regulator-name = "mt6360,ldo1";
173				regulator-min-microvolt = <1200000>;
174				regulator-max-microvolt = <3600000>;
175				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
176							   MT6360_OPMODE_LP>;
177			};
178
179			mt6360_ldo2: ldo2 {
180				regulator-name = "mt6360,ldo2";
181				regulator-min-microvolt = <1200000>;
182				regulator-max-microvolt = <3600000>;
183				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
184							   MT6360_OPMODE_LP>;
185			};
186
187			mt6360_ldo3: ldo3 {
188				regulator-name = "mt6360,ldo3";
189				regulator-min-microvolt = <1200000>;
190				regulator-max-microvolt = <3600000>;
191				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
192							   MT6360_OPMODE_LP>;
193			};
194
195			mt6360_ldo5: ldo5 {
196				regulator-name = "mt6360,ldo5";
197				regulator-min-microvolt = <2700000>;
198				regulator-max-microvolt = <3600000>;
199				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
200							   MT6360_OPMODE_LP>;
201			};
202
203			mt6360_ldo6: ldo6 {
204				regulator-name = "mt6360,ldo6";
205				regulator-min-microvolt = <500000>;
206				regulator-max-microvolt = <2100000>;
207				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
208							   MT6360_OPMODE_LP>;
209			};
210
211			mt6360_ldo7: ldo7 {
212				regulator-name = "mt6360,ldo7";
213				regulator-min-microvolt = <500000>;
214				regulator-max-microvolt = <2100000>;
215				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
216							   MT6360_OPMODE_LP>;
217				regulator-always-on;
218			};
219		};
220	};
221};
222
223&mmc0 {
224	status = "okay";
225	pinctrl-names = "default", "state_uhs";
226	pinctrl-0 = <&mmc0_default_pins>;
227	pinctrl-1 = <&mmc0_uhs_pins>;
228	bus-width = <8>;
229	max-frequency = <200000000>;
230	cap-mmc-highspeed;
231	mmc-hs200-1_8v;
232	mmc-hs400-1_8v;
233	cap-mmc-hw-reset;
234	no-sdio;
235	no-sd;
236	hs400-ds-delay = <0x14c11>;
237	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
238	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
239	non-removable;
240};
241
242&mmc1 {
243	pinctrl-names = "default", "state_uhs";
244	pinctrl-0 = <&mmc1_default_pins>;
245	pinctrl-1 = <&mmc1_uhs_pins>;
246	cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
247	bus-width = <4>;
248	max-frequency = <200000000>;
249	cap-sd-highspeed;
250	sd-uhs-sdr50;
251	sd-uhs-sdr104;
252	vmmc-supply = <&mt6360_ldo5>;
253	vqmmc-supply = <&mt6360_ldo3>;
254	status = "okay";
255};
256
257&mt6359_vbbck_ldo_reg {
258	regulator-always-on;
259};
260
261&mt6359_vcore_buck_reg {
262	regulator-always-on;
263};
264
265&mt6359_vgpu11_buck_reg {
266	regulator-always-on;
267};
268
269&mt6359_vproc1_buck_reg {
270	regulator-always-on;
271};
272
273&mt6359_vproc2_buck_reg {
274	regulator-always-on;
275};
276
277&mt6359_vpu_buck_reg {
278	regulator-always-on;
279};
280
281&mt6359_vrf12_ldo_reg {
282	regulator-always-on;
283};
284
285&mt6359_vsram_md_ldo_reg {
286	regulator-always-on;
287};
288
289&mt6359_vsram_others_ldo_reg {
290	regulator-always-on;
291};
292
293&pio {
294	eth_default_pins: eth-default-pins {
295		pins-txd {
296			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
297				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
298				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
299				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
300			drive-strength = <8>;
301		};
302		pins-cc {
303			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
304				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
305				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
306				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
307			drive-strength = <8>;
308		};
309		pins-rxd {
310			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
311				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
312				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
313				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
314		};
315		pins-mdio {
316			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
317				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
318			input-enable;
319		};
320		pins-power {
321			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
322				 <PINMUX_GPIO92__FUNC_GPIO92>;
323			output-high;
324		};
325	};
326
327	eth_sleep_pins: eth-sleep-pins {
328		pins-txd {
329			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
330				 <PINMUX_GPIO78__FUNC_GPIO78>,
331				 <PINMUX_GPIO79__FUNC_GPIO79>,
332				 <PINMUX_GPIO80__FUNC_GPIO80>;
333		};
334		pins-cc {
335			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
336				 <PINMUX_GPIO88__FUNC_GPIO88>,
337				 <PINMUX_GPIO87__FUNC_GPIO87>,
338				 <PINMUX_GPIO86__FUNC_GPIO86>;
339		};
340		pins-rxd {
341			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
342				 <PINMUX_GPIO82__FUNC_GPIO82>,
343				 <PINMUX_GPIO83__FUNC_GPIO83>,
344				 <PINMUX_GPIO84__FUNC_GPIO84>;
345		};
346		pins-mdio {
347			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
348				 <PINMUX_GPIO90__FUNC_GPIO90>;
349			input-disable;
350			bias-disable;
351		};
352	};
353
354	gpio_keys_pins: gpio-keys-pins {
355		pins {
356			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
357			input-enable;
358		};
359	};
360
361	i2c6_pins: i2c6-pins {
362		pins {
363			pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
364				 <PINMUX_GPIO26__FUNC_SCL6>;
365			bias-pull-up;
366		};
367	};
368
369	mmc0_default_pins: mmc0-default-pins {
370		pins-clk {
371			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
372			drive-strength = <6>;
373			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
374		};
375
376		pins-cmd-dat {
377			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
378				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
379				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
380				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
381				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
382				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
383				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
384				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
385				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
386			input-enable;
387			drive-strength = <6>;
388			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
389		};
390
391		pins-rst {
392			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
393			drive-strength = <6>;
394			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
395		};
396	};
397
398	mmc0_uhs_pins: mmc0-uhs-pins {
399		pins-clk {
400			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
401			drive-strength = <8>;
402			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
403		};
404
405		pins-cmd-dat {
406			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
407				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
408				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
409				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
410				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
411				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
412				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
413				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
414				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
415			input-enable;
416			drive-strength = <8>;
417			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
418		};
419
420		pins-ds {
421			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
422			drive-strength = <8>;
423			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
424		};
425
426		pins-rst {
427			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
428			drive-strength = <8>;
429			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
430		};
431	};
432
433	mmc1_default_pins: mmc1-default-pins {
434		pins-clk {
435			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
436			drive-strength = <8>;
437			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
438		};
439
440		pins-cmd-dat {
441			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
442				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
443				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
444				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
445				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
446			input-enable;
447			drive-strength = <8>;
448			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
449		};
450
451		pins-insert {
452			pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
453			bias-pull-up;
454		};
455	};
456
457	mmc1_uhs_pins: mmc1-uhs-pins {
458		pins-clk {
459			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
460			drive-strength = <8>;
461			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
462		};
463
464		pins-cmd-dat {
465			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
466				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
467				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
468				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
469				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
470			input-enable;
471			drive-strength = <8>;
472			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
473		};
474	};
475
476	uart0_pins: uart0-pins {
477		pins {
478			pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
479				 <PINMUX_GPIO99__FUNC_URXD0>;
480		};
481	};
482
483	uart1_pins: uart1-pins {
484		pins {
485			pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
486				 <PINMUX_GPIO103__FUNC_URXD1>;
487		};
488	};
489};
490
491
492&pmic {
493	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
494};
495
496&uart0 {
497	pinctrl-names = "default";
498	pinctrl-0 = <&uart0_pins>;
499	status = "okay";
500};
501
502&uart1 {
503	pinctrl-names = "default";
504	pinctrl-0 = <&uart1_pins>;
505	status = "okay";
506};
507
508&u3phy0 {
509	status = "okay";
510};
511
512&u3phy1 {
513	status = "okay";
514};
515
516&u3phy2 {
517	status = "okay";
518};
519
520&u3phy3 {
521	status = "okay";
522};
523
524&ssusb0 {
525	vusb33-supply = <&mt6359_vusb_ldo_reg>;
526	status = "okay";
527};
528
529&ssusb2 {
530	vusb33-supply = <&mt6359_vusb_ldo_reg>;
531	status = "okay";
532};
533
534&ssusb3 {
535	vusb33-supply = <&mt6359_vusb_ldo_reg>;
536	status = "okay";
537};
538
539&xhci0 {
540	vbus-supply = <&otg_vbus_regulator>;
541	status = "okay";
542};
543
544&xhci1 {
545	vusb33-supply = <&mt6359_vusb_ldo_reg>;
546	status = "okay";
547};
548
549&xhci2 {
550	status = "okay";
551};
552
553&xhci3 {
554	status = "okay";
555};
556