1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5/dts-v1/; 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8188.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 mmc0 = &mmc0; 20 serial0 = &uart0; 21 }; 22 23 backlight_lcd0: backlight-lcd0 { 24 compatible = "pwm-backlight"; 25 brightness-levels = <0 1023>; 26 default-brightness-level = <576>; 27 enable-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; 28 num-interpolated-steps = <1023>; 29 power-supply = <&ppvar_sys>; 30 pwms = <&disp_pwm0 0 500000>; 31 }; 32 33 chosen { 34 stdout-path = "serial0:115200n8"; 35 }; 36 37 dmic-codec { 38 compatible = "dmic-codec"; 39 num-channels = <2>; 40 wakeup-delay-ms = <100>; 41 }; 42 43 memory@40000000 { 44 device_type = "memory"; 45 /* The size will be filled in by the bootloader */ 46 reg = <0 0x40000000 0 0>; 47 }; 48 49 /* system wide LDO 1.8V power rail */ 50 pp1800_ldo_z1: regulator-pp1800-ldo-z1 { 51 compatible = "regulator-fixed"; 52 regulator-name = "pp1800_ldo_z1"; 53 /* controlled by PP3300_Z1 */ 54 regulator-always-on; 55 regulator-boot-on; 56 regulator-min-microvolt = <1800000>; 57 regulator-max-microvolt = <1800000>; 58 vin-supply = <&pp3300_z1>; 59 }; 60 61 /* separately switched 3.3V power rail */ 62 pp3300_s3: regulator-pp3300-s3 { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp3300_s3"; 65 /* controlled by PMIC */ 66 regulator-always-on; 67 regulator-boot-on; 68 regulator-min-microvolt = <3300000>; 69 regulator-max-microvolt = <3300000>; 70 vin-supply = <&pp3300_z1>; 71 }; 72 73 /* system wide 3.3V power rail */ 74 pp3300_z1: regulator-pp3300-z1 { 75 compatible = "regulator-fixed"; 76 regulator-name = "pp3300_z1"; 77 /* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */ 78 regulator-always-on; 79 regulator-boot-on; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 vin-supply = <&ppvar_sys>; 83 }; 84 85 pp3300_wlan: regulator-pp3300-wlan { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp3300_wlan"; 88 regulator-always-on; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 enable-active-high; 92 gpio = <&pio 12 GPIO_ACTIVE_HIGH>; 93 pinctrl-0 = <&wlan_en>; 94 pinctrl-names = "default"; 95 vin-supply = <&pp3300_z1>; 96 }; 97 98 /* system wide 4.2V power rail */ 99 pp4200_s5: regulator-pp4200-s5 { 100 compatible = "regulator-fixed"; 101 regulator-name = "pp4200_s5"; 102 /* controlled by EC */ 103 regulator-always-on; 104 regulator-boot-on; 105 regulator-min-microvolt = <4200000>; 106 regulator-max-microvolt = <4200000>; 107 vin-supply = <&ppvar_sys>; 108 }; 109 110 /* system wide 5.0V power rail */ 111 pp5000_z1: regulator-pp5000-z1 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pp5000_z1"; 114 /* controlled by EC */ 115 regulator-always-on; 116 regulator-boot-on; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 vin-supply = <&ppvar_sys>; 120 }; 121 122 pp5000_usb_vbus: regulator-pp5000-usb-vbus { 123 compatible = "regulator-fixed"; 124 regulator-name = "pp5000_usb_vbus"; 125 regulator-min-microvolt = <5000000>; 126 regulator-max-microvolt = <5000000>; 127 enable-active-high; 128 gpio = <&pio 150 GPIO_ACTIVE_HIGH>; 129 vin-supply = <&pp5000_z1>; 130 }; 131 132 /* system wide semi-regulated power rail from battery or USB */ 133 ppvar_sys: regulator-ppvar-sys { 134 compatible = "regulator-fixed"; 135 regulator-name = "ppvar_sys"; 136 regulator-always-on; 137 regulator-boot-on; 138 }; 139 140 ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd { 141 compatible = "regulator-fixed"; 142 regulator-name = "ppvar_mipi_disp_avdd"; 143 enable-active-high; 144 gpio = <&pio 3 GPIO_ACTIVE_HIGH>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&mipi_disp_avdd_en>; 147 vin-supply = <&pp5000_z1>; 148 }; 149 150 ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee { 151 compatible = "regulator-fixed"; 152 regulator-name = "ppvar_mipi_disp_avee"; 153 regulator-enable-ramp-delay = <10000>; 154 enable-active-high; 155 gpio = <&pio 4 GPIO_ACTIVE_HIGH>; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&mipi_disp_avee_en>; 158 vin-supply = <&pp5000_z1>; 159 }; 160 161 reserved_memory: reserved-memory { 162 #address-cells = <2>; 163 #size-cells = <2>; 164 ranges; 165 166 apu_mem: memory@55000000 { 167 compatible = "shared-dma-pool"; 168 reg = <0 0x55000000 0 0x1400000>; 169 }; 170 171 adsp_mem: memory@60000000 { 172 compatible = "shared-dma-pool"; 173 reg = <0 0x60000000 0 0xf00000>; 174 no-map; 175 }; 176 177 afe_dma_mem: memory@60f00000 { 178 compatible = "shared-dma-pool"; 179 reg = <0 0x60f00000 0 0x100000>; 180 no-map; 181 }; 182 183 adsp_dma_mem: memory@61000000 { 184 compatible = "shared-dma-pool"; 185 reg = <0 0x61000000 0 0x100000>; 186 no-map; 187 }; 188 }; 189}; 190 191&adsp { 192 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&adsp_uart_pins>; 195 status = "okay"; 196}; 197 198&afe { 199 memory-region = <&afe_dma_mem>; 200 mediatek,etdm-out1-cowork-source = <0>; /* in1 */ 201 mediatek,etdm-in2-cowork-source = <3>; /* out2 */ 202 status = "okay"; 203}; 204 205&auxadc { 206 status = "okay"; 207}; 208 209&cam_vcore { 210 domain-supply = <&mt6359_vproc1_buck_reg>; 211}; 212 213/* 214 * Geralt is the reference design and doesn't have target TDP. 215 * Ciri is (currently) the only device following Geralt, and its 216 * TDP target is 90 degrees. 217 **/ 218&cpu_little0_alert0 { 219 temperature = <90000>; 220 hysteresis = <2000>; 221 type = "passive"; 222}; 223 224&cpu_little1_alert0 { 225 temperature = <90000>; 226 hysteresis = <2000>; 227 type = "passive"; 228}; 229 230&cpu_little2_alert0 { 231 temperature = <90000>; 232 hysteresis = <2000>; 233 type = "passive"; 234}; 235 236&cpu_little3_alert0 { 237 temperature = <90000>; 238 hysteresis = <2000>; 239 type = "passive"; 240}; 241 242&cpu_big0_alert0 { 243 temperature = <90000>; 244 hysteresis = <2000>; 245 type = "passive"; 246}; 247 248&cpu_big1_alert0 { 249 temperature = <90000>; 250 hysteresis = <2000>; 251 type = "passive"; 252}; 253 254&disp_dsi0 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 status = "okay"; 258 259 dsi_panel: panel@0 { 260 /* Compatible string for different panels can be found in each device dts */ 261 reg = <0>; 262 enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&mipi_dsi_pins>; 265 266 backlight = <&backlight_lcd0>; 267 avdd-supply = <&ppvar_mipi_disp_avdd>; 268 avee-supply = <&ppvar_mipi_disp_avee>; 269 pp1800-supply = <&mt6359_vm18_ldo_reg>; 270 rotation = <270>; 271 272 status = "okay"; 273 274 port { 275 dsi_panel_in: endpoint { 276 remote-endpoint = <&dsi_out>; 277 }; 278 }; 279 }; 280 281 port { 282 dsi_out: endpoint { 283 remote-endpoint = <&dsi_panel_in>; 284 }; 285 }; 286}; 287 288&disp_pwm0 { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&disp_pwm0_pins>; 291 status = "okay"; 292}; 293 294&disp_pwm1 { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&disp_pwm1_pins>; 297}; 298 299&dp_intf1 { 300 status = "okay"; 301 302 port { 303 dp_intf1_out: endpoint { 304 remote-endpoint = <&dptx_in>; 305 }; 306 }; 307}; 308 309&dp_tx { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&dp_tx_hpd>; 312 #sound-dai-cells = <0>; 313 status = "okay"; 314 315 ports { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319 port@0 { 320 reg = <0>; 321 dptx_in: endpoint { 322 remote-endpoint = <&dp_intf1_out>; 323 }; 324 }; 325 326 port@1 { 327 reg = <1>; 328 dptx_out: endpoint { 329 data-lanes = <0 1 2 3>; 330 }; 331 }; 332 }; 333}; 334 335&gpu { 336 mali-supply = <&mt6359_vproc2_buck_reg>; 337 status = "okay"; 338}; 339 340&i2c0 { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&i2c0_pins>; 343 clock-frequency = <400000>; 344 status = "okay"; 345}; 346 347&i2c1 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&i2c1_pins>; 350 clock-frequency = <400000>; 351 status = "okay"; 352 353 tpm@50 { 354 compatible = "google,cr50"; 355 reg = <0x50>; 356 interrupts-extended = <&pio 0 IRQ_TYPE_EDGE_RISING>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&gsc_int>; 359 }; 360}; 361 362&i2c2 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&i2c2_pins>; 365 clock-frequency = <400000>; 366 status = "okay"; 367}; 368 369&i2c3 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&i2c3_pins>; 372 clock-frequency = <400000>; 373 status = "okay"; 374}; 375 376&i2c4 { 377 pinctrl-names = "default"; 378 pinctrl-0 = <&i2c4_pins>; 379 clock-frequency = <400000>; 380 status = "okay"; 381}; 382 383&i2c5 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&i2c5_pins>; 386 clock-frequency = <400000>; 387 status = "okay"; 388}; 389 390&i2c6 { 391 pinctrl-names = "default"; 392 pinctrl-0 = <&i2c6_pins>; 393 clock-frequency = <400000>; 394 status = "okay"; 395}; 396 397&mfg0 { 398 domain-supply = <&mt6359_vproc2_buck_reg>; 399}; 400 401&mfg1 { 402 domain-supply = <&mt6359_vsram_others_ldo_reg>; 403}; 404 405&mipi_tx_config0 { 406 status = "okay"; 407}; 408 409&mmc0 { 410 bus-width = <8>; 411 cap-mmc-highspeed; 412 cap-mmc-hw-reset; 413 hs400-ds-delay = <0x1481b>; 414 max-frequency = <200000000>; 415 mmc-hs200-1_8v; 416 mmc-hs400-1_8v; 417 mmc-hs400-enhanced-strobe; 418 no-sd; 419 no-sdio; 420 non-removable; 421 pinctrl-names = "default", "state_uhs"; 422 pinctrl-0 = <&mmc0_pins_default>; 423 pinctrl-1 = <&mmc0_pins_uhs>; 424 supports-cqe; 425 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 426 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 427 status = "okay"; 428}; 429 430&mt6359codec { 431 mediatek,dmic-mode = <1>; /* one-wire */ 432 mediatek,mic-type-0 = <2>; /* DMIC */ 433 mediatek,mic-type-2 = <2>; /* DMIC */ 434}; 435 436&mt6359_vcore_buck_reg { 437 regulator-always-on; 438}; 439 440&mt6359_vgpu11_buck_reg { 441 regulator-always-on; 442}; 443 444&mt6359_vgpu11_sshub_buck_reg { 445 regulator-min-microvolt = <550000>; 446 regulator-max-microvolt = <550000>; 447 regulator-always-on; 448}; 449 450&mt6359_vio28_ldo_reg { 451 /delete-property/ regulator-always-on; 452}; 453 454&mt6359_vm18_ldo_reg { 455 /delete-property/ regulator-always-on; 456}; 457 458&mt6359_vmodem_buck_reg { 459 regulator-min-microvolt = <775000>; 460 regulator-max-microvolt = <775000>; 461}; 462 463&mt6359_vpa_buck_reg { 464 regulator-max-microvolt = <3100000>; 465}; 466 467&mt6359_vproc2_buck_reg { 468 /* 469 * Called "ppvar_dvdd_gpu" in the schematic. Renamed to 470 * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements. 471 */ 472 regulator-name = "ppvar_dvdd_vgpu"; 473 regulator-min-microvolt = <550000>; 474 regulator-max-microvolt = <800000>; 475 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 476 regulator-coupled-max-spread = <6250>; 477}; 478 479&mt6359_vpu_buck_reg { 480 regulator-always-on; 481}; 482 483&mt6359_vrf12_ldo_reg { 484 regulator-always-on; 485}; 486 487&mt6359_vsram_md_ldo_reg { 488 regulator-min-microvolt = <800000>; 489 regulator-max-microvolt = <800000>; 490}; 491 492&mt6359_vsram_others_ldo_reg { 493 regulator-name = "pp0850_dvdd_sram_gpu"; 494 regulator-min-microvolt = <750000>; 495 regulator-max-microvolt = <800000>; 496 regulator-coupled-with = <&mt6359_vproc2_buck_reg>; 497 regulator-coupled-max-spread = <6250>; 498}; 499 500&mt6359_vufs_ldo_reg { 501 regulator-always-on; 502}; 503 504&nor_flash { 505 pinctrl-names = "default"; 506 pinctrl-0 = <&nor_pins>; 507 status = "okay"; 508 509 flash@0 { 510 compatible = "jedec,spi-nor"; 511 reg = <0>; 512 spi-max-frequency = <52000000>; 513 }; 514}; 515 516&pcie { 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pcie_pins>; 519 status = "okay"; 520}; 521 522&pciephy { 523 status = "okay"; 524}; 525 526&pio { 527 gpio-line-names = 528 "gsc_int", 529 "AP_DISP_BKLTEN", 530 "", 531 "EN_PPVAR_MIPI_DISP", 532 "EN_PPVAR_MIPI_DISP_150MA", 533 "TCHSCR_RST_1V8_L", 534 "TCHSRC_REPORT_DISABLE", 535 "", 536 "", 537 "", 538 "", 539 "I2S_SPKR_DATAOUT", 540 "EN_PP3300_WLAN_X", 541 "WIFI_KILL_1V8_L", 542 "BT_KILL_1V8_L", 543 "AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ 544 "", 545 "EDP_HPD_1V8", 546 "WCAM_PWDN_L", 547 "WCAM_RST_L", 548 "UCAM_PWDM_L", 549 "UCAM_RST_L", 550 "WCAM_24M_CLK", 551 "UCAM_24M_CLK", 552 "MT6319_INT", 553 "DISP_RST_1V8_L", 554 "DSIO_DSI_TE", 555 "EN_PP3300_EDP_DISP_X", 556 "TP", 557 "MIPI_BL_PWM_1V8", 558 "EDP_BL_PWM_1V8", 559 "UART_AP_TX_GSC_RX", 560 "UART_GSC_TX_AP_RX", 561 "UART_SSPM_TX_DBGCON_RX", 562 "UART_DBGCON_TX_SSPM_RX", 563 "UART_ADSP_TX_DBGCON_RX", 564 "UART_DBGCON_TX_ADSP_RX", 565 "JTAG_AP_TMS", 566 "JTAG_AP_TCK", 567 "JTAG_AP_TDI", 568 "JTAG_AP_TDO", 569 "JTAG_AP_TRST", 570 "AP_KPCOL0", 571 "TP", 572 "BEEP_ON_OD", 573 "TP", 574 "EC_AP_HPD_OD", 575 "PCIE_WAKE_1V8_ODL", 576 "PCIE_RST_1V8_L", 577 "PCIE_CLKREQ_1V8_ODL", 578 "", 579 "", 580 "", 581 "", 582 "", 583 "AP_I2C_AUD_SCL_1V8", 584 "AP_I2C_AUD_SDA_1V8", 585 "AP_I2C_TPM_SCL_1V8", 586 "AP_I2C_TPM_SDA_1V8", 587 "AP_I2C_TCHSCR_SCL_1V8", 588 "AP_I2C_TCHSCR_SDA_1V8", 589 "AP_I2C_PMIC_SAR_SCL_1V8", 590 "AP_I2C_PMIC_SAR_SDA_1V8", 591 "AP_I2C_EC_HID_KB_SCL_1V8", 592 "AP_I2C_EC_HID_KB_SDA_1V8", 593 "AP_I2C_UCAM_SCL_1V8", 594 "AP_I2C_UCAM_SDA_1V8", 595 "AP_I2C_WCAM_SCL_1V8", 596 "AP_I2C_WCAM_SDA_1V8", 597 "SPI_AP_CS_EC_L", 598 "SPI_AP_CLK_EC", 599 "SPI_AP_DO_EC_DI", 600 "SPI_AP_DI_EC_DO", 601 "TP", 602 "TP", 603 "SPI_AP_CS_TCHSCR_L", 604 "SPI_AP_CLK_TCHSCR", 605 "SPI_AP_DO_TCHSCR_DI", 606 "SPI_AP_DI_TCHSCR_DO", 607 "TP", 608 "TP", 609 "TP", 610 "TP", 611 "", 612 "", 613 "", 614 "TP", 615 "", 616 "SAR_INT_ODL", 617 "", 618 "", 619 "", 620 "PWRAP_SPI_CS_L", 621 "PWRAP_SPI_CK", 622 "PWRAP_SPI_MOSI", 623 "PWRAP_SPI_MISO", 624 "SRCLKENA0", 625 "SRCLKENA1", 626 "SCP_VREQ_VAO", 627 "AP_RTC_CLK32K", 628 "AP_PMIC_WDTRST_L", 629 "AUD_CLK_MOSI", 630 "AUD_SYNC_MOSI", 631 "AUD_DAT_MOSI0", 632 "AUD_DAT_MOSI1", 633 "AUD_DAT_MISO0", 634 "AUD_DAT_MISO1", 635 "SD_CD_ODL", 636 "HP_INT_ODL", 637 "SPKR_INT_ODL", 638 "I2S_HP_DATAIN", 639 "EN_SPKR", 640 "I2S_SPKR_MCLK", 641 "I2S_SPKR_BCLK", 642 "I2S_HP_MCLK", 643 "I2S_HP_BCLK", 644 "I2S_HP_LRCK", 645 "I2S_HP_DATAOUT", 646 "RST_SPKR_L", 647 "I2S_SPKR_LRCK", 648 "I2S_SPKR_DATAIN", 649 "", 650 "", 651 "", 652 "", 653 "SPI_AP_CLK_ROM", 654 "SPI_AP_CS_ROM_L", 655 "SPI_AP_DO_ROM_DI", 656 "SPI_AP_DI_ROM_DO", 657 "TP", 658 "TP", 659 "", 660 "", 661 "", 662 "", 663 "", 664 "", 665 "", 666 "", 667 "EN_PP2800A_UCAM_X", 668 "EN_PP1200_UCAM_X", 669 "EN_PP2800A_WCAM_X", 670 "EN_PP1100_WCAM_X", 671 "TCHSCR_INT_1V8_L", 672 "EN_PP3300_MIPI_TCHSCR_X", 673 "MT7921_PMU_EN_1V8", 674 "EN_PP3300_EDP_TCHSCR_X", 675 "AP_EC_WARM_RST_REQ", 676 "EC_AP_HID_INT_ODL", 677 "EC_AP_INT_ODL", 678 "AP_XHCI_INIT_DONE", 679 "EMMC_DAT7", 680 "EMMC_DAT6", 681 "EMMC_DAT5", 682 "EMMC_DAT4", 683 "EMMC_RST_L", 684 "EMMC_CMD", 685 "EMMC_CLK", 686 "EMMC_DAT3", 687 "EMMC_DAT2", 688 "EMMC_DAT1", 689 "EMMC_DAT0", 690 "EMMC_DSL", 691 "SD_CMD", 692 "SD_CLK", 693 "SD_DAT0", 694 "SD_DAT1", 695 "SD_DAT2", 696 "SD_DAT3", 697 "", 698 "", 699 "USB3_HUB_RST_L", 700 "EC_AP_RSVD0_ODL", 701 "", 702 "", 703 "SPMI_SCL", 704 "SPMI_SDA"; 705 706 adsp_uart_pins: adsp-uart-pins { 707 pins-bus { 708 pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, 709 <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>; 710 }; 711 }; 712 713 aud_etdm_hp_on: aud-etdm-hp-on-pins { 714 pins-bus { 715 pinmux = <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>, 716 <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>, 717 <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>, 718 <PINMUX_GPIO117__FUNC_O_I2SO2_D0>; 719 }; 720 }; 721 722 aud_etdm_hp_off: aud-etdm-hp-off-pins { 723 pins-bus { 724 pinmux = <PINMUX_GPIO110__FUNC_B_GPIO110>, 725 <PINMUX_GPIO115__FUNC_B_GPIO115>, 726 <PINMUX_GPIO116__FUNC_B_GPIO116>, 727 <PINMUX_GPIO117__FUNC_B_GPIO117>; 728 bias-pull-down; 729 input-enable; 730 }; 731 }; 732 733 aud_etdm_spk_on: aud-etdm-spk-on-pins { 734 pins-bus { 735 pinmux = <PINMUX_GPIO11__FUNC_O_I2SO1_D0>, 736 <PINMUX_GPIO113__FUNC_B0_TDMIN_BCK>, 737 <PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK>, 738 <PINMUX_GPIO120__FUNC_I0_TDMIN_DI>; 739 drive-strength = <8>; 740 }; 741 }; 742 743 aud_etdm_spk_off: aud-etdm-spk-off-pins { 744 pins-bus { 745 pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>, 746 <PINMUX_GPIO113__FUNC_B_GPIO113>, 747 <PINMUX_GPIO119__FUNC_B_GPIO119>, 748 <PINMUX_GPIO120__FUNC_B_GPIO120>; 749 bias-pull-down; 750 input-enable; 751 }; 752 }; 753 754 aud_mtkaif_on: aud-mtkaif-on-pins { 755 pins-bus { 756 pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>, 757 <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>, 758 <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>, 759 <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>, 760 <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>, 761 <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>; 762 }; 763 }; 764 765 aud_mtkaif_off: aud-mtkaif-off-pins { 766 pins-bus { 767 pinmux = <PINMUX_GPIO101__FUNC_B_GPIO101>, 768 <PINMUX_GPIO102__FUNC_B_GPIO102>, 769 <PINMUX_GPIO103__FUNC_B_GPIO103>, 770 <PINMUX_GPIO104__FUNC_B_GPIO104>, 771 <PINMUX_GPIO105__FUNC_B_GPIO105>, 772 <PINMUX_GPIO106__FUNC_B_GPIO106>; 773 bias-pull-down; 774 input-enable; 775 }; 776 }; 777 778 cros_ec_int: cros-ec-int-pins { 779 pins-ec-ap-int-odl { 780 pinmux = <PINMUX_GPIO149__FUNC_B_GPIO149>; 781 input-enable; 782 }; 783 }; 784 785 disp_pwm0_pins: disp-pwm0-pins { 786 pins-disp-pwm0 { 787 pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>; 788 output-high; 789 }; 790 }; 791 792 disp_pwm1_pins: disp-pwm1-pins { 793 pins-disp-pwm1 { 794 pinmux = <PINMUX_GPIO30__FUNC_O_DISP_PWM1>; 795 output-high; 796 }; 797 }; 798 799 dp_tx_hpd: dp-tx-hpd-pins { 800 pins-dp-tx-hpd { 801 pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>; 802 }; 803 }; 804 805 gsc_int: gsc-int-pins { 806 pins-gsc-ap-int-odl { 807 pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>; 808 input-enable; 809 }; 810 }; 811 812 i2c0_pins: i2c0-pins { 813 pins-bus { 814 pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, 815 <PINMUX_GPIO55__FUNC_B1_SCL0>; 816 }; 817 }; 818 819 i2c1_pins: i2c1-pins { 820 pins-bus { 821 pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, 822 <PINMUX_GPIO57__FUNC_B1_SCL1>; 823 }; 824 }; 825 826 i2c2_pins: i2c2-pins { 827 pins-bus { 828 pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, 829 <PINMUX_GPIO59__FUNC_B1_SCL2>; 830 bias-disable; 831 drive-strength = <12>; 832 }; 833 }; 834 835 i2c3_pins: i2c3-pins { 836 pins-bus { 837 pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, 838 <PINMUX_GPIO61__FUNC_B1_SCL3>; 839 }; 840 }; 841 842 i2c4_pins: i2c4-pins { 843 pins-bus { 844 pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>, 845 <PINMUX_GPIO63__FUNC_B1_SCL4>; 846 }; 847 }; 848 849 i2c5_pins: i2c5-pins { 850 pins-bus { 851 pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>, 852 <PINMUX_GPIO65__FUNC_B1_SCL5>; 853 }; 854 }; 855 856 i2c6_pins: i2c6-pins { 857 pins-bus { 858 pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>, 859 <PINMUX_GPIO67__FUNC_B1_SCL6>; 860 }; 861 }; 862 863 mipi_disp_avdd_en: mipi-disp-avdd-en-pins { 864 pins-en-ppvar-mipi-disp { 865 pinmux = <PINMUX_GPIO3__FUNC_B_GPIO3>; 866 output-low; 867 }; 868 }; 869 870 mipi_disp_avee_en: mipi-disp-avee-en-pins { 871 pins-en-ppvar-mipi-disp-150ma { 872 pinmux = <PINMUX_GPIO4__FUNC_B_GPIO4>; 873 output-low; 874 }; 875 }; 876 877 mipi_dsi_pins: mipi-dsi-pins { 878 pins-bus { 879 pinmux = <PINMUX_GPIO1__FUNC_B_GPIO1>, 880 <PINMUX_GPIO25__FUNC_B_GPIO25>; 881 output-low; 882 }; 883 }; 884 885 mmc0_pins_default: mmc0-default-pins { 886 pins-bus { 887 pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, 888 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, 889 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, 890 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, 891 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, 892 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, 893 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, 894 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, 895 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; 896 input-enable; 897 drive-strength = <6>; 898 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 899 }; 900 901 pins-clk { 902 pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; 903 drive-strength = <6>; 904 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 905 }; 906 907 pins-rst { 908 pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; 909 drive-strength = <6>; 910 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 911 }; 912 }; 913 914 mmc0_pins_uhs: mmc0-uhs-pins { 915 pins-bus { 916 pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, 917 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, 918 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, 919 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, 920 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, 921 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, 922 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, 923 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, 924 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; 925 input-enable; 926 drive-strength = <8>; 927 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 928 }; 929 930 pins-clk { 931 pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; 932 drive-strength = <8>; 933 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 934 }; 935 936 pins-ds { 937 pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; 938 drive-strength = <8>; 939 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 940 }; 941 942 pins-rst { 943 pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; 944 drive-strength = <8>; 945 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 946 }; 947 }; 948 949 nor_pins: nor-default-pins { 950 pins-clk { 951 pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>, 952 <PINMUX_GPIO125__FUNC_O_SPINOR_CK>, 953 <PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>; 954 bias-pull-down; 955 }; 956 957 pins-cs { 958 pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>; 959 bias-pull-up; 960 }; 961 }; 962 963 pcie_pins: pcie-default-pins { 964 pins-bus { 965 pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, 966 <PINMUX_GPIO48__FUNC_O_PERSTN>, 967 <PINMUX_GPIO49__FUNC_B1_CLKREQN>; 968 }; 969 }; 970 971 spi0_pins: spi0-pins { 972 pins-bus { 973 pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, 974 <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>, 975 <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>, 976 <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>; 977 bias-disable; 978 }; 979 }; 980 981 spi1_pins_default: spi1-default-pins { 982 pins-bus { 983 pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, 984 <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, 985 <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>, 986 <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; 987 bias-disable; 988 }; 989 }; 990 991 spi1_pins_sleep: spi1-sleep-pins { 992 pins-bus { 993 pinmux = <PINMUX_GPIO75__FUNC_B_GPIO75>, 994 <PINMUX_GPIO76__FUNC_B_GPIO76>, 995 <PINMUX_GPIO77__FUNC_B_GPIO77>, 996 <PINMUX_GPIO78__FUNC_B_GPIO78>; 997 bias-pull-down; 998 input-enable; 999 }; 1000 }; 1001 1002 spi2_pins: spi2-pins { 1003 pins-bus { 1004 pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>, 1005 <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>, 1006 <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>, 1007 <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>; 1008 bias-disable; 1009 }; 1010 }; 1011 1012 uart0_pins: uart0-pins { 1013 pins-bus { 1014 pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, 1015 <PINMUX_GPIO32__FUNC_I1_URXD0>; 1016 bias-pull-up; 1017 }; 1018 }; 1019 1020 wlan_en: wlan-en-pins { 1021 pins-en-pp3300-wlan { 1022 pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>; 1023 output-low; 1024 }; 1025 }; 1026}; 1027 1028&pmic { 1029 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 1030}; 1031 1032&sound { 1033 pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", 1034 "aud_etdm_spk_on", "aud_etdm_spk_off", 1035 "aud_mtkaif_on", "aud_mtkaif_off"; 1036 pinctrl-0 = <&aud_etdm_hp_on>; 1037 pinctrl-1 = <&aud_etdm_hp_off>; 1038 pinctrl-2 = <&aud_etdm_spk_on>; 1039 pinctrl-3 = <&aud_etdm_spk_off>; 1040 pinctrl-4 = <&aud_mtkaif_on>; 1041 pinctrl-5 = <&aud_mtkaif_off>; 1042 mediatek,adsp = <&adsp>; 1043 /* The audio-routing is defined in each board dts */ 1044 1045 status = "okay"; 1046}; 1047 1048&spi0 { 1049 pinctrl-names = "default"; 1050 pinctrl-0 = <&spi0_pins>; 1051 status = "okay"; 1052 1053 cros_ec: ec@0 { 1054 compatible = "google,cros-ec-spi"; 1055 reg = <0>; 1056 interrupts-extended = <&pio 149 IRQ_TYPE_LEVEL_LOW>; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&cros_ec_int>; 1059 spi-max-frequency = <3000000>; 1060 1061 i2c_tunnel: i2c-tunnel { 1062 compatible = "google,cros-ec-i2c-tunnel"; 1063 google,remote-bus = <1>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 }; 1067 1068 cbas { 1069 compatible = "google,cros-cbas"; 1070 }; 1071 }; 1072}; 1073 1074&spi1 { 1075 pinctrl-names = "default", "sleep"; 1076 pinctrl-0 = <&spi1_pins_default>; 1077 pinctrl-1 = <&spi1_pins_sleep>; 1078 status = "okay"; 1079}; 1080 1081&spi2 { 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&spi2_pins>; 1084 status = "okay"; 1085}; 1086 1087&uart0 { 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&uart0_pins>; 1090 status = "okay"; 1091}; 1092 1093&u3phy0 { 1094 status = "okay"; 1095}; 1096 1097&u3phy1 { 1098 status = "okay"; 1099}; 1100 1101&u3phy2 { 1102 status = "okay"; 1103}; 1104 1105/* USB detachable base */ 1106&xhci0 { 1107 /* controlled by EC */ 1108 vbus-supply = <&pp3300_z1>; 1109 status = "okay"; 1110}; 1111 1112/* USB3 hub */ 1113&xhci1 { 1114 vusb33-supply = <&pp3300_s3>; 1115 vbus-supply = <&pp5000_usb_vbus>; 1116 status = "okay"; 1117}; 1118 1119/* USB BT */ 1120&xhci2 { 1121 /* no power supply since MT7921's power is controlled by PCIe */ 1122 /* MT7921's USB BT has issues with USB2 LPM */ 1123 usb2-lpm-disable; 1124 status = "okay"; 1125}; 1126 1127#include <arm/cros-ec-keyboard.dtsi> 1128 1129&keyboard_controller { 1130 function-row-physmap = < 1131 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1132 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1133 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1134 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1135 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1136 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1137 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1138 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1139 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1140 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1141 >; 1142 1143 linux,keymap = < 1144 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1145 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1146 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1147 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1148 MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN) 1149 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP) 1150 MATRIX_KEY(0x01, 0x04, KEY_MICMUTE) 1151 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1152 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1153 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1154 CROS_STD_MAIN_KEYMAP 1155 >; 1156}; 1157