1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5/dts-v1/; 6#include "mt8186.dtsi" 7#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/input/gpio-keys.h> 11#include <dt-bindings/regulator/mediatek,mt6397-regulator.h> 12 13/ { 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c5 = &i2c5; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 /* The size should be filled in by the bootloader. */ 32 reg = <0 0x40000000 0 0>; 33 }; 34 35 backlight_lcd0: backlight-lcd0 { 36 compatible = "pwm-backlight"; 37 pwms = <&pwm0 0 500000>; 38 power-supply = <&ppvar_sys>; 39 enable-gpios = <&pio 152 0>; 40 brightness-levels = <0 1023>; 41 num-interpolated-steps = <1023>; 42 default-brightness-level = <576>; 43 }; 44 45 bt-sco { 46 compatible = "linux,bt-sco"; 47 #sound-dai-cells = <0>; 48 }; 49 50 dmic-codec { 51 compatible = "dmic-codec"; 52 #sound-dai-cells = <0>; 53 num-channels = <2>; 54 wakeup-delay-ms = <50>; 55 }; 56 57 gpio_keys: gpio-keys { 58 compatible = "gpio-keys"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pen_eject>; 61 62 pen_insert: pen-insert-switch { 63 label = "Pen Insert"; 64 /* Insert = low, eject = high */ 65 gpios = <&pio 18 GPIO_ACTIVE_LOW>; 66 wakeup-event-action = <EV_ACT_DEASSERTED>; 67 wakeup-source; 68 linux,code = <SW_PEN_INSERTED>; 69 linux,input-type = <EV_SW>; 70 }; 71 }; 72 73 pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx { 74 compatible = "regulator-fixed"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&en_pp1800_dpbrdg>; 77 gpios = <&pio 39 GPIO_ACTIVE_HIGH>; 78 regulator-name = "pp1800_dpbrdg_dx"; 79 enable-active-high; 80 vin-supply = <&mt6366_vio18_reg>; 81 }; 82 83 pp3300_disp_x: regulator-pp3300-disp-x { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&edp_panel_fixed_pins>; 87 gpios = <&pio 153 GPIO_ACTIVE_HIGH>; 88 regulator-name = "pp3300_disp_x"; 89 enable-active-high; 90 regulator-boot-on; 91 vin-supply = <&pp3300_z2>; 92 }; 93 94 /* system wide LDO 3.3V power rail */ 95 pp3300_z5: regulator-pp3300-ldo-z5 { 96 compatible = "regulator-fixed"; 97 regulator-name = "pp3300_ldo_z5"; 98 regulator-always-on; 99 regulator-boot-on; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 vin-supply = <&ppvar_sys>; 103 }; 104 105 /* separately switched 3.3V power rail */ 106 pp3300_s3: regulator-pp3300-s3 { 107 compatible = "regulator-fixed"; 108 regulator-name = "pp3300_s3"; 109 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 110 regulator-always-on; 111 regulator-boot-on; 112 vin-supply = <&pp3300_z2>; 113 }; 114 115 /* system wide 3.3V power rail */ 116 pp3300_z2: regulator-pp3300-z2 { 117 compatible = "regulator-fixed"; 118 regulator-name = "pp3300_z2"; 119 /* EN pin tied to pp4200_z2, which is controlled by EC */ 120 regulator-always-on; 121 regulator-boot-on; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <&ppvar_sys>; 125 }; 126 127 /* system wide 4.2V power rail */ 128 pp4200_z2: regulator-pp4200-z2 { 129 compatible = "regulator-fixed"; 130 regulator-name = "pp4200_z2"; 131 /* controlled by EC */ 132 regulator-always-on; 133 regulator-boot-on; 134 regulator-min-microvolt = <4200000>; 135 regulator-max-microvolt = <4200000>; 136 vin-supply = <&ppvar_sys>; 137 }; 138 139 /* system wide switching 5.0V power rail */ 140 pp5000_z2: regulator-pp5000-z2 { 141 compatible = "regulator-fixed"; 142 regulator-name = "pp5000_z2"; 143 /* controlled by EC */ 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 vin-supply = <&ppvar_sys>; 149 }; 150 151 /* system wide semi-regulated power rail from battery or USB */ 152 ppvar_sys: regulator-ppvar-sys { 153 compatible = "regulator-fixed"; 154 regulator-name = "ppvar_sys"; 155 regulator-always-on; 156 regulator-boot-on; 157 }; 158 159 reserved_memory: reserved-memory { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 ranges; 163 164 adsp_dma_mem: memory@61000000 { 165 compatible = "shared-dma-pool"; 166 reg = <0 0x61000000 0 0x100000>; 167 no-map; 168 }; 169 170 adsp_mem: memory@60000000 { 171 compatible = "shared-dma-pool"; 172 reg = <0 0x60000000 0 0x1000000>; 173 no-map; 174 }; 175 176 scp_mem: memory@50000000 { 177 compatible = "shared-dma-pool"; 178 reg = <0 0x50000000 0 0x10a0000>; 179 no-map; 180 }; 181 }; 182 183 sound: sound { 184 compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound"; 185 pinctrl-names = "aud_clk_mosi_off", 186 "aud_clk_mosi_on", 187 "aud_clk_miso_off", 188 "aud_clk_miso_on", 189 "aud_dat_miso_off", 190 "aud_dat_miso_on", 191 "aud_dat_mosi_off", 192 "aud_dat_mosi_on", 193 "aud_gpio_i2s0_off", 194 "aud_gpio_i2s0_on", 195 "aud_gpio_i2s1_off", 196 "aud_gpio_i2s1_on", 197 "aud_gpio_i2s2_off", 198 "aud_gpio_i2s2_on", 199 "aud_gpio_i2s3_off", 200 "aud_gpio_i2s3_on", 201 "aud_gpio_pcm_off", 202 "aud_gpio_pcm_on", 203 "aud_gpio_dmic_sec"; 204 pinctrl-0 = <&aud_clk_mosi_off>; 205 pinctrl-1 = <&aud_clk_mosi_on>; 206 pinctrl-2 = <&aud_clk_miso_off>; 207 pinctrl-3 = <&aud_clk_miso_on>; 208 pinctrl-4 = <&aud_dat_miso_off>; 209 pinctrl-5 = <&aud_dat_miso_on>; 210 pinctrl-6 = <&aud_dat_mosi_off>; 211 pinctrl-7 = <&aud_dat_mosi_on>; 212 pinctrl-8 = <&aud_gpio_i2s0_off>; 213 pinctrl-9 = <&aud_gpio_i2s0_on>; 214 pinctrl-10 = <&aud_gpio_i2s1_off>; 215 pinctrl-11 = <&aud_gpio_i2s1_on>; 216 pinctrl-12 = <&aud_gpio_i2s2_off>; 217 pinctrl-13 = <&aud_gpio_i2s2_on>; 218 pinctrl-14 = <&aud_gpio_i2s3_off>; 219 pinctrl-15 = <&aud_gpio_i2s3_on>; 220 pinctrl-16 = <&aud_gpio_pcm_off>; 221 pinctrl-17 = <&aud_gpio_pcm_on>; 222 pinctrl-18 = <&aud_gpio_dmic_sec>; 223 mediatek,adsp = <&adsp>; 224 mediatek,platform = <&afe>; 225 226 audio-routing = 227 "Headphone", "HPOL", 228 "Headphone", "HPOR", 229 "IN1P", "Headset Mic", 230 "Speakers", "Speaker", 231 "HDMI1", "TX"; 232 233 hs-playback-dai-link { 234 link-name = "I2S0"; 235 dai-format = "i2s"; 236 mediatek,clk-provider = "cpu"; 237 codec { 238 sound-dai = <&rt5682s 0>; 239 }; 240 }; 241 242 hs-capture-dai-link { 243 link-name = "I2S1"; 244 dai-format = "i2s"; 245 mediatek,clk-provider = "cpu"; 246 codec { 247 sound-dai = <&rt5682s 0>; 248 }; 249 }; 250 251 spk-share-dai-link { 252 link-name = "I2S2"; 253 mediatek,clk-provider = "cpu"; 254 }; 255 256 spk-hdmi-playback-dai-link { 257 link-name = "I2S3"; 258 dai-format = "i2s"; 259 mediatek,clk-provider = "cpu"; 260 /* RT1019P and IT6505 connected to the same I2S line */ 261 codec { 262 sound-dai = <&it6505dptx>, <&speaker_codec>; 263 }; 264 }; 265 }; 266 267 speaker_codec: speaker-codec { 268 compatible = "realtek,rt1019p"; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&speaker_codec_pins_default>; 271 #sound-dai-cells = <0>; 272 sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; 273 }; 274 275 usb_p1_vbus: regulator-usb-p1-vbus { 276 compatible = "regulator-fixed"; 277 gpio = <&pio 148 GPIO_ACTIVE_HIGH>; 278 regulator-name = "vbus1"; 279 regulator-min-microvolt = <5000000>; 280 regulator-max-microvolt = <5000000>; 281 enable-active-high; 282 vin-supply = <&pp5000_z2>; 283 }; 284 285 wifi_pwrseq: wifi-pwrseq { 286 compatible = "mmc-pwrseq-simple"; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&wifi_enable_pin>; 289 post-power-on-delay-ms = <50>; 290 reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 291 }; 292 293 wifi_wakeup: wifi-wakeup { 294 compatible = "gpio-keys"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&wifi_wakeup_pin>; 297 298 wowlan-event { 299 label = "Wake on WiFi"; 300 gpios = <&pio 7 GPIO_ACTIVE_LOW>; 301 linux,code = <KEY_WAKEUP>; 302 wakeup-source; 303 }; 304 }; 305}; 306 307&adsp { 308 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 309 status = "okay"; 310}; 311 312&afe { 313 status = "okay"; 314}; 315 316&cci { 317 proc-supply = <&mt6366_vproc12_reg>; 318}; 319 320&cpu0 { 321 proc-supply = <&mt6366_vproc12_reg>; 322}; 323 324&cpu1 { 325 proc-supply = <&mt6366_vproc12_reg>; 326}; 327 328&cpu2 { 329 proc-supply = <&mt6366_vproc12_reg>; 330}; 331 332&cpu3 { 333 proc-supply = <&mt6366_vproc12_reg>; 334}; 335 336&cpu4 { 337 proc-supply = <&mt6366_vproc12_reg>; 338}; 339 340&cpu5 { 341 proc-supply = <&mt6366_vproc12_reg>; 342}; 343 344&cpu6 { 345 proc-supply = <&mt6366_vproc11_reg>; 346}; 347 348&cpu7 { 349 proc-supply = <&mt6366_vproc11_reg>; 350}; 351 352&dpi { 353 pinctrl-names = "default", "sleep"; 354 pinctrl-0 = <&dpi_pins_default>; 355 pinctrl-1 = <&dpi_pins_sleep>; 356 /* TODO Re-enable after DP to Type-C port muxing can be described */ 357 status = "disabled"; 358}; 359 360&dpi_out { 361 remote-endpoint = <&it6505_in>; 362}; 363 364&dsi0 { 365 status = "okay"; 366}; 367 368&gic { 369 mediatek,broken-save-restore-fw; 370}; 371 372&gpu { 373 mali-supply = <&mt6366_vgpu_reg>; 374 status = "okay"; 375}; 376 377&i2c0 { 378 pinctrl-names = "default"; 379 pinctrl-0 = <&i2c0_pins>; 380 status = "okay"; 381}; 382 383&i2c1 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&i2c1_pins>; 386 clock-frequency = <400000>; 387 i2c-scl-internal-delay-ns = <8000>; 388 status = "okay"; 389}; 390 391&i2c2 { 392 pinctrl-names = "default"; 393 /* 394 * Trackpad pin put here to work around second source components 395 * sharing the pinmux in steelix designs. 396 */ 397 pinctrl-0 = <&i2c2_pins>, <&trackpad_pin>; 398 clock-frequency = <400000>; 399 i2c-scl-internal-delay-ns = <10000>; 400 status = "okay"; 401 402 trackpad@15 { 403 compatible = "elan,ekth3000"; 404 reg = <0x15>; 405 interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; 406 vcc-supply = <&pp3300_s3>; 407 wakeup-source; 408 }; 409}; 410 411&i2c3 { 412 pinctrl-names = "default"; 413 pinctrl-0 = <&i2c3_pins>; 414 clock-frequency = <100000>; 415 status = "okay"; 416 417 it6505dptx: dp-bridge@5c { 418 compatible = "ite,it6505"; 419 reg = <0x5c>; 420 interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&it6505_pins>; 423 #sound-dai-cells = <0>; 424 ovdd-supply = <&mt6366_vsim2_reg>; 425 pwr18-supply = <&pp1800_dpbrdg_dx>; 426 reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>; 427 extcon = <&usbc_extcon>; 428 429 ports { 430 #address-cells = <1>; 431 #size-cells = <0>; 432 433 port@0 { 434 reg = <0>; 435 436 it6505_in: endpoint { 437 link-frequencies = /bits/ 64 <150000000>; 438 remote-endpoint = <&dpi_out>; 439 }; 440 }; 441 442 port@1 { 443 reg = <1>; 444 }; 445 }; 446 }; 447}; 448 449&i2c5 { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&i2c5_pins>; 452 status = "okay"; 453 454 rt5682s: codec@1a { 455 compatible = "realtek,rt5682s"; 456 reg = <0x1a>; 457 interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>; 458 #sound-dai-cells = <1>; 459 AVDD-supply = <&mt6366_vio18_reg>; 460 DBVDD-supply = <&mt6366_vio18_reg>; 461 LDO1-IN-supply = <&mt6366_vio18_reg>; 462 MICVDD-supply = <&pp3300_z2>; 463 realtek,jd-src = <1>; 464 }; 465}; 466 467&mfg0 { 468 domain-supply = <&mt6366_vsram_gpu_reg>; 469}; 470 471&mfg1 { 472 domain-supply = <&mt6366_vgpu_reg>; 473}; 474 475&mipi_tx0 { 476 status = "okay"; 477}; 478 479&mmc0 { 480 pinctrl-names = "default", "state_uhs"; 481 pinctrl-0 = <&mmc0_pins_default>; 482 pinctrl-1 = <&mmc0_pins_uhs>; 483 bus-width = <8>; 484 max-frequency = <200000000>; 485 non-removable; 486 cap-mmc-highspeed; 487 mmc-hs200-1_8v; 488 mmc-hs400-1_8v; 489 supports-cqe; 490 no-sd; 491 no-sdio; 492 cap-mmc-hw-reset; 493 hs400-ds-delay = <0x11814>; 494 mediatek,hs400-ds-dly3 = <0x14>; 495 vmmc-supply = <&mt6366_vemc_reg>; 496 vqmmc-supply = <&mt6366_vio18_reg>; 497 status = "okay"; 498}; 499 500&mmc1 { 501 pinctrl-names = "default", "state_uhs", "state_eint"; 502 pinctrl-0 = <&mmc1_pins_default>; 503 pinctrl-1 = <&mmc1_pins_uhs>; 504 pinctrl-2 = <&mmc1_pins_eint>; 505 /delete-property/ interrupts; 506 interrupt-names = "msdc", "sdio_wakeup"; 507 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 508 <&pio 87 IRQ_TYPE_LEVEL_LOW>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 bus-width = <4>; 512 max-frequency = <200000000>; 513 cap-sd-highspeed; 514 sd-uhs-sdr104; 515 sd-uhs-sdr50; 516 keep-power-in-suspend; 517 wakeup-source; 518 cap-sdio-irq; 519 no-mmc; 520 no-sd; 521 non-removable; 522 vmmc-supply = <&pp3300_s3>; 523 vqmmc-supply = <&mt6366_vio18_reg>; 524 mmc-pwrseq = <&wifi_pwrseq>; 525 status = "okay"; 526 527 bluetooth@2 { 528 compatible = "mediatek,mt7921s-bluetooth"; 529 reg = <2>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&bt_pins_reset>; 532 reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>; 533 }; 534}; 535 536&nor_flash { 537 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&nor_pins_default>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 status = "okay"; 543 544 flash@0 { 545 compatible = "jedec,spi-nor"; 546 reg = <0>; 547 spi-max-frequency = <39000000>; 548 }; 549}; 550 551&pio { 552 /* 185 lines */ 553 gpio-line-names = "TP", 554 "TP", 555 "TP", 556 "I2S0_HP_DI", 557 "I2S3_DP_SPKR_DO", 558 "SAR_INT_ODL", 559 "BT_WAKE_AP_ODL", 560 "WIFI_INT_ODL", 561 "DPBRDG_INT_ODL", 562 "EDPBRDG_INT_ODL", 563 "EC_AP_HPD_OD", 564 "TCHPAD_INT_ODL", 565 "TCHSCR_INT_1V8_ODL", 566 "EC_AP_INT_ODL", 567 "EC_IN_RW_ODL", 568 "GSC_AP_INT_ODL", 569 /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ 570 "AP_FLASH_WP_L", 571 "HP_INT_ODL", 572 "PEN_EJECT_OD", 573 "WCAM_PWDN_L", 574 "WCAM_RST_L", 575 "UCAM_SEN_EN", 576 "UCAM_RST_L", 577 "LTE_RESET_L", 578 "LTE_SAR_DETECT_L", 579 "I2S2_DP_SPK_MCK", 580 "I2S2_DP_SPKR_BCK", 581 "I2S2_DP_SPKR_LRCK", 582 "I2S2_DP_SPKR_DI (TP)", 583 "EN_PP1000_EDPBRDG", 584 "EN_PP1800_EDPBRDG", 585 "EN_PP3300_EDPBRDG", 586 "UART_GSC_TX_AP_RX", 587 "UART_AP_TX_GSC_RX", 588 "UART_DBGCON_TX_ADSP_RX", 589 "UART_ADSP_TX_DBGCON_RX", 590 "EN_PP1000_DPBRDG", 591 "TCHSCR_REPORT_DISABLE", 592 "EN_PP3300_DPBRDG", 593 "EN_PP1800_DPBRDG", 594 "SPI_AP_CLK_EC", 595 "SPI_AP_CS_EC_L", 596 "SPI_AP_DO_EC_DI", 597 "SPI_AP_DI_EC_DO", 598 "SPI_AP_CLK_GSC", 599 "SPI_AP_CS_GSC_L", 600 "SPI_AP_DO_GSC_DI", 601 "SPI_AP_DI_GSC_DO", 602 "UART_DBGCON_TX_SCP_RX", 603 "UART_SCP_TX_DBGCON_RX", 604 "EN_PP1200_CAM_X", 605 "EN_PP2800A_VCM_X", 606 "EN_PP2800A_UCAM_X", 607 "EN_PP2800A_WCAM_X", 608 "WLAN_MODULE_RST_L", 609 "EN_PP1200_UCAM_X", 610 "I2S1_HP_DO", 611 "I2S1_HP_BCK", 612 "I2S1_HP_LRCK", 613 "I2S1_HP_MCK", 614 "TCHSCR_RST_1V8_L", 615 "SPI_AP_CLK_ROM", 616 "SPI_AP_CS_ROM_L", 617 "SPI_AP_DO_ROM_DI", 618 "SPI_AP_DI_ROM_DO", 619 "NC", 620 "NC", 621 "EMMC_STRB", 622 "EMMC_CLK", 623 "EMMC_CMD", 624 "EMMC_RST_L", 625 "EMMC_DATA0", 626 "EMMC_DATA1", 627 "EMMC_DATA2", 628 "EMMC_DATA3", 629 "EMMC_DATA4", 630 "EMMC_DATA5", 631 "EMMC_DATA6", 632 "EMMC_DATA7", 633 "AP_KPCOL0", 634 "NC", 635 "NC", 636 "NC", 637 "TP", 638 "SDIO_CLK", 639 "SDIO_CMD", 640 "SDIO_DATA0", 641 "SDIO_DATA1", 642 "SDIO_DATA2", 643 "SDIO_DATA3", 644 "NC", 645 "NC", 646 "NC", 647 "NC", 648 "NC", 649 "NC", 650 "EDPBRDG_PWREN", 651 "BL_PWM_1V8", 652 "EDPBRDG_RST_L", 653 "MIPI_DPI_CLK", 654 "MIPI_DPI_VSYNC", 655 "MIPI_DPI_HSYNC", 656 "MIPI_DPI_DE", 657 "MIPI_DPI_D0", 658 "MIPI_DPI_D1", 659 "MIPI_DPI_D2", 660 "MIPI_DPI_D3", 661 "MIPI_DPI_D4", 662 "MIPI_DPI_D5", 663 "MIPI_DPI_D6", 664 "MIPI_DPI_DA7", 665 "MIPI_DPI_D8", 666 "MIPI_DPI_D9", 667 "MIPI_DPI_D10", 668 "MIPI_DPI_D11", 669 "PCM_BT_CLK", 670 "PCM_BT_SYNC", 671 "PCM_BT_DI", 672 "PCM_BT_DO", 673 "JTAG_TMS_TP", 674 "JTAG_TCK_TP", 675 "JTAG_TDI_TP", 676 "JTAG_TDO_TP", 677 "JTAG_TRSTN_TP", 678 "CLK_24M_WCAM", 679 "CLK_24M_UCAM", 680 "UCAM_DET_ODL", 681 "AP_I2C_EDPBRDG_SCL_1V8", 682 "AP_I2C_EDPBRDG_SDA_1V8", 683 "AP_I2C_TCHSCR_SCL_1V8", 684 "AP_I2C_TCHSCR_SDA_1V8", 685 "AP_I2C_TCHPAD_SCL_1V8", 686 "AP_I2C_TCHPAD_SDA_1V8", 687 "AP_I2C_DPBRDG_SCL_1V8", 688 "AP_I2C_DPBRDG_SDA_1V8", 689 "AP_I2C_WLAN_SCL_1V8", 690 "AP_I2C_WLAN_SDA_1V8", 691 "AP_I2C_AUD_SCL_1V8", 692 "AP_I2C_AUD_SDA_1V8", 693 "AP_I2C_TPM_SCL_1V8", 694 "AP_I2C_UCAM_SDA_1V8", 695 "AP_I2C_UCAM_SCL_1V8", 696 "AP_I2C_UCAM_SDA_1V8", 697 "AP_I2C_WCAM_SCL_1V8", 698 "AP_I2C_WCAM_SDA_1V8", 699 "SCP_I2C_SENSOR_SCL_1V8", 700 "SCP_I2C_SENSOR_SDA_1V8", 701 "AP_EC_WARM_RST_REQ", 702 "AP_XHCI_INIT_DONE", 703 "USB3_HUB_RST_L", 704 "EN_SPKR", 705 "BEEP_ON", 706 "AP_EDP_BKLTEN", 707 "EN_PP3300_DISP_X", 708 "EN_PP3300_SDBRDG_X", 709 "BT_KILL_1V8_L", 710 "WIFI_KILL_1V8_L", 711 "PWRAP_SPI0_CSN", 712 "PWRAP_SPI0_CK", 713 "PWRAP_SPI0_MO", 714 "PWRAP_SPI0_MI", 715 "SRCLKENA0", 716 "SRCLKENA1", 717 "SCP_VREQ_VAO", 718 "AP_RTC_CLK32K", 719 "AP_PMIC_WDTRST_L", 720 "AUD_CLK_MOSI", 721 "AUD_SYNC_MOSI", 722 "AUD_DAT_MOSI0", 723 "AUD_DAT_MOSI1", 724 "AUD_CLK_MISO", 725 "AUD_SYNC_MISO", 726 "AUD_DAT_MISO0", 727 "AUD_DAT_MISO1", 728 "NC", 729 "NC", 730 "DPBRDG_PWREN", 731 "DPBRDG_RST_L", 732 "LTE_W_DISABLE_L", 733 "LTE_SAR_DETECT_L", 734 "EN_PP3300_LTE_X", 735 "LTE_PWR_OFF_L", 736 "LTE_RESET_L", 737 "TP", 738 "TP"; 739 740 aud_clk_mosi_off: aud-clk-mosi-off-pins { 741 pins-clk-sync { 742 pinmux = <PINMUX_GPIO166__FUNC_GPIO166>, 743 <PINMUX_GPIO167__FUNC_GPIO167>; 744 input-enable; 745 bias-pull-down; 746 }; 747 }; 748 749 aud_clk_mosi_on: aud-clk-mosi-on-pins { 750 pins-clk-sync { 751 pinmux = <PINMUX_GPIO166__FUNC_AUD_CLK_MOSI>, 752 <PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI>; 753 }; 754 }; 755 756 aud_clk_miso_off: aud-clk-miso-off-pins { 757 pins-clk-sync { 758 pinmux = <PINMUX_GPIO170__FUNC_GPIO170>, 759 <PINMUX_GPIO171__FUNC_GPIO171>; 760 input-enable; 761 bias-pull-down; 762 }; 763 }; 764 765 aud_clk_miso_on: aud-clk-miso-on-pins { 766 pins-clk-sync { 767 pinmux = <PINMUX_GPIO170__FUNC_AUD_CLK_MISO>, 768 <PINMUX_GPIO171__FUNC_AUD_SYNC_MISO>; 769 }; 770 }; 771 772 aud_dat_mosi_off: aud-dat-mosi-off-pins { 773 pins-dat { 774 pinmux = <PINMUX_GPIO168__FUNC_GPIO168>, 775 <PINMUX_GPIO169__FUNC_GPIO169>; 776 input-enable; 777 bias-pull-down; 778 }; 779 }; 780 781 aud_dat_mosi_on: aud-dat-mosi-on-pins { 782 pins-dat { 783 pinmux = <PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0>, 784 <PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1>; 785 }; 786 }; 787 788 aud_dat_miso_off: aud-dat-miso-off-pins { 789 pins-dat { 790 pinmux = <PINMUX_GPIO172__FUNC_GPIO172>, 791 <PINMUX_GPIO173__FUNC_GPIO173>; 792 input-enable; 793 bias-pull-down; 794 }; 795 }; 796 797 aud_dat_miso_on: aud-dat-miso-on-pins { 798 pins-dat { 799 pinmux = <PINMUX_GPIO172__FUNC_AUD_DAT_MISO0>, 800 <PINMUX_GPIO173__FUNC_AUD_DAT_MISO1>; 801 input-schmitt-enable; 802 bias-disable; 803 }; 804 }; 805 806 aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins { 807 pins-sdata { 808 pinmux = <PINMUX_GPIO3__FUNC_GPIO3>; 809 }; 810 }; 811 812 aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins { 813 pins-sdata { 814 pinmux = <PINMUX_GPIO3__FUNC_I2S0_DI>; 815 }; 816 }; 817 818 aud_gpio_i2s1_off: aud-gpio-i2s-off-pins { 819 pins-clk-sdata { 820 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>, 821 <PINMUX_GPIO57__FUNC_GPIO57>, 822 <PINMUX_GPIO58__FUNC_GPIO58>, 823 <PINMUX_GPIO59__FUNC_GPIO59>; 824 output-low; 825 }; 826 }; 827 828 aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins { 829 pins-clk-sdata { 830 pinmux = <PINMUX_GPIO56__FUNC_I2S1_DO>, 831 <PINMUX_GPIO57__FUNC_I2S1_BCK>, 832 <PINMUX_GPIO58__FUNC_I2S1_LRCK>, 833 <PINMUX_GPIO59__FUNC_I2S1_MCK>; 834 }; 835 }; 836 837 aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins { 838 pins-cmd-dat { 839 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>, 840 <PINMUX_GPIO27__FUNC_GPIO27>; 841 output-low; 842 }; 843 }; 844 845 aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins { 846 pins-clk { 847 pinmux = <PINMUX_GPIO26__FUNC_I2S2_BCK>, 848 <PINMUX_GPIO27__FUNC_I2S2_LRCK>; 849 drive-strength = <4>; 850 }; 851 }; 852 853 aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins { 854 pins-sdata { 855 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 856 output-low; 857 }; 858 }; 859 860 aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins { 861 pins-sdata { 862 pinmux = <PINMUX_GPIO4__FUNC_I2S3_DO>; 863 drive-strength = <4>; 864 }; 865 }; 866 867 aud_gpio_pcm_off: aud-gpio-pcm-off-pins { 868 pins-clk-sdata { 869 pinmux = <PINMUX_GPIO115__FUNC_GPIO115>, 870 <PINMUX_GPIO116__FUNC_GPIO116>, 871 <PINMUX_GPIO117__FUNC_GPIO117>, 872 <PINMUX_GPIO118__FUNC_GPIO118>; 873 output-low; 874 }; 875 }; 876 877 aud_gpio_pcm_on: aud-gpio-pcm-on-pins { 878 pins-clk-sdata { 879 pinmux = <PINMUX_GPIO115__FUNC_PCM_CLK>, 880 <PINMUX_GPIO116__FUNC_PCM_SYNC>, 881 <PINMUX_GPIO117__FUNC_PCM_DI>, 882 <PINMUX_GPIO118__FUNC_PCM_DO>; 883 }; 884 }; 885 886 aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins { 887 pins { 888 pinmux = <PINMUX_GPIO23__FUNC_GPIO23>; 889 output-low; 890 }; 891 }; 892 893 bt_pins_reset: bt-reset-pins { 894 pins-bt-reset { 895 pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; 896 output-high; 897 }; 898 }; 899 900 dpi_pins_sleep: dpi-sleep-pins { 901 pins-cmd-dat { 902 pinmux = <PINMUX_GPIO103__FUNC_GPIO103>, 903 <PINMUX_GPIO104__FUNC_GPIO104>, 904 <PINMUX_GPIO105__FUNC_GPIO105>, 905 <PINMUX_GPIO106__FUNC_GPIO106>, 906 <PINMUX_GPIO107__FUNC_GPIO107>, 907 <PINMUX_GPIO108__FUNC_GPIO108>, 908 <PINMUX_GPIO109__FUNC_GPIO109>, 909 <PINMUX_GPIO110__FUNC_GPIO110>, 910 <PINMUX_GPIO111__FUNC_GPIO111>, 911 <PINMUX_GPIO112__FUNC_GPIO112>, 912 <PINMUX_GPIO113__FUNC_GPIO113>, 913 <PINMUX_GPIO114__FUNC_GPIO114>, 914 <PINMUX_GPIO101__FUNC_GPIO101>, 915 <PINMUX_GPIO100__FUNC_GPIO100>, 916 <PINMUX_GPIO102__FUNC_GPIO102>, 917 <PINMUX_GPIO99__FUNC_GPIO99>; 918 drive-strength = <10>; 919 output-low; 920 }; 921 }; 922 923 dpi_pins_default: dpi-default-pins { 924 pins-cmd-dat { 925 pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>, 926 <PINMUX_GPIO104__FUNC_DPI_DATA1>, 927 <PINMUX_GPIO105__FUNC_DPI_DATA2>, 928 <PINMUX_GPIO106__FUNC_DPI_DATA3>, 929 <PINMUX_GPIO107__FUNC_DPI_DATA4>, 930 <PINMUX_GPIO108__FUNC_DPI_DATA5>, 931 <PINMUX_GPIO109__FUNC_DPI_DATA6>, 932 <PINMUX_GPIO110__FUNC_DPI_DATA7>, 933 <PINMUX_GPIO111__FUNC_DPI_DATA8>, 934 <PINMUX_GPIO112__FUNC_DPI_DATA9>, 935 <PINMUX_GPIO113__FUNC_DPI_DATA10>, 936 <PINMUX_GPIO114__FUNC_DPI_DATA11>, 937 <PINMUX_GPIO101__FUNC_DPI_HSYNC>, 938 <PINMUX_GPIO100__FUNC_DPI_VSYNC>, 939 <PINMUX_GPIO102__FUNC_DPI_DE>, 940 <PINMUX_GPIO99__FUNC_DPI_PCLK>; 941 drive-strength = <10>; 942 }; 943 }; 944 945 ec_ap_int: cros-ec-int-pins { 946 pins-ec-ap-int-odl { 947 pinmux = <PINMUX_GPIO13__FUNC_GPIO13>; 948 input-enable; 949 }; 950 }; 951 952 edp_panel_fixed_pins: edp-panel-fixed-pins { 953 pins-vreg-en { 954 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 955 output-high; 956 }; 957 }; 958 959 en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins { 960 pins-vreg-en { 961 pinmux = <PINMUX_GPIO39__FUNC_GPIO39>; 962 output-low; 963 }; 964 }; 965 966 gsc_int: gsc-int-pins { 967 pins-gsc-ap-int-odl { 968 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 969 input-enable; 970 }; 971 }; 972 973 i2c0_pins: i2c0-pins { 974 pins-bus { 975 pinmux = <PINMUX_GPIO128__FUNC_SDA0>, 976 <PINMUX_GPIO127__FUNC_SCL0>; 977 bias-disable; 978 drive-strength = <4>; 979 input-enable; 980 }; 981 }; 982 983 i2c1_pins: i2c1-pins { 984 pins-bus { 985 pinmux = <PINMUX_GPIO130__FUNC_SDA1>, 986 <PINMUX_GPIO129__FUNC_SCL1>; 987 bias-disable; 988 drive-strength = <4>; 989 input-enable; 990 }; 991 }; 992 993 i2c2_pins: i2c2-pins { 994 pins-bus { 995 pinmux = <PINMUX_GPIO132__FUNC_SDA2>, 996 <PINMUX_GPIO131__FUNC_SCL2>; 997 bias-disable; 998 drive-strength = <4>; 999 input-enable; 1000 }; 1001 }; 1002 1003 i2c3_pins: i2c3-pins { 1004 pins-bus { 1005 pinmux = <PINMUX_GPIO134__FUNC_SDA3>, 1006 <PINMUX_GPIO133__FUNC_SCL3>; 1007 bias-disable; 1008 drive-strength = <4>; 1009 input-enable; 1010 }; 1011 }; 1012 1013 i2c5_pins: i2c5-pins { 1014 pins-bus { 1015 pinmux = <PINMUX_GPIO138__FUNC_SDA5>, 1016 <PINMUX_GPIO137__FUNC_SCL5>; 1017 bias-disable; 1018 drive-strength = <4>; 1019 input-enable; 1020 }; 1021 }; 1022 1023 it6505_pins: it6505-pins { 1024 pins-hpd { 1025 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>; 1026 input-enable; 1027 bias-pull-up; 1028 }; 1029 1030 pins-int { 1031 pinmux = <PINMUX_GPIO8__FUNC_GPIO8>; 1032 input-enable; 1033 bias-pull-up; 1034 }; 1035 1036 pins-reset { 1037 pinmux = <PINMUX_GPIO177__FUNC_GPIO177>; 1038 output-low; 1039 bias-pull-up; 1040 }; 1041 }; 1042 1043 mmc0_pins_default: mmc0-default-pins { 1044 pins-clk { 1045 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1046 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1047 }; 1048 1049 pins-cmd-dat { 1050 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1051 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1052 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1053 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1054 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1055 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1056 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1057 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1058 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1059 input-enable; 1060 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1061 }; 1062 1063 pins-rst { 1064 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1065 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1066 }; 1067 }; 1068 1069 mmc0_pins_uhs: mmc0-uhs-pins { 1070 pins-clk { 1071 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1072 drive-strength = <6>; 1073 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1074 }; 1075 1076 pins-cmd-dat { 1077 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1078 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1079 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1080 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1081 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1082 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1083 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1084 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1085 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1086 input-enable; 1087 drive-strength = <6>; 1088 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1089 }; 1090 1091 pins-ds { 1092 pinmux = <PINMUX_GPIO67__FUNC_MSDC0_DSL>; 1093 drive-strength = <6>; 1094 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1095 }; 1096 1097 pins-rst { 1098 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1099 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1100 }; 1101 }; 1102 1103 mmc1_pins_default: mmc1-default-pins { 1104 pins-clk { 1105 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1106 drive-strength = <6>; 1107 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1108 }; 1109 1110 pins-cmd-dat { 1111 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1112 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1113 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1114 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1115 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1116 input-enable; 1117 drive-strength = <6>; 1118 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1119 }; 1120 }; 1121 1122 mmc1_pins_uhs: mmc1-uhs-pins { 1123 pins-clk { 1124 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1125 drive-strength = <6>; 1126 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1127 }; 1128 1129 pins-cmd-dat { 1130 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1131 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1132 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1133 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1134 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1135 input-enable; 1136 drive-strength = <8>; 1137 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1138 }; 1139 }; 1140 1141 mmc1_pins_eint: mmc1-eint-pins { 1142 pins-dat1 { 1143 pinmux = <PINMUX_GPIO87__FUNC_GPIO87>; 1144 input-enable; 1145 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1146 }; 1147 }; 1148 1149 nor_pins_default: nor-default-pins { 1150 pins-clk-dat { 1151 pinmux = <PINMUX_GPIO63__FUNC_SPINOR_IO0>, 1152 <PINMUX_GPIO61__FUNC_SPINOR_CK>, 1153 <PINMUX_GPIO64__FUNC_SPINOR_IO1>; 1154 drive-strength = <6>; 1155 bias-pull-down; 1156 }; 1157 1158 pins-cs-dat { 1159 pinmux = <PINMUX_GPIO62__FUNC_SPINOR_CS>, 1160 <PINMUX_GPIO65__FUNC_SPINOR_IO2>, 1161 <PINMUX_GPIO66__FUNC_SPINOR_IO3>; 1162 drive-strength = <6>; 1163 bias-pull-up; 1164 }; 1165 }; 1166 1167 pen_eject: pen-eject-pins { 1168 pins { 1169 pinmux = <PINMUX_GPIO18__FUNC_GPIO18>; 1170 input-enable; 1171 /* External pull-up. */ 1172 bias-disable; 1173 }; 1174 }; 1175 1176 pwm0_pin: disp-pwm-pins { 1177 pins { 1178 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM>; 1179 output-high; 1180 }; 1181 }; 1182 1183 speaker_codec_pins_default: speaker-codec-default-pins { 1184 pins-sdb { 1185 pinmux = <PINMUX_GPIO150__FUNC_GPIO150>; 1186 output-low; 1187 }; 1188 }; 1189 1190 scp_pins: scp-default-pins { 1191 pins-scp-uart { 1192 pinmux = <PINMUX_GPIO48__FUNC_TP_URXD2_AO>, 1193 <PINMUX_GPIO49__FUNC_TP_UTXD2_AO>; 1194 }; 1195 }; 1196 1197 spi1_pins: spi1-pins { 1198 pins-bus { 1199 pinmux = <PINMUX_GPIO40__FUNC_SPI1_CLK_A>, 1200 <PINMUX_GPIO41__FUNC_SPI1_CSB_A>, 1201 <PINMUX_GPIO42__FUNC_SPI1_MO_A>, 1202 <PINMUX_GPIO43__FUNC_SPI1_MI_A>; 1203 bias-disable; 1204 input-enable; 1205 }; 1206 }; 1207 1208 spi2_pins: spi2-pins { 1209 pins-bus { 1210 pinmux = <PINMUX_GPIO44__FUNC_SPI2_CLK_A>, 1211 <PINMUX_GPIO45__FUNC_GPIO45>, 1212 <PINMUX_GPIO46__FUNC_SPI2_MO_A>, 1213 <PINMUX_GPIO47__FUNC_SPI2_MI_A>; 1214 bias-disable; 1215 input-enable; 1216 }; 1217 }; 1218 1219 spmi_pins: spmi-pins { 1220 pins-bus { 1221 pinmux = <PINMUX_GPIO183__FUNC_SPMI_SCL>, 1222 <PINMUX_GPIO184__FUNC_SPMI_SDA>; 1223 }; 1224 }; 1225 1226 touchscreen_pins: touchscreen-pins { 1227 pins-irq { 1228 pinmux = <PINMUX_GPIO12__FUNC_GPIO12>; 1229 input-enable; 1230 bias-pull-up; 1231 }; 1232 1233 pins-reset { 1234 pinmux = <PINMUX_GPIO60__FUNC_GPIO60>; 1235 output-high; 1236 }; 1237 1238 pins-report-sw { 1239 pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; 1240 output-low; 1241 }; 1242 }; 1243 1244 trackpad_pin: trackpad-default-pins { 1245 pins-int-n { 1246 pinmux = <PINMUX_GPIO11__FUNC_GPIO11>; 1247 input-enable; 1248 bias-disable; /* pulled externally */ 1249 }; 1250 }; 1251 1252 wifi_enable_pin: wifi-enable-pins { 1253 pins-wifi-enable { 1254 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 1255 }; 1256 }; 1257 1258 wifi_wakeup_pin: wifi-wakeup-pins { 1259 pins-wifi-wakeup { 1260 pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; 1261 input-enable; 1262 }; 1263 }; 1264}; 1265 1266&pwm0 { 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&pwm0_pin>; 1269 status = "okay"; 1270}; 1271 1272&pwrap { 1273 pmic { 1274 compatible = "mediatek,mt6366", "mediatek,mt6358"; 1275 interrupt-controller; 1276 interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>; 1277 #interrupt-cells = <2>; 1278 1279 mt6366codec: audio-codec { 1280 compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound"; 1281 Avdd-supply = <&mt6366_vaud28_reg>; 1282 mediatek,dmic-mode = <1>; /* one-wire */ 1283 }; 1284 1285 mt6366_regulators: regulators { 1286 compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; 1287 vsys-ldo1-supply = <&pp4200_z2>; 1288 vsys-ldo2-supply = <&pp4200_z2>; 1289 vsys-ldo3-supply = <&pp4200_z2>; 1290 vsys-vcore-supply = <&pp4200_z2>; 1291 vsys-vdram1-supply = <&pp4200_z2>; 1292 vsys-vgpu-supply = <&pp4200_z2>; 1293 vsys-vmodem-supply = <&pp4200_z2>; 1294 vsys-vpa-supply = <&pp4200_z2>; 1295 vsys-vproc11-supply = <&pp4200_z2>; 1296 vsys-vproc12-supply = <&pp4200_z2>; 1297 vsys-vs1-supply = <&pp4200_z2>; 1298 vsys-vs2-supply = <&pp4200_z2>; 1299 vs1-ldo1-supply = <&mt6366_vs1_reg>; 1300 vs2-ldo1-supply = <&mt6366_vdram1_reg>; 1301 vs2-ldo2-supply = <&mt6366_vs2_reg>; 1302 vs2-ldo3-supply = <&mt6366_vs2_reg>; 1303 1304 vcore { 1305 regulator-name = "pp0750_dvdd_core"; 1306 regulator-min-microvolt = <550000>; 1307 regulator-max-microvolt = <800000>; 1308 regulator-ramp-delay = <6250>; 1309 regulator-enable-ramp-delay = <200>; 1310 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1311 MT6397_BUCK_MODE_FORCE_PWM>; 1312 regulator-always-on; 1313 }; 1314 1315 mt6366_vdram1_reg: vdram1 { 1316 regulator-name = "pp1125_emi_vdd2"; 1317 regulator-min-microvolt = <1125000>; 1318 regulator-max-microvolt = <1125000>; 1319 regulator-ramp-delay = <12500>; 1320 regulator-enable-ramp-delay = <0>; 1321 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1322 MT6397_BUCK_MODE_FORCE_PWM>; 1323 regulator-always-on; 1324 }; 1325 1326 mt6366_vgpu_reg: vgpu { 1327 /* 1328 * Called "ppvar_dvdd_gpu" in the schematic. 1329 * Called "ppvar_dvdd_vgpu" here to match 1330 * regulator coupling requirements. 1331 */ 1332 regulator-name = "ppvar_dvdd_vgpu"; 1333 regulator-min-microvolt = <500000>; 1334 regulator-max-microvolt = <950000>; 1335 regulator-ramp-delay = <6250>; 1336 regulator-enable-ramp-delay = <200>; 1337 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1338 MT6397_BUCK_MODE_FORCE_PWM>; 1339 regulator-coupled-with = <&mt6366_vsram_gpu_reg>; 1340 regulator-coupled-max-spread = <100000>; 1341 }; 1342 1343 mt6366_vproc11_reg: vproc11 { 1344 regulator-name = "ppvar_dvdd_proc_bc_mt6366"; 1345 regulator-min-microvolt = <600000>; 1346 regulator-max-microvolt = <1200000>; 1347 regulator-ramp-delay = <6250>; 1348 regulator-enable-ramp-delay = <200>; 1349 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1350 MT6397_BUCK_MODE_FORCE_PWM>; 1351 regulator-always-on; 1352 }; 1353 1354 mt6366_vproc12_reg: vproc12 { 1355 regulator-name = "ppvar_dvdd_proc_lc"; 1356 regulator-min-microvolt = <600000>; 1357 regulator-max-microvolt = <1200000>; 1358 regulator-ramp-delay = <6250>; 1359 regulator-enable-ramp-delay = <200>; 1360 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1361 MT6397_BUCK_MODE_FORCE_PWM>; 1362 regulator-always-on; 1363 }; 1364 1365 mt6366_vs1_reg: vs1 { 1366 regulator-name = "pp2000_vs1"; 1367 regulator-min-microvolt = <2000000>; 1368 regulator-max-microvolt = <2000000>; 1369 regulator-ramp-delay = <12500>; 1370 regulator-enable-ramp-delay = <0>; 1371 regulator-always-on; 1372 }; 1373 1374 mt6366_vs2_reg: vs2 { 1375 regulator-name = "pp1350_vs2"; 1376 regulator-min-microvolt = <1350000>; 1377 regulator-max-microvolt = <1350000>; 1378 regulator-ramp-delay = <12500>; 1379 regulator-enable-ramp-delay = <0>; 1380 regulator-always-on; 1381 }; 1382 1383 va12 { 1384 regulator-name = "pp1200_va12"; 1385 regulator-min-microvolt = <1200000>; 1386 regulator-max-microvolt = <1200000>; 1387 regulator-enable-ramp-delay = <270>; 1388 regulator-always-on; 1389 }; 1390 1391 mt6366_vaud28_reg: vaud28 { 1392 regulator-name = "pp2800_vaud28"; 1393 regulator-min-microvolt = <2800000>; 1394 regulator-max-microvolt = <2800000>; 1395 regulator-enable-ramp-delay = <270>; 1396 }; 1397 1398 mt6366_vaux18_reg: vaux18 { 1399 regulator-name = "pp1840_vaux18"; 1400 regulator-min-microvolt = <1800000>; 1401 regulator-max-microvolt = <1840000>; 1402 regulator-enable-ramp-delay = <270>; 1403 }; 1404 1405 mt6366_vbif28_reg: vbif28 { 1406 regulator-name = "pp2800_vbif28"; 1407 regulator-min-microvolt = <2800000>; 1408 regulator-max-microvolt = <2800000>; 1409 regulator-enable-ramp-delay = <270>; 1410 }; 1411 1412 mt6366_vcn18_reg: vcn18 { 1413 regulator-name = "pp1800_vcn18_x"; 1414 regulator-min-microvolt = <1800000>; 1415 regulator-max-microvolt = <1800000>; 1416 regulator-enable-ramp-delay = <270>; 1417 }; 1418 1419 mt6366_vcn28_reg: vcn28 { 1420 regulator-name = "pp2800_vcn28_x"; 1421 regulator-min-microvolt = <2800000>; 1422 regulator-max-microvolt = <2800000>; 1423 regulator-enable-ramp-delay = <270>; 1424 }; 1425 1426 mt6366_vefuse_reg: vefuse { 1427 regulator-name = "pp1800_vefuse"; 1428 regulator-min-microvolt = <1800000>; 1429 regulator-max-microvolt = <1800000>; 1430 regulator-enable-ramp-delay = <270>; 1431 }; 1432 1433 mt6366_vfe28_reg: vfe28 { 1434 regulator-name = "pp2800_vfe28_x"; 1435 regulator-min-microvolt = <2800000>; 1436 regulator-max-microvolt = <2800000>; 1437 regulator-enable-ramp-delay = <270>; 1438 }; 1439 1440 mt6366_vemc_reg: vemc { 1441 regulator-name = "pp3000_vemc"; 1442 regulator-min-microvolt = <3000000>; 1443 regulator-max-microvolt = <3000000>; 1444 regulator-enable-ramp-delay = <60>; 1445 }; 1446 1447 mt6366_vibr_reg: vibr { 1448 regulator-name = "pp2800_vibr_x"; 1449 regulator-min-microvolt = <2800000>; 1450 regulator-max-microvolt = <2800000>; 1451 regulator-enable-ramp-delay = <60>; 1452 }; 1453 1454 mt6366_vio18_reg: vio18 { 1455 regulator-name = "pp1800_vio18_s3"; 1456 regulator-min-microvolt = <1800000>; 1457 regulator-max-microvolt = <1800000>; 1458 regulator-enable-ramp-delay = <2700>; 1459 regulator-always-on; 1460 }; 1461 1462 mt6366_vio28_reg: vio28 { 1463 regulator-name = "pp2800_vio28_x"; 1464 regulator-min-microvolt = <2800000>; 1465 regulator-max-microvolt = <2800000>; 1466 regulator-enable-ramp-delay = <270>; 1467 }; 1468 1469 mt6366_vm18_reg: vm18 { 1470 regulator-name = "pp1800_emi_vdd1"; 1471 regulator-min-microvolt = <1800000>; 1472 regulator-max-microvolt = <1840000>; 1473 regulator-enable-ramp-delay = <325>; 1474 regulator-always-on; 1475 }; 1476 1477 mt6366_vmc_reg: vmc { 1478 regulator-name = "pp3000_vmc"; 1479 regulator-min-microvolt = <3000000>; 1480 regulator-max-microvolt = <3000000>; 1481 regulator-enable-ramp-delay = <60>; 1482 }; 1483 1484 mt6366_vmddr_reg: vmddr { 1485 regulator-name = "pm0750_emi_vmddr"; 1486 regulator-min-microvolt = <700000>; 1487 regulator-max-microvolt = <750000>; 1488 regulator-enable-ramp-delay = <325>; 1489 regulator-always-on; 1490 }; 1491 1492 mt6366_vmch_reg: vmch { 1493 regulator-name = "pp3000_vmch"; 1494 regulator-min-microvolt = <3000000>; 1495 regulator-max-microvolt = <3000000>; 1496 regulator-enable-ramp-delay = <60>; 1497 }; 1498 1499 mt6366_vcn33_reg: vcn33 { 1500 regulator-name = "pp3300_vcn33_x"; 1501 regulator-min-microvolt = <3300000>; 1502 regulator-max-microvolt = <3300000>; 1503 regulator-enable-ramp-delay = <270>; 1504 }; 1505 1506 vdram2 { 1507 regulator-name = "pp0600_emi_vddq"; 1508 regulator-min-microvolt = <600000>; 1509 regulator-max-microvolt = <600000>; 1510 regulator-enable-ramp-delay = <3300>; 1511 regulator-always-on; 1512 }; 1513 1514 mt6366_vrf12_reg: vrf12 { 1515 regulator-name = "pp1200_vrf12_x"; 1516 regulator-min-microvolt = <1200000>; 1517 regulator-max-microvolt = <1200000>; 1518 regulator-enable-ramp-delay = <120>; 1519 }; 1520 1521 mt6366_vrf18_reg: vrf18 { 1522 regulator-name = "pp1800_vrf18_x"; 1523 regulator-min-microvolt = <1800000>; 1524 regulator-max-microvolt = <1800000>; 1525 regulator-enable-ramp-delay = <120>; 1526 }; 1527 1528 vsim1 { 1529 regulator-name = "pp1860_vsim1_x"; 1530 regulator-min-microvolt = <1800000>; 1531 regulator-max-microvolt = <1860000>; 1532 regulator-enable-ramp-delay = <540>; 1533 }; 1534 1535 mt6366_vsim2_reg: vsim2 { 1536 regulator-name = "pp2760_vsim2_x"; 1537 regulator-min-microvolt = <2700000>; 1538 regulator-max-microvolt = <2760000>; 1539 regulator-enable-ramp-delay = <540>; 1540 }; 1541 1542 mt6366_vsram_gpu_reg: vsram-gpu { 1543 regulator-name = "pp0900_dvdd_sram_gpu"; 1544 regulator-min-microvolt = <850000>; 1545 regulator-max-microvolt = <1050000>; 1546 regulator-ramp-delay = <6250>; 1547 regulator-enable-ramp-delay = <240>; 1548 regulator-coupled-with = <&mt6366_vgpu_reg>; 1549 regulator-coupled-max-spread = <100000>; 1550 }; 1551 1552 mt6366_vsram_others_reg: vsram-others { 1553 regulator-name = "pp0900_dvdd_sram_core"; 1554 regulator-min-microvolt = <900000>; 1555 regulator-max-microvolt = <900000>; 1556 regulator-ramp-delay = <6250>; 1557 regulator-enable-ramp-delay = <240>; 1558 regulator-always-on; 1559 }; 1560 1561 mt6366_vsram_proc11_reg: vsram-proc11 { 1562 regulator-name = "pp0900_dvdd_sram_bc"; 1563 regulator-min-microvolt = <850000>; 1564 regulator-max-microvolt = <1120000>; 1565 regulator-ramp-delay = <6250>; 1566 regulator-enable-ramp-delay = <240>; 1567 regulator-always-on; 1568 }; 1569 1570 mt6366_vsram_proc12_reg: vsram-proc12 { 1571 regulator-name = "pp0900_dvdd_sram_lc"; 1572 regulator-min-microvolt = <850000>; 1573 regulator-max-microvolt = <1120000>; 1574 regulator-ramp-delay = <6250>; 1575 regulator-enable-ramp-delay = <240>; 1576 regulator-always-on; 1577 }; 1578 1579 vusb { 1580 regulator-name = "pp3070_vusb"; 1581 regulator-min-microvolt = <3000000>; 1582 regulator-max-microvolt = <3070000>; 1583 regulator-enable-ramp-delay = <270>; 1584 regulator-always-on; 1585 }; 1586 1587 vxo22 { 1588 regulator-name = "pp2240_vxo22"; 1589 regulator-min-microvolt = <2200000>; 1590 regulator-max-microvolt = <2240000>; 1591 regulator-enable-ramp-delay = <120>; 1592 /* Feeds DCXO internally */ 1593 regulator-always-on; 1594 }; 1595 }; 1596 1597 rtc { 1598 compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc"; 1599 }; 1600 }; 1601}; 1602 1603&scp { 1604 pinctrl-names = "default"; 1605 pinctrl-0 = <&scp_pins>; 1606 firmware-name = "mediatek/mt8186/scp.img"; 1607 memory-region = <&scp_mem>; 1608 status = "okay"; 1609 1610 cros-ec-rpmsg { 1611 compatible = "google,cros-ec-rpmsg"; 1612 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1613 }; 1614}; 1615 1616&spi1 { 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&spi1_pins>; 1619 mediatek,pad-select = <0>; 1620 status = "okay"; 1621 1622 cros_ec: ec@0 { 1623 compatible = "google,cros-ec-spi"; 1624 reg = <0>; 1625 interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>; 1626 pinctrl-names = "default"; 1627 pinctrl-0 = <&ec_ap_int>; 1628 spi-max-frequency = <1000000>; 1629 1630 i2c_tunnel: i2c-tunnel { 1631 compatible = "google,cros-ec-i2c-tunnel"; 1632 google,remote-bus = <1>; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 }; 1636 1637 typec { 1638 compatible = "google,cros-ec-typec"; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 1642 usb_c0: connector@0 { 1643 compatible = "usb-c-connector"; 1644 reg = <0>; 1645 label = "left"; 1646 power-role = "dual"; 1647 data-role = "host"; 1648 try-power-role = "source"; 1649 }; 1650 1651 usb_c1: connector@1 { 1652 compatible = "usb-c-connector"; 1653 reg = <1>; 1654 label = "right"; 1655 power-role = "dual"; 1656 data-role = "host"; 1657 try-power-role = "source"; 1658 }; 1659 }; 1660 1661 usbc_extcon: extcon0 { 1662 compatible = "google,extcon-usbc-cros-ec"; 1663 google,usb-port-id = <0>; 1664 }; 1665 }; 1666}; 1667 1668&spi2 { 1669 pinctrl-names = "default"; 1670 pinctrl-0 = <&spi2_pins>; 1671 cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>; 1672 mediatek,pad-select = <0>; 1673 status = "okay"; 1674 1675 tpm@0 { 1676 compatible = "google,cr50"; 1677 reg = <0>; 1678 interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>; 1679 pinctrl-names = "default"; 1680 pinctrl-0 = <&gsc_int>; 1681 spi-max-frequency = <1000000>; 1682 }; 1683}; 1684 1685&ssusb0 { 1686 status = "okay"; 1687}; 1688 1689&ssusb1 { 1690 status = "okay"; 1691}; 1692 1693&u3phy0 { 1694 status = "okay"; 1695}; 1696 1697&u3phy1 { 1698 status = "okay"; 1699}; 1700 1701&uart0 { 1702 status = "okay"; 1703}; 1704 1705&usb_host0 { 1706 vbus-supply = <&pp3300_s3>; 1707 status = "okay"; 1708}; 1709 1710&usb_host1 { 1711 vbus-supply = <&usb_p1_vbus>; 1712 status = "okay"; 1713}; 1714 1715&watchdog { 1716 mediatek,reset-by-toprgu; 1717}; 1718 1719#include <arm/cros-ec-keyboard.dtsi> 1720#include <arm/cros-ec-sbs.dtsi> 1721