1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <[email protected]>
5 *	   Erin Lo <[email protected]>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include "mt8183.dtsi"
11#include "mt6358.dtsi"
12
13/ {
14	aliases {
15		serial0 = &uart0;
16		mmc0 = &mmc0;
17		mmc1 = &mmc1;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	backlight_lcd0: backlight_lcd0 {
25		compatible = "pwm-backlight";
26		pwms = <&pwm0 0 500000>;
27		power-supply = <&reg_vsys>;
28		enable-gpios = <&pio 176 0>;
29		brightness-levels = <0 1023>;
30		num-interpolated-steps = <1023>;
31		default-brightness-level = <576>;
32		status = "okay";
33	};
34
35	memory@40000000 {
36		device_type = "memory";
37		reg = <0 0x40000000 0 0x80000000>;
38	};
39
40	clk32k: oscillator1 {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <32768>;
44		clock-output-names = "clk32k";
45	};
46
47	it6505_pp18_reg: regulator0 {
48		compatible = "regulator-fixed";
49		regulator-name = "it6505_pp18";
50		gpio = <&pio 178 0>;
51		enable-active-high;
52		vin-supply = <&pp1800_alw>;
53	};
54
55	pp1800_alw: regulator5 {
56		compatible = "regulator-fixed";
57		regulator-name = "pp1800_alw";
58		regulator-always-on;
59		regulator-boot-on;
60		regulator-min-microvolt = <1800000>;
61		regulator-max-microvolt = <1800000>;
62		vin-supply = <&reg_vsys>;
63	};
64
65	pp3300_alw: regulator6 {
66		compatible = "regulator-fixed";
67		regulator-name = "pp3300_alw";
68		regulator-always-on;
69		regulator-boot-on;
70		regulator-min-microvolt = <3300000>;
71		regulator-max-microvolt = <3300000>;
72		vin-supply = <&reg_vsys>;
73	};
74
75	/* system wide semi-regulated power rail from charger */
76	reg_vsys: regulator-vsys {
77		compatible = "regulator-fixed";
78		regulator-name = "vsys";
79		regulator-always-on;
80		regulator-boot-on;
81	};
82
83	reserved_memory: reserved-memory {
84		#address-cells = <2>;
85		#size-cells = <2>;
86		ranges;
87
88		scp_mem_reserved: memory@50000000 {
89			compatible = "shared-dma-pool";
90			reg = <0 0x50000000 0 0x2900000>;
91			no-map;
92		};
93	};
94
95	sound: mt8183-sound {
96		mediatek,platform = <&afe>;
97		pinctrl-names = "default",
98				"aud_tdm_out_on",
99				"aud_tdm_out_off";
100		pinctrl-0 = <&aud_pins_default>;
101		pinctrl-1 = <&aud_pins_tdm_out_on>;
102		pinctrl-2 = <&aud_pins_tdm_out_off>;
103		status = "okay";
104	};
105
106	btsco: bt-sco {
107		compatible = "linux,bt-sco";
108	};
109
110	wifi_pwrseq: wifi-pwrseq {
111		compatible = "mmc-pwrseq-simple";
112		pinctrl-names = "default";
113		pinctrl-0 = <&wifi_pins_pwrseq>;
114
115		/* Toggle WIFI_ENABLE to reset the chip. */
116		reset-gpios = <&pio 119 1>;
117	};
118
119	wifi_wakeup: wifi-wakeup {
120		compatible = "gpio-keys";
121		pinctrl-names = "default";
122		pinctrl-0 = <&wifi_pins_wakeup>;
123
124		wifi_wakeup_event: event-wowlan {
125			label = "Wake on WiFi";
126			gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
127			linux,code = <KEY_WAKEUP>;
128			wakeup-source;
129		};
130	};
131
132	tboard_thermistor1: thermal-sensor1 {
133		compatible = "generic-adc-thermal";
134		#thermal-sensor-cells = <0>;
135		io-channels = <&auxadc 0>;
136		io-channel-names = "sensor-channel";
137		temperature-lookup-table = <    (-5000) 1553
138						0 1488
139						5000 1412
140						10000 1326
141						15000 1232
142						20000 1132
143						25000 1029
144						30000 925
145						35000 823
146						40000 726
147						45000 635
148						50000 552
149						55000 478
150						60000 411
151						65000 353
152						70000 303
153						75000 260
154						80000 222
155						85000 190
156						90000 163
157						95000 140
158						100000 121
159						105000 104
160						110000 90
161						115000 78
162						120000 67
163						125000 59>;
164	};
165
166	tboard_thermistor2: thermal-sensor2 {
167		compatible = "generic-adc-thermal";
168		#thermal-sensor-cells = <0>;
169		io-channels = <&auxadc 1>;
170		io-channel-names = "sensor-channel";
171		temperature-lookup-table = <    (-5000) 1553
172						0 1488
173						5000 1412
174						10000 1326
175						15000 1232
176						20000 1132
177						25000 1029
178						30000 925
179						35000 823
180						40000 726
181						45000 635
182						50000 552
183						55000 478
184						60000 411
185						65000 353
186						70000 303
187						75000 260
188						80000 222
189						85000 190
190						90000 163
191						95000 140
192						100000 121
193						105000 104
194						110000 90
195						115000 78
196						120000 67
197						125000 59>;
198	};
199};
200
201&auxadc {
202	status = "okay";
203};
204
205&cci {
206	proc-supply = <&mt6358_vproc12_reg>;
207};
208
209&cpu0 {
210	proc-supply = <&mt6358_vproc12_reg>;
211};
212
213&cpu1 {
214	proc-supply = <&mt6358_vproc12_reg>;
215};
216
217&cpu2 {
218	proc-supply = <&mt6358_vproc12_reg>;
219};
220
221&cpu3 {
222	proc-supply = <&mt6358_vproc12_reg>;
223};
224
225&cpu4 {
226	proc-supply = <&mt6358_vproc11_reg>;
227};
228
229&cpu5 {
230	proc-supply = <&mt6358_vproc11_reg>;
231};
232
233&cpu6 {
234	proc-supply = <&mt6358_vproc11_reg>;
235};
236
237&cpu7 {
238	proc-supply = <&mt6358_vproc11_reg>;
239};
240
241&dsi0 {
242	status = "okay";
243	#address-cells = <1>;
244	#size-cells = <0>;
245	panel: panel@0 {
246		/* compatible will be set in board dts */
247		reg = <0>;
248		enable-gpios = <&pio 45 0>;
249		pinctrl-names = "default";
250		pinctrl-0 = <&panel_pins_default>;
251		avdd-supply = <&ppvarn_lcd>;
252		avee-supply = <&ppvarp_lcd>;
253		pp1800-supply = <&pp1800_lcd>;
254		backlight = <&backlight_lcd0>;
255		rotation = <270>;
256		port {
257			panel_in: endpoint {
258				remote-endpoint = <&dsi_out>;
259			};
260		};
261	};
262
263	ports {
264		port {
265			dsi_out: endpoint {
266				remote-endpoint = <&panel_in>;
267			};
268		};
269	};
270};
271
272&gic {
273	mediatek,broken-save-restore-fw;
274};
275
276&gpu {
277	mali-supply = <&mt6358_vgpu_reg>;
278};
279
280&i2c0 {
281	pinctrl-names = "default";
282	pinctrl-0 = <&i2c0_pins>;
283	status = "okay";
284	clock-frequency = <400000>;
285	#address-cells = <1>;
286	#size-cells = <0>;
287};
288
289&i2c1 {
290	pinctrl-names = "default";
291	pinctrl-0 = <&i2c1_pins>;
292	status = "okay";
293	clock-frequency = <100000>;
294};
295
296&i2c3 {
297	pinctrl-names = "default";
298	pinctrl-0 = <&i2c3_pins>;
299	status = "okay";
300	clock-frequency = <100000>;
301	#address-cells = <1>;
302	#size-cells = <0>;
303};
304
305&i2c5 {
306	pinctrl-names = "default";
307	pinctrl-0 = <&i2c5_pins>;
308	status = "okay";
309	clock-frequency = <100000>;
310	#address-cells = <1>;
311	#size-cells = <0>;
312};
313
314&i2c6 {
315	pinctrl-names = "default";
316	pinctrl-0 = <&i2c6_pins>;
317	status = "okay";
318	clock-frequency = <100000>;
319};
320
321&mipi_tx0 {
322	status = "okay";
323};
324
325&mmc0 {
326	status = "okay";
327	pinctrl-names = "default", "state_uhs";
328	pinctrl-0 = <&mmc0_pins_default>;
329	pinctrl-1 = <&mmc0_pins_uhs>;
330	bus-width = <8>;
331	max-frequency = <200000000>;
332	cap-mmc-highspeed;
333	mmc-hs200-1_8v;
334	mmc-hs400-1_8v;
335	cap-mmc-hw-reset;
336	no-sdio;
337	no-sd;
338	hs400-ds-delay = <0x12814>;
339	vmmc-supply = <&mt6358_vemc_reg>;
340	vqmmc-supply = <&mt6358_vio18_reg>;
341	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
342	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
343	non-removable;
344};
345
346&mmc1 {
347	status = "okay";
348	pinctrl-names = "default", "state_uhs";
349	pinctrl-0 = <&mmc1_pins_default>;
350	pinctrl-1 = <&mmc1_pins_uhs>;
351	vmmc-supply = <&pp3300_alw>;
352	vqmmc-supply = <&pp1800_alw>;
353	mmc-pwrseq = <&wifi_pwrseq>;
354	bus-width = <4>;
355	max-frequency = <200000000>;
356	cap-sd-highspeed;
357	sd-uhs-sdr50;
358	sd-uhs-sdr104;
359	keep-power-in-suspend;
360	wakeup-source;
361	cap-sdio-irq;
362	non-removable;
363	no-mmc;
364	no-sd;
365	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
366	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
367	#address-cells = <1>;
368	#size-cells = <0>;
369
370	qca_wifi: qca-wifi@1 {
371		compatible = "qcom,ath10k";
372		reg = <1>;
373	};
374};
375
376&mt6358_vdram2_reg {
377	regulator-always-on;
378};
379
380&mt6358codec {
381	Avdd-supply = <&mt6358_vaud28_reg>;
382};
383
384&mt6358regulator {
385	vsys-ldo1-supply = <&reg_vsys>;
386	vsys-ldo2-supply = <&reg_vsys>;
387	vsys-ldo3-supply = <&reg_vsys>;
388	vsys-vcore-supply = <&reg_vsys>;
389	vsys-vdram1-supply = <&reg_vsys>;
390	vsys-vgpu-supply = <&reg_vsys>;
391	vsys-vmodem-supply = <&reg_vsys>;
392	vsys-vpa-supply = <&reg_vsys>;
393	vsys-vproc11-supply = <&reg_vsys>;
394	vsys-vproc12-supply = <&reg_vsys>;
395	vsys-vs1-supply = <&reg_vsys>;
396	vsys-vs2-supply = <&reg_vsys>;
397	vs1-ldo1-supply = <&mt6358_vs1_reg>;
398	vs2-ldo1-supply = <&mt6358_vdram1_reg>;
399	vs2-ldo2-supply = <&mt6358_vs2_reg>;
400	vs2-ldo3-supply = <&mt6358_vs2_reg>;
401	vs2-ldo4-supply = <&mt6358_vs2_reg>;
402};
403
404&mt6358_vgpu_reg {
405	regulator-max-microvolt = <900000>;
406
407	regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
408	regulator-coupled-max-spread = <100000>;
409};
410
411&mt6358_vsim1_reg {
412	regulator-min-microvolt = <2700000>;
413	regulator-max-microvolt = <2700000>;
414};
415
416&mt6358_vsim2_reg {
417	regulator-min-microvolt = <2700000>;
418	regulator-max-microvolt = <2700000>;
419};
420
421&mt6358_vsram_gpu_reg {
422	regulator-min-microvolt = <850000>;
423	regulator-max-microvolt = <1000000>;
424
425	regulator-coupled-with = <&mt6358_vgpu_reg>;
426	regulator-coupled-max-spread = <100000>;
427};
428
429&pio {
430	aud_pins_default: audiopins {
431		pins-bus {
432			pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
433				<PINMUX_GPIO98__FUNC_I2S2_BCK>,
434				<PINMUX_GPIO101__FUNC_I2S2_LRCK>,
435				<PINMUX_GPIO102__FUNC_I2S2_DI>,
436				<PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
437				<PINMUX_GPIO89__FUNC_I2S5_BCK>,
438				<PINMUX_GPIO90__FUNC_I2S5_LRCK>,
439				<PINMUX_GPIO91__FUNC_I2S5_DO>,
440				<PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
441				<PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
442				<PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
443				<PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
444				<PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
445				<PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
446				<PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
447				<PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
448				<PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
449		};
450	};
451
452	aud_pins_tdm_out_on: audiotdmouton {
453		pins-bus {
454			pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
455				<PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
456				<PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
457				<PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
458				<PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
459				<PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
460			drive-strength = <6>;
461		};
462	};
463
464	aud_pins_tdm_out_off: audiotdmoutoff {
465		pins-bus {
466			pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
467				<PINMUX_GPIO170__FUNC_GPIO170>,
468				<PINMUX_GPIO171__FUNC_GPIO171>,
469				<PINMUX_GPIO172__FUNC_GPIO172>,
470				<PINMUX_GPIO173__FUNC_GPIO173>,
471				<PINMUX_GPIO10__FUNC_GPIO10>;
472			input-enable;
473			bias-pull-down;
474			drive-strength = <2>;
475		};
476	};
477
478	bt_pins: bt-pins {
479		pins-bt-en {
480			pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
481			output-low;
482		};
483	};
484
485	ec_ap_int_odl: ec-ap-int-odl {
486		pins1 {
487			pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
488			input-enable;
489			bias-pull-up;
490		};
491	};
492
493	h1_int_od_l: h1-int-od-l {
494		pins1 {
495			pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
496			input-enable;
497		};
498	};
499
500	i2c0_pins: i2c0 {
501		pins-bus {
502			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
503				 <PINMUX_GPIO83__FUNC_SCL0>;
504			mediatek,pull-up-adv = <3>;
505		};
506	};
507
508	i2c1_pins: i2c1 {
509		pins-bus {
510			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
511				 <PINMUX_GPIO84__FUNC_SCL1>;
512			mediatek,pull-up-adv = <3>;
513		};
514	};
515
516	i2c2_pins: i2c2 {
517		pins-bus {
518			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
519				 <PINMUX_GPIO104__FUNC_SDA2>;
520			bias-disable;
521		};
522	};
523
524	i2c3_pins: i2c3 {
525		pins-bus {
526			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
527				 <PINMUX_GPIO51__FUNC_SDA3>;
528			mediatek,pull-up-adv = <3>;
529		};
530	};
531
532	i2c4_pins: i2c4 {
533		pins-bus {
534			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
535				 <PINMUX_GPIO106__FUNC_SDA4>;
536			bias-disable;
537		};
538	};
539
540	i2c5_pins: i2c5 {
541		pins-bus {
542			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
543				 <PINMUX_GPIO49__FUNC_SDA5>;
544			mediatek,pull-up-adv = <3>;
545		};
546	};
547
548	i2c6_pins: i2c6 {
549		pins-bus {
550			pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
551				 <PINMUX_GPIO12__FUNC_SDA6>;
552			bias-disable;
553		};
554	};
555
556	mmc0_pins_default: mmc0-pins-default {
557		pins-cmd-dat {
558			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
559				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
560				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
561				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
562				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
563				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
564				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
565				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
566				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
567			input-enable;
568			drive-strength = <MTK_DRIVE_14mA>;
569			mediatek,pull-up-adv = <01>;
570		};
571
572		pins-clk {
573			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
574			drive-strength = <MTK_DRIVE_14mA>;
575			mediatek,pull-down-adv = <10>;
576		};
577
578		pins-rst {
579			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
580			drive-strength = <MTK_DRIVE_14mA>;
581			mediatek,pull-down-adv = <01>;
582		};
583	};
584
585	mmc0_pins_uhs: mmc0-pins-uhs {
586		pins-cmd-dat {
587			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
588				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
589				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
590				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
591				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
592				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
593				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
594				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
595				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
596			input-enable;
597			drive-strength = <MTK_DRIVE_14mA>;
598			mediatek,pull-up-adv = <01>;
599		};
600
601		pins-clk {
602			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
603			drive-strength = <MTK_DRIVE_14mA>;
604			mediatek,pull-down-adv = <10>;
605		};
606
607		pins-ds {
608			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
609			drive-strength = <MTK_DRIVE_14mA>;
610			mediatek,pull-down-adv = <10>;
611		};
612
613		pins-rst {
614			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
615			drive-strength = <MTK_DRIVE_14mA>;
616			mediatek,pull-up-adv = <01>;
617		};
618	};
619
620	mmc1_pins_default: mmc1-pins-default {
621		pins-cmd-dat {
622			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
623				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
624				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
625				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
626				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
627			input-enable;
628			mediatek,pull-up-adv = <10>;
629		};
630
631		pins-clk {
632			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
633			input-enable;
634			mediatek,pull-down-adv = <10>;
635		};
636	};
637
638	mmc1_pins_uhs: mmc1-pins-uhs {
639		pins-cmd-dat {
640			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
641				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
642				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
643				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
644				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
645			drive-strength = <6>;
646			input-enable;
647			mediatek,pull-up-adv = <10>;
648		};
649
650		pins-clk {
651			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
652			drive-strength = <8>;
653			mediatek,pull-down-adv = <10>;
654			input-enable;
655		};
656	};
657
658	panel_pins_default: panel-pins-default {
659		panel-reset {
660			pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
661			output-low;
662			bias-pull-up;
663		};
664	};
665
666	pwm0_pin_default: pwm0-pin-default {
667		pins1 {
668			pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
669			output-high;
670			bias-pull-up;
671		};
672		pins2 {
673			pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
674		};
675	};
676
677	scp_pins: scp {
678		pins-scp-uart {
679			pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
680				 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
681		};
682	};
683
684	spi0_pins: spi0 {
685		pins-spi {
686			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
687				 <PINMUX_GPIO86__FUNC_GPIO86>,
688				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
689				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
690			bias-disable;
691		};
692	};
693
694	spi1_pins: spi1 {
695		pins-spi {
696			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
697				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
698				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
699				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
700			bias-disable;
701		};
702	};
703
704	spi2_pins: spi2 {
705		pins-spi {
706			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
707				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
708				 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
709			bias-disable;
710		};
711		pins-spi-mi {
712			pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
713			mediatek,pull-down-adv = <00>;
714		};
715	};
716
717	spi3_pins: spi3 {
718		pins-spi {
719			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
720				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
721				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
722				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
723			bias-disable;
724		};
725	};
726
727	spi4_pins: spi4 {
728		pins-spi {
729			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
730				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
731				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
732				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
733			bias-disable;
734		};
735	};
736
737	spi5_pins: spi5 {
738		pins-spi {
739			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
740				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
741				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
742				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
743			bias-disable;
744		};
745	};
746
747	uart0_pins_default: uart0-pins-default {
748		pins-rx {
749			pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
750			input-enable;
751			bias-pull-up;
752		};
753		pins-tx {
754			pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
755		};
756	};
757
758	uart1_pins_default: uart1-pins-default {
759		pins-rx {
760			pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
761			input-enable;
762			bias-pull-up;
763		};
764		pins-tx {
765			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
766		};
767		pins-rts {
768			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
769		};
770		pins-cts {
771			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
772			input-enable;
773		};
774	};
775
776	uart1_pins_sleep: uart1-pins-sleep {
777		pins-rx {
778			pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
779			input-enable;
780			bias-pull-up;
781		};
782		pins-tx {
783			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
784		};
785		pins-rts {
786			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
787		};
788		pins-cts {
789			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
790			input-enable;
791		};
792	};
793
794	wifi_pins_pwrseq: wifi-pins-pwrseq {
795		pins-wifi-enable {
796			pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
797			output-low;
798		};
799	};
800
801	wifi_pins_wakeup: wifi-pins-wakeup {
802		pins-wifi-wakeup {
803			pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
804			input-enable;
805		};
806	};
807};
808
809&pmic {
810	interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
811};
812
813&pwm0 {
814	status = "okay";
815	pinctrl-names = "default";
816	pinctrl-0 = <&pwm0_pin_default>;
817};
818
819&scp {
820	status = "okay";
821
822	firmware-name = "mediatek/mt8183/scp.img";
823	pinctrl-names = "default";
824	pinctrl-0 = <&scp_pins>;
825
826	cros-ec-rpmsg {
827		compatible = "google,cros-ec-rpmsg";
828		mediatek,rpmsg-name = "cros-ec-rpmsg";
829	};
830};
831
832&mfg_async {
833	domain-supply = <&mt6358_vsram_gpu_reg>;
834};
835
836&mfg {
837	domain-supply = <&mt6358_vgpu_reg>;
838};
839
840&spi0 {
841	pinctrl-names = "default";
842	pinctrl-0 = <&spi0_pins>;
843	mediatek,pad-select = <0>;
844	status = "okay";
845	cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
846
847	tpm@0 {
848		compatible = "google,cr50";
849		reg = <0>;
850		spi-max-frequency = <1000000>;
851		pinctrl-names = "default";
852		pinctrl-0 = <&h1_int_od_l>;
853		interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>;
854	};
855};
856
857&spi1 {
858	pinctrl-names = "default";
859	pinctrl-0 = <&spi1_pins>;
860	mediatek,pad-select = <0>;
861	status = "okay";
862
863	w25q64dw: flash@0 {
864		compatible = "winbond,w25q64dw", "jedec,spi-nor";
865		reg = <0>;
866		spi-max-frequency = <25000000>;
867	};
868};
869
870&spi2 {
871	pinctrl-names = "default";
872	pinctrl-0 = <&spi2_pins>;
873	mediatek,pad-select = <0>;
874	status = "okay";
875
876	cros_ec: cros-ec@0 {
877		compatible = "google,cros-ec-spi";
878		reg = <0>;
879		spi-max-frequency = <3000000>;
880		interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>;
881		pinctrl-names = "default";
882		pinctrl-0 = <&ec_ap_int_odl>;
883		wakeup-source;
884
885		i2c_tunnel: i2c-tunnel {
886			compatible = "google,cros-ec-i2c-tunnel";
887			google,remote-bus = <1>;
888			#address-cells = <1>;
889			#size-cells = <0>;
890		};
891
892		usbc_extcon: extcon0 {
893			compatible = "google,extcon-usbc-cros-ec";
894			google,usb-port-id = <0>;
895		};
896
897		typec {
898			compatible = "google,cros-ec-typec";
899			#address-cells = <1>;
900			#size-cells = <0>;
901
902			usb_c0: connector@0 {
903				compatible = "usb-c-connector";
904				reg = <0>;
905				power-role = "dual";
906				data-role = "host";
907				try-power-role = "sink";
908			};
909		};
910	};
911};
912
913&spi3 {
914	pinctrl-names = "default";
915	pinctrl-0 = <&spi3_pins>;
916	mediatek,pad-select = <0>;
917	status = "disabled";
918};
919
920&spi4 {
921	pinctrl-names = "default";
922	pinctrl-0 = <&spi4_pins>;
923	mediatek,pad-select = <0>;
924	status = "disabled";
925};
926
927&spi5 {
928	pinctrl-names = "default";
929	pinctrl-0 = <&spi5_pins>;
930	mediatek,pad-select = <0>;
931	status = "disabled";
932};
933
934&ssusb {
935	dr_mode = "host";
936	wakeup-source;
937	vusb33-supply = <&mt6358_vusb_reg>;
938	status = "okay";
939};
940
941&thermal_zones {
942	tboard1-thermal {
943		polling-delay = <1000>; /* milliseconds */
944		polling-delay-passive = <0>; /* milliseconds */
945		thermal-sensors = <&tboard_thermistor1>;
946	};
947
948	tboard2-thermal {
949		polling-delay = <1000>; /* milliseconds */
950		polling-delay-passive = <0>; /* milliseconds */
951		thermal-sensors = <&tboard_thermistor2>;
952	};
953};
954
955&u3phy {
956	status = "okay";
957};
958
959&uart0 {
960	pinctrl-names = "default";
961	pinctrl-0 = <&uart0_pins_default>;
962	status = "okay";
963};
964
965&uart1 {
966	pinctrl-names = "default", "sleep";
967	pinctrl-0 = <&uart1_pins_default>;
968	pinctrl-1 = <&uart1_pins_sleep>;
969	status = "okay";
970	/delete-property/ interrupts;
971	interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
972			      <&pio 121 IRQ_TYPE_EDGE_FALLING>;
973
974	bluetooth: bluetooth {
975		pinctrl-names = "default";
976		pinctrl-0 = <&bt_pins>;
977		status = "okay";
978		compatible = "qcom,qca6174-bt";
979		enable-gpios = <&pio 120 0>;
980		clocks = <&clk32k>;
981		firmware-name = "nvm_00440302_i2s.bin";
982	};
983};
984
985&usb_host {
986	#address-cells = <1>;
987	#size-cells = <0>;
988	vusb33-supply = <&mt6358_vusb_reg>;
989	status = "okay";
990
991	hub@1 {
992		compatible = "usb5e3,610";
993		reg = <1>;
994	};
995};
996
997#include <arm/cros-ec-sbs.dtsi>
998