1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/clock/mediatek,mt7988-clk.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6#include <dt-bindings/pinctrl/mt65xx.h> 7#include <dt-bindings/reset/mediatek,mt7988-resets.h> 8 9/ { 10 compatible = "mediatek,mt7988a"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a73"; 21 reg = <0x0>; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 25 <&topckgen CLK_TOP_XTAL>; 26 clock-names = "cpu", "intermediate"; 27 operating-points-v2 = <&cluster0_opp>; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "arm,cortex-a73"; 32 reg = <0x1>; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 36 <&topckgen CLK_TOP_XTAL>; 37 clock-names = "cpu", "intermediate"; 38 operating-points-v2 = <&cluster0_opp>; 39 }; 40 41 cpu2: cpu@2 { 42 compatible = "arm,cortex-a73"; 43 reg = <0x2>; 44 device_type = "cpu"; 45 enable-method = "psci"; 46 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 47 <&topckgen CLK_TOP_XTAL>; 48 clock-names = "cpu", "intermediate"; 49 operating-points-v2 = <&cluster0_opp>; 50 }; 51 52 cpu3: cpu@3 { 53 compatible = "arm,cortex-a73"; 54 reg = <0x3>; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 58 <&topckgen CLK_TOP_XTAL>; 59 clock-names = "cpu", "intermediate"; 60 operating-points-v2 = <&cluster0_opp>; 61 }; 62 63 cluster0_opp: opp-table-0 { 64 compatible = "operating-points-v2"; 65 opp-shared; 66 67 opp-800000000 { 68 opp-hz = /bits/ 64 <800000000>; 69 opp-microvolt = <850000>; 70 }; 71 opp-1100000000 { 72 opp-hz = /bits/ 64 <1100000000>; 73 opp-microvolt = <850000>; 74 }; 75 opp-1500000000 { 76 opp-hz = /bits/ 64 <1500000000>; 77 opp-microvolt = <850000>; 78 }; 79 opp-1800000000 { 80 opp-hz = /bits/ 64 <1800000000>; 81 opp-microvolt = <900000>; 82 }; 83 }; 84 }; 85 86 oscillator-40m { 87 compatible = "fixed-clock"; 88 clock-frequency = <40000000>; 89 #clock-cells = <0>; 90 clock-output-names = "clkxtal"; 91 }; 92 93 pmu { 94 compatible = "arm,cortex-a73-pmu"; 95 interrupt-parent = <&gic>; 96 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 97 }; 98 99 psci { 100 compatible = "arm,psci-0.2"; 101 method = "smc"; 102 }; 103 104 reserved-memory { 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ 110 secmon@43000000 { 111 reg = <0 0x43000000 0 0x50000>; 112 no-map; 113 }; 114 }; 115 116 soc { 117 compatible = "simple-bus"; 118 ranges; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 122 gic: interrupt-controller@c000000 { 123 compatible = "arm,gic-v3"; 124 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 125 <0 0x0c080000 0 0x200000>, /* GICR */ 126 <0 0x0c400000 0 0x2000>, /* GICC */ 127 <0 0x0c410000 0 0x1000>, /* GICH */ 128 <0 0x0c420000 0 0x2000>; /* GICV */ 129 interrupt-parent = <&gic>; 130 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-controller; 132 #interrupt-cells = <3>; 133 }; 134 135 infracfg: clock-controller@10001000 { 136 compatible = "mediatek,mt7988-infracfg", "syscon"; 137 reg = <0 0x10001000 0 0x1000>; 138 #clock-cells = <1>; 139 #reset-cells = <1>; 140 }; 141 142 topckgen: clock-controller@1001b000 { 143 compatible = "mediatek,mt7988-topckgen", "syscon"; 144 reg = <0 0x1001b000 0 0x1000>; 145 #clock-cells = <1>; 146 }; 147 148 watchdog: watchdog@1001c000 { 149 compatible = "mediatek,mt7988-wdt"; 150 reg = <0 0x1001c000 0 0x1000>; 151 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 152 #reset-cells = <1>; 153 }; 154 155 apmixedsys: clock-controller@1001e000 { 156 compatible = "mediatek,mt7988-apmixedsys"; 157 reg = <0 0x1001e000 0 0x1000>; 158 #clock-cells = <1>; 159 }; 160 161 pio: pinctrl@1001f000 { 162 compatible = "mediatek,mt7988-pinctrl"; 163 reg = <0 0x1001f000 0 0x1000>, 164 <0 0x11c10000 0 0x1000>, 165 <0 0x11d00000 0 0x1000>, 166 <0 0x11d20000 0 0x1000>, 167 <0 0x11e00000 0 0x1000>, 168 <0 0x11f00000 0 0x1000>, 169 <0 0x1000b000 0 0x1000>; 170 reg-names = "gpio", "iocfg_tr", 171 "iocfg_br", "iocfg_rb", 172 "iocfg_lb", "iocfg_tl", "eint"; 173 gpio-controller; 174 #gpio-cells = <2>; 175 gpio-ranges = <&pio 0 0 84>; 176 interrupt-controller; 177 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-parent = <&gic>; 179 #interrupt-cells = <2>; 180 181 pcie0_pins: pcie0-pins { 182 mux { 183 function = "pcie"; 184 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", 185 "pcie_wake_n0_0"; 186 }; 187 }; 188 189 pcie1_pins: pcie1-pins { 190 mux { 191 function = "pcie"; 192 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", 193 "pcie_wake_n1_0"; 194 }; 195 }; 196 197 pcie2_pins: pcie2-pins { 198 mux { 199 function = "pcie"; 200 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", 201 "pcie_wake_n2_0"; 202 }; 203 }; 204 205 pcie3_pins: pcie3-pins { 206 mux { 207 function = "pcie"; 208 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", 209 "pcie_wake_n3_0"; 210 }; 211 }; 212 }; 213 214 pwm: pwm@10048000 { 215 compatible = "mediatek,mt7988-pwm"; 216 reg = <0 0x10048000 0 0x1000>; 217 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, 218 <&infracfg CLK_INFRA_66M_PWM_HCK>, 219 <&infracfg CLK_INFRA_66M_PWM_CK1>, 220 <&infracfg CLK_INFRA_66M_PWM_CK2>, 221 <&infracfg CLK_INFRA_66M_PWM_CK3>, 222 <&infracfg CLK_INFRA_66M_PWM_CK4>, 223 <&infracfg CLK_INFRA_66M_PWM_CK5>, 224 <&infracfg CLK_INFRA_66M_PWM_CK6>, 225 <&infracfg CLK_INFRA_66M_PWM_CK7>, 226 <&infracfg CLK_INFRA_66M_PWM_CK8>; 227 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 228 "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; 229 #pwm-cells = <2>; 230 status = "disabled"; 231 }; 232 233 mcusys: mcusys@100e0000 { 234 compatible = "mediatek,mt7988-mcusys", "syscon"; 235 reg = <0 0x100e0000 0 0x1000>; 236 #clock-cells = <1>; 237 }; 238 239 serial0: serial@11000000 { 240 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 241 reg = <0 0x11000000 0 0x100>; 242 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-names = "uart", "wakeup"; 244 clocks = <&topckgen CLK_TOP_UART_SEL>, 245 <&infracfg CLK_INFRA_52M_UART0_CK>; 246 clock-names = "baud", "bus"; 247 status = "disabled"; 248 }; 249 250 serial@11000100 { 251 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 252 reg = <0 0x11000100 0 0x100>; 253 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 254 interrupt-names = "uart", "wakeup"; 255 clocks = <&topckgen CLK_TOP_UART_SEL>, 256 <&infracfg CLK_INFRA_52M_UART1_CK>; 257 clock-names = "baud", "bus"; 258 status = "disabled"; 259 }; 260 261 serial@11000200 { 262 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 263 reg = <0 0x11000200 0 0x100>; 264 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "uart", "wakeup"; 266 clocks = <&topckgen CLK_TOP_UART_SEL>, 267 <&infracfg CLK_INFRA_52M_UART2_CK>; 268 clock-names = "baud", "bus"; 269 status = "disabled"; 270 }; 271 272 i2c0: i2c@11003000 { 273 compatible = "mediatek,mt7981-i2c"; 274 reg = <0 0x11003000 0 0x1000>, 275 <0 0x10217080 0 0x80>; 276 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 277 clock-div = <1>; 278 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 279 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 280 clock-names = "main", "dma"; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 i2c1: i2c@11004000 { 287 compatible = "mediatek,mt7981-i2c"; 288 reg = <0 0x11004000 0 0x1000>, 289 <0 0x10217100 0 0x80>; 290 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 291 clock-div = <1>; 292 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 293 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 294 clock-names = "main", "dma"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 status = "disabled"; 298 }; 299 300 i2c2: i2c@11005000 { 301 compatible = "mediatek,mt7981-i2c"; 302 reg = <0 0x11005000 0 0x1000>, 303 <0 0x10217180 0 0x80>; 304 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 305 clock-div = <1>; 306 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 307 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 308 clock-names = "main", "dma"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 status = "disabled"; 312 }; 313 314 lvts: lvts@1100a000 { 315 compatible = "mediatek,mt7988-lvts-ap"; 316 #thermal-sensor-cells = <1>; 317 reg = <0 0x1100a000 0 0x1000>; 318 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; 319 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 320 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; 321 nvmem-cells = <&lvts_calibration>; 322 nvmem-cell-names = "lvts-calib-data-1"; 323 }; 324 325 usb@11190000 { 326 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 327 reg = <0 0x11190000 0 0x2e00>, 328 <0 0x11193e00 0 0x0100>; 329 reg-names = "mac", "ippc"; 330 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&infracfg CLK_INFRA_USB_SYS>, 332 <&infracfg CLK_INFRA_USB_REF>, 333 <&infracfg CLK_INFRA_66M_USB_HCK>, 334 <&infracfg CLK_INFRA_133M_USB_HCK>, 335 <&infracfg CLK_INFRA_USB_XHCI>; 336 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 337 status = "disabled"; 338 }; 339 340 ssusb1: usb@11200000 { 341 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 342 reg = <0 0x11200000 0 0x2e00>, 343 <0 0x11203e00 0 0x0100>; 344 reg-names = "mac", "ippc"; 345 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, 347 <&infracfg CLK_INFRA_USB_CK_P1>, 348 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, 349 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, 350 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; 351 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 352 phys = <&tphyu2port0 PHY_TYPE_USB2>, 353 <&tphyu3port0 PHY_TYPE_USB3>; 354 status = "disabled"; 355 }; 356 357 mmc0: mmc@11230000 { 358 compatible = "mediatek,mt7988-mmc"; 359 reg = <0 0x11230000 0 0x1000>, 360 <0 0x11D60000 0 0x1000>; 361 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&infracfg CLK_INFRA_MSDC400>, 363 <&infracfg CLK_INFRA_MSDC2_HCK>, 364 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, 365 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; 366 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, 367 <&topckgen CLK_TOP_EMMC_400M_SEL>; 368 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, 369 <&apmixedsys CLK_APMIXED_MSDCPLL>; 370 clock-names = "source", "hclk", "axi_cg", "ahb_cg"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 status = "disabled"; 374 }; 375 376 pcie2: pcie@11280000 { 377 compatible = "mediatek,mt7986-pcie", 378 "mediatek,mt8192-pcie"; 379 device_type = "pci"; 380 #address-cells = <3>; 381 #size-cells = <2>; 382 reg = <0 0x11280000 0 0x2000>; 383 reg-names = "pcie-mac"; 384 linux,pci-domain = <3>; 385 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 386 bus-range = <0x00 0xff>; 387 ranges = <0x81000000 0x00 0x20000000 0x00 388 0x20000000 0x00 0x00200000>, 389 <0x82000000 0x00 0x20200000 0x00 390 0x20200000 0x00 0x07e00000>; 391 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, 392 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, 393 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, 394 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; 395 clock-names = "pl_250m", "tl_26m", "peri_26m", 396 "top_133m"; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pcie2_pins>; 399 status = "disabled"; 400 401 #interrupt-cells = <1>; 402 interrupt-map-mask = <0 0 0 0x7>; 403 interrupt-map = <0 0 0 1 &pcie_intc2 0>, 404 <0 0 0 2 &pcie_intc2 1>, 405 <0 0 0 3 &pcie_intc2 2>, 406 <0 0 0 4 &pcie_intc2 3>; 407 pcie_intc2: interrupt-controller { 408 #address-cells = <0>; 409 #interrupt-cells = <1>; 410 interrupt-controller; 411 }; 412 }; 413 414 pcie3: pcie@11290000 { 415 compatible = "mediatek,mt7986-pcie", 416 "mediatek,mt8192-pcie"; 417 device_type = "pci"; 418 #address-cells = <3>; 419 #size-cells = <2>; 420 reg = <0 0x11290000 0 0x2000>; 421 reg-names = "pcie-mac"; 422 linux,pci-domain = <2>; 423 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 424 bus-range = <0x00 0xff>; 425 ranges = <0x81000000 0x00 0x28000000 0x00 426 0x28000000 0x00 0x00200000>, 427 <0x82000000 0x00 0x28200000 0x00 428 0x28200000 0x00 0x07e00000>; 429 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, 430 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, 431 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, 432 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; 433 clock-names = "pl_250m", "tl_26m", "peri_26m", 434 "top_133m"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&pcie3_pins>; 437 status = "disabled"; 438 439 #interrupt-cells = <1>; 440 interrupt-map-mask = <0 0 0 0x7>; 441 interrupt-map = <0 0 0 1 &pcie_intc3 0>, 442 <0 0 0 2 &pcie_intc3 1>, 443 <0 0 0 3 &pcie_intc3 2>, 444 <0 0 0 4 &pcie_intc3 3>; 445 pcie_intc3: interrupt-controller { 446 #address-cells = <0>; 447 #interrupt-cells = <1>; 448 interrupt-controller; 449 }; 450 }; 451 452 pcie0: pcie@11300000 { 453 compatible = "mediatek,mt7986-pcie", 454 "mediatek,mt8192-pcie"; 455 device_type = "pci"; 456 #address-cells = <3>; 457 #size-cells = <2>; 458 reg = <0 0x11300000 0 0x2000>; 459 reg-names = "pcie-mac"; 460 linux,pci-domain = <0>; 461 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 462 bus-range = <0x00 0xff>; 463 ranges = <0x81000000 0x00 0x30000000 0x00 464 0x30000000 0x00 0x00200000>, 465 <0x82000000 0x00 0x30200000 0x00 466 0x30200000 0x00 0x07e00000>; 467 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, 468 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, 469 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, 470 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; 471 clock-names = "pl_250m", "tl_26m", "peri_26m", 472 "top_133m"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pcie0_pins>; 475 status = "disabled"; 476 477 #interrupt-cells = <1>; 478 interrupt-map-mask = <0 0 0 0x7>; 479 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 480 <0 0 0 2 &pcie_intc0 1>, 481 <0 0 0 3 &pcie_intc0 2>, 482 <0 0 0 4 &pcie_intc0 3>; 483 pcie_intc0: interrupt-controller { 484 #address-cells = <0>; 485 #interrupt-cells = <1>; 486 interrupt-controller; 487 }; 488 }; 489 490 pcie1: pcie@11310000 { 491 compatible = "mediatek,mt7986-pcie", 492 "mediatek,mt8192-pcie"; 493 device_type = "pci"; 494 #address-cells = <3>; 495 #size-cells = <2>; 496 reg = <0 0x11310000 0 0x2000>; 497 reg-names = "pcie-mac"; 498 linux,pci-domain = <1>; 499 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 500 bus-range = <0x00 0xff>; 501 ranges = <0x81000000 0x00 0x38000000 0x00 502 0x38000000 0x00 0x00200000>, 503 <0x82000000 0x00 0x38200000 0x00 504 0x38200000 0x00 0x07e00000>; 505 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, 506 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, 507 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, 508 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; 509 clock-names = "pl_250m", "tl_26m", "peri_26m", 510 "top_133m"; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pcie1_pins>; 513 status = "disabled"; 514 515 #interrupt-cells = <1>; 516 interrupt-map-mask = <0 0 0 0x7>; 517 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 518 <0 0 0 2 &pcie_intc1 1>, 519 <0 0 0 3 &pcie_intc1 2>, 520 <0 0 0 4 &pcie_intc1 3>; 521 pcie_intc1: interrupt-controller { 522 #address-cells = <0>; 523 #interrupt-cells = <1>; 524 interrupt-controller; 525 }; 526 }; 527 528 tphy: t-phy@11c50000 { 529 compatible = "mediatek,mt7986-tphy", 530 "mediatek,generic-tphy-v2"; 531 #address-cells = <2>; 532 #size-cells = <2>; 533 ranges; 534 status = "disabled"; 535 536 tphyu2port0: usb-phy@11c50000 { 537 reg = <0 0x11c50000 0 0x700>; 538 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; 539 clock-names = "ref"; 540 #phy-cells = <1>; 541 }; 542 543 tphyu3port0: usb-phy@11c50700 { 544 reg = <0 0x11c50700 0 0x900>; 545 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; 546 clock-names = "ref"; 547 #phy-cells = <1>; 548 }; 549 }; 550 551 clock-controller@11f40000 { 552 compatible = "mediatek,mt7988-xfi-pll"; 553 reg = <0 0x11f40000 0 0x1000>; 554 resets = <&watchdog 16>; 555 #clock-cells = <1>; 556 }; 557 558 efuse@11f50000 { 559 compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; 560 reg = <0 0x11f50000 0 0x1000>; 561 #address-cells = <1>; 562 #size-cells = <1>; 563 564 lvts_calibration: calib@918 { 565 reg = <0x918 0x28>; 566 }; 567 }; 568 569 clock-controller@15000000 { 570 compatible = "mediatek,mt7988-ethsys", "syscon"; 571 reg = <0 0x15000000 0 0x1000>; 572 #clock-cells = <1>; 573 #reset-cells = <1>; 574 }; 575 576 clock-controller@15031000 { 577 compatible = "mediatek,mt7988-ethwarp"; 578 reg = <0 0x15031000 0 0x1000>; 579 #clock-cells = <1>; 580 #reset-cells = <1>; 581 }; 582 }; 583 584 thermal-zones { 585 cpu_thermal: cpu-thermal { 586 polling-delay-passive = <1000>; 587 polling-delay = <1000>; 588 thermal-sensors = <&lvts 0>; 589 trips { 590 cpu_trip_crit: crit { 591 temperature = <125000>; 592 hysteresis = <2000>; 593 type = "critical"; 594 }; 595 }; 596 }; 597 }; 598 599 timer { 600 compatible = "arm,armv8-timer"; 601 interrupt-parent = <&gic>; 602 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 603 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 604 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 605 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 606 }; 607}; 608