1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada 8040 Development board platform
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include "armada-8040.dtsi"
10
11/ {
12	model = "Marvell Armada 8040 DB board";
13	compatible = "marvell,armada8040-db", "marvell,armada8040",
14		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	memory@0 {
21		device_type = "memory";
22		reg = <0x0 0x0 0x0 0x80000000>;
23	};
24
25	aliases {
26		ethernet0 = &cp0_eth0;
27		ethernet1 = &cp0_eth2;
28		ethernet2 = &cp1_eth0;
29		ethernet3 = &cp1_eth1;
30		i2c1 = &cp0_i2c0;
31		i2c2 = &cp1_i2c0;
32	};
33
34	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35		compatible = "regulator-fixed";
36		regulator-name = "cp0-usb3h0-vbus";
37		regulator-min-microvolt = <5000000>;
38		regulator-max-microvolt = <5000000>;
39		enable-active-high;
40		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
41	};
42
43	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
44		compatible = "regulator-fixed";
45		regulator-name = "cp0-usb3h1-vbus";
46		regulator-min-microvolt = <5000000>;
47		regulator-max-microvolt = <5000000>;
48		enable-active-high;
49		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
50	};
51
52	cp0_usb3_0_phy: cp0-usb3-0-phy {
53		compatible = "usb-nop-xceiv";
54		vcc-supply = <&cp0_reg_usb3_0_vbus>;
55	};
56
57	cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
58		compatible = "regulator-fixed";
59		regulator-name = "cp1-usb3h0-vbus";
60		regulator-min-microvolt = <5000000>;
61		regulator-max-microvolt = <5000000>;
62		enable-active-high;
63		gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
64	};
65
66	cp1_usb3_0_phy: cp1-usb3-0-phy {
67		compatible = "usb-nop-xceiv";
68		vcc-supply = <&cp1_reg_usb3_0_vbus>;
69	};
70};
71
72&spi0 {
73	status = "okay";
74
75	flash@0 {
76		compatible = "jedec,spi-nor";
77		reg = <0>;
78		spi-max-frequency = <10000000>;
79
80		partitions {
81			compatible = "fixed-partitions";
82			#address-cells = <1>;
83			#size-cells = <1>;
84
85			partition@0 {
86				label = "U-Boot";
87				reg = <0 0x200000>;
88			};
89			partition@400000 {
90				label = "Filesystem";
91				reg = <0x200000 0xce0000>;
92			};
93		};
94	};
95};
96
97/* Accessible over the mini-USB CON9 connector on the main board */
98&uart0 {
99	status = "okay";
100	pinctrl-0 = <&uart0_pins>;
101	pinctrl-names = "default";
102};
103
104/* CON6 on CP0 expansion */
105&cp0_pcie0 {
106	phys = <&cp0_comphy0 0>;
107	phy-names = "cp0-pcie0-x1-phy";
108	status = "okay";
109};
110
111/* CON5 on CP0 expansion */
112&cp0_pcie2 {
113	phys = <&cp0_comphy5 2>;
114	phy-names = "cp0-pcie2-x1-phy";
115	status = "okay";
116};
117
118&cp0_i2c0 {
119	status = "okay";
120	clock-frequency = <100000>;
121
122	/* U31 */
123	expander0: pca9555@21 {
124		compatible = "nxp,pca9555";
125		pinctrl-names = "default";
126		gpio-controller;
127		#gpio-cells = <2>;
128		reg = <0x21>;
129	};
130
131	/* U25 */
132	expander1: pca9555@25 {
133		compatible = "nxp,pca9555";
134		pinctrl-names = "default";
135		gpio-controller;
136		#gpio-cells = <2>;
137		reg = <0x25>;
138	};
139
140};
141
142/* CON4 on CP0 expansion */
143&cp0_sata0 {
144	status = "okay";
145
146	sata-port@0 {
147		phys = <&cp0_comphy1 0>;
148		status = "okay";
149	};
150
151	sata-port@1 {
152		phys = <&cp0_comphy3 1>;
153		status = "okay";
154	};
155};
156
157/* CON9 on CP0 expansion */
158&cp0_utmi {
159	status = "okay";
160};
161
162&cp0_usb3_0 {
163	usb-phy = <&cp0_usb3_0_phy>;
164	phys = <&cp0_utmi0>;
165	phy-names = "utmi";
166	dr_mode = "host";
167	status = "okay";
168};
169
170&cp0_comphy4 {
171	cp0_usbh1_con: connector {
172		compatible = "usb-a-connector";
173		phy-supply = <&cp0_reg_usb3_1_vbus>;
174	};
175};
176
177/* CON10 on CP0 expansion */
178&cp0_usb3_1 {
179	phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
180	phy-names = "usb", "utmi";
181	dr_mode = "host";
182	status = "okay";
183};
184
185&cp0_mdio {
186	status = "okay";
187
188	phy1: ethernet-phy@1 {
189		reg = <1>;
190	};
191};
192
193&cp0_ethernet {
194	status = "okay";
195};
196
197&cp0_eth0 {
198	status = "okay";
199	phy-mode = "10gbase-r";
200
201	fixed-link {
202		speed = <10000>;
203		full-duplex;
204	};
205};
206
207&cp0_eth2 {
208	status = "okay";
209	phy = <&phy1>;
210	phy-mode = "rgmii-id";
211};
212
213/* CON6 on CP1 expansion */
214&cp1_pcie0 {
215	phys = <&cp1_comphy0 0>;
216	phy-names = "cp1-pcie0-x1-phy";
217	status = "okay";
218};
219
220/* CON7 on CP1 expansion */
221&cp1_pcie1 {
222	phys = <&cp1_comphy4 1>;
223	phy-names = "cp1-pcie1-x1-phy";
224	status = "okay";
225};
226
227/* CON5 on CP1 expansion */
228&cp1_pcie2 {
229	phys = <&cp1_comphy5 2>;
230	phy-names = "cp1-pcie2-x1-phy";
231	status = "okay";
232};
233
234&cp1_i2c0 {
235	status = "okay";
236	clock-frequency = <100000>;
237};
238
239&cp1_spi1 {
240	status = "okay";
241
242	flash@0 {
243		compatible = "jedec,spi-nor";
244		reg = <0x0>;
245		spi-max-frequency = <20000000>;
246
247		partitions {
248			compatible = "fixed-partitions";
249			#address-cells = <1>;
250			#size-cells = <1>;
251
252			partition@0 {
253				label = "Boot";
254				reg = <0x0 0x200000>;
255			};
256			partition@200000 {
257				label = "Filesystem";
258				reg = <0x200000 0xd00000>;
259			};
260			partition@f00000 {
261				label = "Boot_2nd";
262				reg = <0xf00000 0x100000>;
263			};
264		};
265	};
266};
267
268/*
269 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
270 * MDIO signal of CP1.
271 */
272&cp1_nand_controller {
273	pinctrl-0 = <&nand_pins>, <&nand_rb>;
274	pinctrl-names = "default";
275
276	nand@0 {
277		reg = <0>;
278		nand-rb = <0>;
279		nand-on-flash-bbt;
280		nand-ecc-strength = <4>;
281		nand-ecc-step-size = <512>;
282
283		partitions {
284			compatible = "fixed-partitions";
285			#address-cells = <1>;
286			#size-cells = <1>;
287
288			partition@0 {
289				label = "U-Boot";
290				reg = <0 0x200000>;
291			};
292			partition@200000 {
293				label = "Linux";
294				reg = <0x200000 0xe00000>;
295			};
296			partition@1000000 {
297				label = "Filesystem";
298				reg = <0x1000000 0x3f000000>;
299			};
300		};
301	};
302};
303
304/* CON4 on CP1 expansion */
305&cp1_sata0 {
306	status = "okay";
307
308	sata-port@0 {
309		phys = <&cp1_comphy1 0>;
310	};
311	sata-port@1 {
312		phys = <&cp1_comphy3 1>;
313	};
314};
315
316&cp1_utmi {
317	status = "okay";
318};
319
320/* CON9 on CP1 expansion */
321&cp1_usb3_0 {
322	usb-phy = <&cp1_usb3_0_phy>;
323	phys = <&cp1_utmi0>;
324	phy-names = "utmi";
325	dr_mode = "host";
326	status = "okay";
327};
328
329/* CON10 on CP1 expansion */
330&cp1_usb3_1 {
331	phys = <&cp1_utmi1>;
332	phy-names = "utmi";
333	status = "okay";
334};
335
336&cp1_mdio {
337	status = "okay";
338
339	phy0: ethernet-phy@0 {
340		reg = <0>;
341	};
342};
343
344&cp1_ethernet {
345	status = "okay";
346};
347
348&cp1_eth0 {
349	status = "okay";
350	phy-mode = "10gbase-r";
351
352	fixed-link {
353		speed = <10000>;
354		full-duplex;
355	};
356};
357
358&cp1_eth1 {
359	status = "okay";
360	phy = <&phy0>;
361	phy-mode = "rgmii-id";
362};
363
364&ap_sdhci0 {
365	status = "okay";
366	bus-width = <4>;
367	non-removable;
368};
369
370&cp0_sdhci0 {
371	status = "okay";
372	bus-width = <8>;
373	non-removable;
374};
375