1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/agilex-clock.h> 11 12/ { 13 compatible = "intel,socfpga-agilex"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 service_reserved: svcbuffer@0 { 23 compatible = "shared-dma-pool"; 24 reg = <0x0 0x0 0x0 0x2000000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 enable-method = "psci"; 38 reg = <0x0>; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x1>; 46 }; 47 48 cpu2: cpu@2 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 enable-method = "psci"; 52 reg = <0x2>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 }; 61 }; 62 63 firmware { 64 svc { 65 compatible = "intel,agilex-svc"; 66 method = "smc"; 67 memory-region = <&service_reserved>; 68 69 fpga_mgr: fpga-mgr { 70 compatible = "intel,agilex-soc-fpga-mgr"; 71 }; 72 }; 73 }; 74 75 fpga-region { 76 compatible = "fpga-region"; 77 #address-cells = <0x2>; 78 #size-cells = <0x2>; 79 fpga-mgr = <&fpga_mgr>; 80 }; 81 82 pmu { 83 compatible = "arm,cortex-a53-pmu"; 84 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 88 interrupt-affinity = <&cpu0>, 89 <&cpu1>, 90 <&cpu2>, 91 <&cpu3>; 92 interrupt-parent = <&intc>; 93 }; 94 95 psci { 96 compatible = "arm,psci-0.2"; 97 method = "smc"; 98 }; 99 100 intc: interrupt-controller@fffc1000 { 101 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 interrupt-parent = <&intc>; 105 reg = <0x0 0xfffc1000 0x0 0x1000>, 106 <0x0 0xfffc2000 0x0 0x2000>, 107 <0x0 0xfffc4000 0x0 0x2000>, 108 <0x0 0xfffc6000 0x0 0x2000>; 109 /* VGIC maintenance interrupt */ 110 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 clocks { 114 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 115 #clock-cells = <0>; 116 compatible = "fixed-clock"; 117 }; 118 119 cb_intosc_ls_clk: cb-intosc-ls-clk { 120 #clock-cells = <0>; 121 compatible = "fixed-clock"; 122 }; 123 124 f2s_free_clk: f2s-free-clk { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 }; 128 129 osc1: osc1 { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 }; 133 134 qspi_clk: qspi-clk { 135 #clock-cells = <0>; 136 compatible = "fixed-clock"; 137 clock-frequency = <200000000>; 138 }; 139 }; 140 141 timer { 142 compatible = "arm,armv8-timer"; 143 interrupt-parent = <&intc>; 144 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 145 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 146 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 147 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 148 }; 149 150 usbphy0: usbphy { 151 #phy-cells = <0>; 152 compatible = "usb-nop-xceiv"; 153 }; 154 155 soc@0 { 156 #address-cells = <1>; 157 #size-cells = <1>; 158 compatible = "simple-bus"; 159 device_type = "soc"; 160 interrupt-parent = <&intc>; 161 ranges = <0 0 0 0xffffffff>; 162 163 clkmgr: clock-controller@ffd10000 { 164 compatible = "intel,agilex-clkmgr"; 165 reg = <0xffd10000 0x1000>; 166 #clock-cells = <1>; 167 }; 168 169 gmac0: ethernet@ff800000 { 170 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 171 reg = <0xff800000 0x2000>; 172 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 173 interrupt-names = "macirq"; 174 mac-address = [00 00 00 00 00 00]; 175 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 176 reset-names = "stmmaceth", "ahb"; 177 tx-fifo-depth = <16384>; 178 rx-fifo-depth = <16384>; 179 snps,multicast-filter-bins = <256>; 180 iommus = <&smmu 1>; 181 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 182 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 183 clock-names = "stmmaceth", "ptp_ref"; 184 status = "disabled"; 185 }; 186 187 gmac1: ethernet@ff802000 { 188 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 189 reg = <0xff802000 0x2000>; 190 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 191 interrupt-names = "macirq"; 192 mac-address = [00 00 00 00 00 00]; 193 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 194 reset-names = "stmmaceth", "ahb"; 195 tx-fifo-depth = <16384>; 196 rx-fifo-depth = <16384>; 197 snps,multicast-filter-bins = <256>; 198 iommus = <&smmu 2>; 199 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 200 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 201 clock-names = "stmmaceth", "ptp_ref"; 202 status = "disabled"; 203 }; 204 205 gmac2: ethernet@ff804000 { 206 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 207 reg = <0xff804000 0x2000>; 208 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 209 interrupt-names = "macirq"; 210 mac-address = [00 00 00 00 00 00]; 211 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 212 reset-names = "stmmaceth", "ahb"; 213 tx-fifo-depth = <16384>; 214 rx-fifo-depth = <16384>; 215 snps,multicast-filter-bins = <256>; 216 iommus = <&smmu 3>; 217 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 218 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 219 clock-names = "stmmaceth", "ptp_ref"; 220 status = "disabled"; 221 }; 222 223 gpio0: gpio@ffc03200 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "snps,dw-apb-gpio"; 227 reg = <0xffc03200 0x100>; 228 resets = <&rst GPIO0_RESET>; 229 status = "disabled"; 230 231 porta: gpio-controller@0 { 232 compatible = "snps,dw-apb-gpio-port"; 233 gpio-controller; 234 #gpio-cells = <2>; 235 snps,nr-gpios = <24>; 236 reg = <0>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 240 }; 241 }; 242 243 gpio1: gpio@ffc03300 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "snps,dw-apb-gpio"; 247 reg = <0xffc03300 0x100>; 248 resets = <&rst GPIO1_RESET>; 249 status = "disabled"; 250 251 portb: gpio-controller@0 { 252 compatible = "snps,dw-apb-gpio-port"; 253 gpio-controller; 254 #gpio-cells = <2>; 255 snps,nr-gpios = <24>; 256 reg = <0>; 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 260 }; 261 }; 262 263 i2c0: i2c@ffc02800 { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 compatible = "snps,designware-i2c"; 267 reg = <0xffc02800 0x100>; 268 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 269 resets = <&rst I2C0_RESET>; 270 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 271 status = "disabled"; 272 }; 273 274 i2c1: i2c@ffc02900 { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 compatible = "snps,designware-i2c"; 278 reg = <0xffc02900 0x100>; 279 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 280 resets = <&rst I2C1_RESET>; 281 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 282 status = "disabled"; 283 }; 284 285 i2c2: i2c@ffc02a00 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 compatible = "snps,designware-i2c"; 289 reg = <0xffc02a00 0x100>; 290 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 291 resets = <&rst I2C2_RESET>; 292 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 293 status = "disabled"; 294 }; 295 296 i2c3: i2c@ffc02b00 { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 compatible = "snps,designware-i2c"; 300 reg = <0xffc02b00 0x100>; 301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 302 resets = <&rst I2C3_RESET>; 303 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 304 status = "disabled"; 305 }; 306 307 i2c4: i2c@ffc02c00 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 compatible = "snps,designware-i2c"; 311 reg = <0xffc02c00 0x100>; 312 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 313 resets = <&rst I2C4_RESET>; 314 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 315 status = "disabled"; 316 }; 317 318 mmc: mmc@ff808000 { 319 #address-cells = <1>; 320 #size-cells = <0>; 321 compatible = "altr,socfpga-dw-mshc"; 322 reg = <0xff808000 0x1000>; 323 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 324 fifo-depth = <0x400>; 325 resets = <&rst SDMMC_RESET>; 326 reset-names = "reset"; 327 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 328 <&clkmgr AGILEX_SDMMC_CLK>; 329 clock-names = "biu", "ciu"; 330 iommus = <&smmu 5>; 331 altr,sysmgr-syscon = <&sysmgr 0x28 4>; 332 status = "disabled"; 333 }; 334 335 nand: nand-controller@ffb90000 { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 compatible = "altr,socfpga-denali-nand"; 339 reg = <0xffb90000 0x10000>, 340 <0xffb80000 0x1000>; 341 reg-names = "nand_data", "denali_reg"; 342 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&clkmgr AGILEX_NAND_CLK>, 344 <&clkmgr AGILEX_NAND_X_CLK>, 345 <&clkmgr AGILEX_NAND_ECC_CLK>; 346 clock-names = "nand", "nand_x", "ecc"; 347 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 348 status = "disabled"; 349 }; 350 351 ocram: sram@ffe00000 { 352 compatible = "mmio-sram"; 353 reg = <0xffe00000 0x40000>; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges = <0 0xffe00000 0x40000>; 357 }; 358 359 pdma: dma-controller@ffda0000 { 360 compatible = "arm,pl330", "arm,primecell"; 361 reg = <0xffda0000 0x1000>; 362 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 371 #dma-cells = <1>; 372 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 373 reset-names = "dma", "dma-ocp"; 374 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 375 clock-names = "apb_pclk"; 376 }; 377 378 pinctrl0: pinctrl@ffd13000 { 379 compatible = "pinctrl-single"; 380 #pinctrl-cells = <1>; 381 reg = <0xffd13000 0xa0>; 382 pinctrl-single,register-width = <32>; 383 pinctrl-single,function-mask = <0x0000000f>; 384 }; 385 386 pinctrl1: pinctrl@ffd13100 { 387 compatible = "pinctrl-single"; 388 #pinctrl-cells = <1>; 389 reg = <0xffd13100 0x20>; 390 pinctrl-single,register-width = <32>; 391 }; 392 393 rst: rstmgr@ffd11000 { 394 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; 395 reg = <0xffd11000 0x100>; 396 #reset-cells = <1>; 397 }; 398 399 smmu: iommu@fa000000 { 400 compatible = "arm,mmu-500", "arm,smmu-v2"; 401 reg = <0xfa000000 0x40000>; 402 #global-interrupts = <2>; 403 #iommu-cells = <1>; 404 interrupt-parent = <&intc>; 405 /* Global Secure Fault */ 406 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 407 /* Global Non-secure Fault */ 408 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 409 /* Non-secure Context Interrupts (32) */ 410 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 442 stream-match-mask = <0x7ff0>; 443 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 444 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 445 <&clkmgr AGILEX_L4_MAIN_CLK>; 446 status = "disabled"; 447 }; 448 449 spi0: spi@ffda4000 { 450 compatible = "snps,dw-apb-ssi"; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 reg = <0xffda4000 0x1000>; 454 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 455 resets = <&rst SPIM0_RESET>; 456 reset-names = "spi"; 457 reg-io-width = <4>; 458 num-cs = <4>; 459 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 460 status = "disabled"; 461 }; 462 463 spi1: spi@ffda5000 { 464 compatible = "snps,dw-apb-ssi"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 reg = <0xffda5000 0x1000>; 468 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 469 resets = <&rst SPIM1_RESET>; 470 reset-names = "spi"; 471 reg-io-width = <4>; 472 num-cs = <4>; 473 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 474 status = "disabled"; 475 }; 476 477 sysmgr: sysmgr@ffd12000 { 478 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 479 reg = <0xffd12000 0x500>; 480 }; 481 482 timer0: timer0@ffc03000 { 483 compatible = "snps,dw-apb-timer"; 484 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 485 reg = <0xffc03000 0x100>; 486 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 487 clock-names = "timer"; 488 }; 489 490 timer1: timer1@ffc03100 { 491 compatible = "snps,dw-apb-timer"; 492 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 493 reg = <0xffc03100 0x100>; 494 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 495 clock-names = "timer"; 496 }; 497 498 timer2: timer2@ffd00000 { 499 compatible = "snps,dw-apb-timer"; 500 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 501 reg = <0xffd00000 0x100>; 502 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 503 clock-names = "timer"; 504 }; 505 506 timer3: timer3@ffd00100 { 507 compatible = "snps,dw-apb-timer"; 508 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 509 reg = <0xffd00100 0x100>; 510 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 511 clock-names = "timer"; 512 }; 513 514 uart0: serial@ffc02000 { 515 compatible = "snps,dw-apb-uart"; 516 reg = <0xffc02000 0x100>; 517 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 518 reg-shift = <2>; 519 reg-io-width = <4>; 520 resets = <&rst UART0_RESET>; 521 status = "disabled"; 522 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 523 }; 524 525 uart1: serial@ffc02100 { 526 compatible = "snps,dw-apb-uart"; 527 reg = <0xffc02100 0x100>; 528 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 529 reg-shift = <2>; 530 reg-io-width = <4>; 531 resets = <&rst UART1_RESET>; 532 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 533 status = "disabled"; 534 }; 535 536 usb0: usb@ffb00000 { 537 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 538 reg = <0xffb00000 0x40000>; 539 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 540 phys = <&usbphy0>; 541 phy-names = "usb2-phy"; 542 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 543 reset-names = "dwc2", "dwc2-ecc"; 544 clocks = <&clkmgr AGILEX_USB_CLK>; 545 clock-names = "otg"; 546 iommus = <&smmu 6>; 547 status = "disabled"; 548 }; 549 550 usb1: usb@ffb40000 { 551 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 552 reg = <0xffb40000 0x40000>; 553 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 554 phys = <&usbphy0>; 555 phy-names = "usb2-phy"; 556 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 557 reset-names = "dwc2", "dwc2-ecc"; 558 iommus = <&smmu 7>; 559 clocks = <&clkmgr AGILEX_USB_CLK>; 560 status = "disabled"; 561 }; 562 563 watchdog0: watchdog@ffd00200 { 564 compatible = "snps,dw-wdt"; 565 reg = <0xffd00200 0x100>; 566 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 567 resets = <&rst WATCHDOG0_RESET>; 568 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 569 status = "disabled"; 570 }; 571 572 watchdog1: watchdog@ffd00300 { 573 compatible = "snps,dw-wdt"; 574 reg = <0xffd00300 0x100>; 575 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 576 resets = <&rst WATCHDOG1_RESET>; 577 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 578 status = "disabled"; 579 }; 580 581 watchdog2: watchdog@ffd00400 { 582 compatible = "snps,dw-wdt"; 583 reg = <0xffd00400 0x100>; 584 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 585 resets = <&rst WATCHDOG2_RESET>; 586 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 587 status = "disabled"; 588 }; 589 590 watchdog3: watchdog@ffd00500 { 591 compatible = "snps,dw-wdt"; 592 reg = <0xffd00500 0x100>; 593 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 594 resets = <&rst WATCHDOG3_RESET>; 595 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 596 status = "disabled"; 597 }; 598 599 sdr: sdr@f8011100 { 600 compatible = "altr,sdr-ctl", "syscon"; 601 reg = <0xf8011100 0xc0>; 602 }; 603 604 eccmgr { 605 compatible = "altr,socfpga-s10-ecc-manager", 606 "altr,socfpga-a10-ecc-manager"; 607 altr,sysmgr-syscon = <&sysmgr>; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 ranges; 614 615 sdramedac { 616 compatible = "altr,sdram-edac-s10"; 617 altr,sdr-syscon = <&sdr>; 618 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 619 }; 620 621 ocram-ecc@ff8cc000 { 622 compatible = "altr,socfpga-s10-ocram-ecc", 623 "altr,socfpga-a10-ocram-ecc"; 624 reg = <0xff8cc000 0x100>; 625 altr,ecc-parent = <&ocram>; 626 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 627 }; 628 629 usb0-ecc@ff8c4000 { 630 compatible = "altr,socfpga-s10-usb-ecc", 631 "altr,socfpga-usb-ecc"; 632 reg = <0xff8c4000 0x100>; 633 altr,ecc-parent = <&usb0>; 634 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 635 }; 636 637 emac0-rx-ecc@ff8c0000 { 638 compatible = "altr,socfpga-s10-eth-mac-ecc", 639 "altr,socfpga-eth-mac-ecc"; 640 reg = <0xff8c0000 0x100>; 641 altr,ecc-parent = <&gmac0>; 642 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 643 }; 644 645 emac0-tx-ecc@ff8c0400 { 646 compatible = "altr,socfpga-s10-eth-mac-ecc", 647 "altr,socfpga-eth-mac-ecc"; 648 reg = <0xff8c0400 0x100>; 649 altr,ecc-parent = <&gmac0>; 650 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 651 }; 652 653 sdmmca-ecc@ff8c8c00 { 654 compatible = "altr,socfpga-s10-sdmmc-ecc", 655 "altr,socfpga-sdmmc-ecc"; 656 reg = <0xff8c8c00 0x100>; 657 altr,ecc-parent = <&mmc>; 658 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 659 <15 IRQ_TYPE_LEVEL_HIGH>; 660 }; 661 }; 662 663 qspi: spi@ff8d2000 { 664 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 reg = <0xff8d2000 0x100>, 668 <0xff900000 0x100000>; 669 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 670 cdns,fifo-depth = <128>; 671 cdns,fifo-width = <4>; 672 cdns,trigger-address = <0x00000000>; 673 clocks = <&qspi_clk>; 674 675 status = "disabled"; 676 }; 677 }; 678}; 679