1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include "imx95.dtsi" 10 11#define FALLING_EDGE 1 12#define RISING_EDGE 2 13 14#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ 15#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ 16#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ 17#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ 18#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ 19 20/ { 21 model = "NXP i.MX95 19X19 board"; 22 compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; 23 24 aliases { 25 ethernet0 = &enetc_port0; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 i2c0 = &lpi2c1; 32 i2c1 = &lpi2c2; 33 i2c2 = &lpi2c3; 34 i2c3 = &lpi2c4; 35 i2c4 = &lpi2c5; 36 i2c5 = &lpi2c6; 37 i2c6 = &lpi2c7; 38 i2c7 = &lpi2c8; 39 mmc0 = &usdhc1; 40 mmc1 = &usdhc2; 41 serial0 = &lpuart1; 42 }; 43 44 bt_sco_codec: audio-codec-bt-sco { 45 #sound-dai-cells = <1>; 46 compatible = "linux,bt-sco"; 47 }; 48 49 chosen { 50 stdout-path = &lpuart1; 51 }; 52 53 memory@80000000 { 54 device_type = "memory"; 55 reg = <0x0 0x80000000 0 0x80000000>; 56 }; 57 58 fan0: pwm-fan { 59 compatible = "pwm-fan"; 60 #cooling-cells = <2>; 61 pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; 62 cooling-levels = <64 128 192 255>; 63 }; 64 65 reserved-memory { 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 linux_cma: linux,cma { 71 compatible = "shared-dma-pool"; 72 alloc-ranges = <0 0x80000000 0 0x7f000000>; 73 size = <0 0x3c000000>; 74 linux,cma-default; 75 reusable; 76 }; 77 }; 78 79 reg_3p3v: regulator-3p3v { 80 compatible = "regulator-fixed"; 81 regulator-max-microvolt = <3300000>; 82 regulator-min-microvolt = <3300000>; 83 regulator-name = "+V3.3_SW"; 84 }; 85 86 reg_audio_pwr: regulator-audio-pwr { 87 compatible = "regulator-fixed"; 88 regulator-name = "audio-pwr"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 gpio = <&i2c4_gpio_expander_21 1 GPIO_ACTIVE_HIGH>; 92 enable-active-high; 93 regulator-always-on; 94 }; 95 96 reg_audio_slot: regulator-audio-slot { 97 compatible = "regulator-fixed"; 98 regulator-name = "audio-wm8962"; 99 regulator-min-microvolt = <3300000>; 100 regulator-max-microvolt = <3300000>; 101 gpio = <&i2c4_gpio_expander_21 7 GPIO_ACTIVE_HIGH>; 102 enable-active-high; 103 regulator-always-on; 104 status = "disabled"; 105 }; 106 107 reg_m2_pwr: regulator-m2-pwr { 108 compatible = "regulator-fixed"; 109 regulator-name = "M.2-power"; 110 regulator-min-microvolt = <3300000>; 111 regulator-max-microvolt = <3300000>; 112 gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; 113 enable-active-high; 114 }; 115 116 reg_pcie0: regulator-pcie { 117 compatible = "regulator-fixed"; 118 regulator-name = "PCIE_WLAN_EN"; 119 regulator-min-microvolt = <3300000>; 120 regulator-max-microvolt = <3300000>; 121 vin-supply = <®_m2_pwr>; 122 gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>; 123 enable-active-high; 124 }; 125 126 reg_slot_pwr: regulator-slot-pwr { 127 compatible = "regulator-fixed"; 128 regulator-name = "PCIe slot-power"; 129 regulator-min-microvolt = <3300000>; 130 regulator-max-microvolt = <3300000>; 131 gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>; 132 enable-active-high; 133 }; 134 135 reg_usdhc2_vmmc: regulator-usdhc2 { 136 compatible = "regulator-fixed"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 139 regulator-name = "VDD_SD2_3V3"; 140 regulator-min-microvolt = <3300000>; 141 regulator-max-microvolt = <3300000>; 142 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 143 enable-active-high; 144 off-on-delay-us = <12000>; 145 }; 146 147 sound-bt-sco { 148 compatible = "simple-audio-card"; 149 simple-audio-card,name = "bt-sco-audio"; 150 simple-audio-card,format = "dsp_a"; 151 simple-audio-card,bitclock-inversion; 152 simple-audio-card,frame-master = <&btcpu>; 153 simple-audio-card,bitclock-master = <&btcpu>; 154 155 btcpu: simple-audio-card,cpu { 156 sound-dai = <&sai1>; 157 dai-tdm-slot-num = <2>; 158 dai-tdm-slot-width = <16>; 159 }; 160 161 simple-audio-card,codec { 162 sound-dai = <&bt_sco_codec 1>; 163 }; 164 }; 165 166 sound-micfil { 167 compatible = "fsl,imx-audio-card"; 168 model = "micfil-audio"; 169 170 pri-dai-link { 171 link-name = "micfil hifi"; 172 format = "i2s"; 173 cpu { 174 sound-dai = <&micfil>; 175 }; 176 }; 177 }; 178 179 sound-wm8962 { 180 compatible = "fsl,imx-audio-wm8962"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_hp>; 183 model = "wm8962-audio"; 184 audio-cpu = <&sai3>; 185 audio-codec = <&wm8962>; 186 hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 187 audio-routing = "Headphone Jack", "HPOUTL", 188 "Headphone Jack", "HPOUTR", 189 "Ext Spk", "SPKOUTL", 190 "Ext Spk", "SPKOUTR", 191 "AMIC", "MICBIAS", 192 "IN3R", "AMIC", 193 "IN1R", "AMIC"; 194 }; 195}; 196 197&enetc_port0 { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_enetc0>; 200 phy-handle = <ðphy0>; 201 phy-mode = "rgmii-id"; 202 status = "okay"; 203}; 204 205&flexspi1 { 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_flexspi1>; 208 status = "okay"; 209 210 flash@0 { 211 compatible = "jedec,spi-nor"; 212 reg = <0>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_flexspi1_reset>; 215 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 spi-max-frequency = <200000000>; 219 spi-tx-bus-width = <8>; 220 spi-rx-bus-width = <8>; 221 }; 222}; 223 224&lpi2c4 { 225 clock-frequency = <400000>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_lpi2c4>; 228 status = "okay"; 229 230 wm8962: audio-codec@1a { 231 compatible = "wlf,wm8962"; 232 reg = <0x1a>; 233 clocks = <&scmi_clk IMX95_CLK_SAI3>; 234 DCVDD-supply = <®_audio_pwr>; 235 DBVDD-supply = <®_audio_pwr>; 236 AVDD-supply = <®_audio_pwr>; 237 CPVDD-supply = <®_audio_pwr>; 238 MICVDD-supply = <®_audio_pwr>; 239 PLLVDD-supply = <®_audio_pwr>; 240 SPKVDD1-supply = <®_audio_pwr>; 241 SPKVDD2-supply = <®_audio_pwr>; 242 gpio-cfg = < 0x0000 /* 0:Default */ 243 0x0000 /* 1:Default */ 244 0x0000 /* 2:FN_DMICCLK */ 245 0x0000 /* 3:Default */ 246 0x0000 /* 4:FN_DMICCDAT */ 247 0x0000 /* 5:Default */ 248 >; 249 }; 250 251 i2c4_gpio_expander_21: gpio@21 { 252 compatible = "nxp,pcal6408"; 253 reg = <0x21>; 254 #gpio-cells = <2>; 255 gpio-controller; 256 interrupt-controller; 257 #interrupt-cells = <2>; 258 interrupt-parent = <&gpio2>; 259 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_i2c4_pcal6408>; 262 vcc-supply = <®_3p3v>; 263 }; 264}; 265 266&lpi2c5 { 267 clock-frequency = <100000>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_lpi2c5>; 270 status = "okay"; 271 272 i2c5_pcal6408: gpio@21 { 273 compatible = "nxp,pcal6408"; 274 reg = <0x21>; 275 gpio-controller; 276 #gpio-cells = <2>; 277 vcc-supply = <®_3p3v>; 278 }; 279}; 280 281&lpi2c6 { 282 clock-frequency = <100000>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pinctrl_lpi2c6>; 285 status = "okay"; 286 287 i2c6_pcal6416: gpio@21 { 288 compatible = "nxp,pcal6416"; 289 reg = <0x21>; 290 gpio-controller; 291 #gpio-cells = <2>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 interrupt-parent = <&gpio4>; 295 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_pcal6416>; 298 vcc-supply = <®_3p3v>; 299 }; 300}; 301 302&lpi2c7 { 303 clock-frequency = <1000000>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_lpi2c7>; 306 status = "okay"; 307 308 i2c7_pcal6524: i2c7-gpio@22 { 309 compatible = "nxp,pcal6524"; 310 reg = <0x22>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_i2c7_pcal6524>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 interrupt-parent = <&gpio5>; 318 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 319 }; 320}; 321 322&lpuart1 { 323 /* console */ 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_uart1>; 326 status = "okay"; 327}; 328 329&micfil { 330 #sound-dai-cells = <0>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pinctrl_pdm>; 333 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 334 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 335 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 336 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 337 <&scmi_clk IMX95_CLK_PDM>; 338 assigned-clock-parents = <0>, <0>, <0>, <0>, 339 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 340 assigned-clock-rates = <3932160000>, 341 <3612672000>, <393216000>, 342 <361267200>, <49152000>; 343 status = "okay"; 344}; 345 346&mu7 { 347 status = "okay"; 348}; 349 350&netcmix_blk_ctrl { 351 status = "okay"; 352}; 353 354&netc_blk_ctrl { 355 status = "okay"; 356}; 357 358&netc_emdio { 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_emdio>; 361 status = "okay"; 362 363 ethphy0: ethernet-phy@1 { 364 reg = <1>; 365 realtek,clkout-disable; 366 }; 367}; 368 369&pcie0 { 370 pinctrl-0 = <&pinctrl_pcie0>; 371 pinctrl-names = "default"; 372 reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; 373 vpcie-supply = <®_pcie0>; 374 status = "okay"; 375}; 376 377&pcie1 { 378 pinctrl-0 = <&pinctrl_pcie1>; 379 pinctrl-names = "default"; 380 reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; 381 vpcie-supply = <®_slot_pwr>; 382 status = "okay"; 383}; 384 385&sai1 { 386 #sound-dai-cells = <0>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&pinctrl_sai1>; 389 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 390 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 391 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 392 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 393 <&scmi_clk IMX95_CLK_SAI1>; 394 assigned-clock-parents = <0>, <0>, <0>, <0>, 395 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 396 assigned-clock-rates = <3932160000>, 397 <3612672000>, <393216000>, 398 <361267200>, <12288000>; 399 fsl,sai-mclk-direction-output; 400 status = "okay"; 401}; 402 403&sai3 { 404 #sound-dai-cells = <0>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_sai3>; 407 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 408 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 409 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 410 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 411 <&scmi_clk IMX95_CLK_SAI3>; 412 assigned-clock-parents = <0>, <0>, <0>, <0>, 413 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 414 assigned-clock-rates = <3932160000>, 415 <3612672000>, <393216000>, 416 <361267200>, <12288000>; 417 fsl,sai-mclk-direction-output; 418 status = "okay"; 419}; 420 421&usdhc1 { 422 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 423 pinctrl-0 = <&pinctrl_usdhc1>; 424 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 425 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 426 pinctrl-3 = <&pinctrl_usdhc1>; 427 bus-width = <8>; 428 non-removable; 429 no-sdio; 430 no-sd; 431 status = "okay"; 432}; 433 434&usdhc2 { 435 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 436 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 437 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 438 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 439 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 440 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 441 vmmc-supply = <®_usdhc2_vmmc>; 442 bus-width = <4>; 443 status = "okay"; 444}; 445 446&scmi_misc { 447 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE 448 BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE 449 BRD_SM_CTRL_BT_WAKE FALLING_EDGE 450 BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE 451 BRD_SM_CTRL_BUTTON FALLING_EDGE>; 452}; 453 454&wdog3 { 455 fsl,ext-reset-output; 456 status = "okay"; 457}; 458 459&scmi_iomuxc { 460 pinctrl_emdio: emdiogrp{ 461 fsl,pins = < 462 IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e 463 IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e 464 >; 465 }; 466 467 pinctrl_enetc0: enetc0grp { 468 fsl,pins = < 469 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e 470 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e 471 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e 472 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e 473 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 474 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 475 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 476 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 477 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 478 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 479 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 480 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 481 >; 482 }; 483 484 pinctrl_flexspi1: flexspi1grp { 485 fsl,pins = < 486 IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe 487 IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe 488 IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe 489 IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe 490 IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe 491 IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe 492 IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe 493 IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe 494 IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe 495 IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe 496 IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe 497 >; 498 }; 499 500 pinctrl_flexspi1_reset: flexspi1-reset-grp { 501 fsl,pins = < 502 IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe 503 >; 504 }; 505 506 pinctrl_hp: hpgrp { 507 fsl,pins = < 508 IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e 509 >; 510 }; 511 512 pinctrl_i2c4_pcal6408: i2c4pcal6498grp { 513 fsl,pins = < 514 IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e 515 >; 516 }; 517 518 pinctrl_i2c7_pcal6524: i2c7pcal6524grp { 519 fsl,pins = < 520 IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e 521 >; 522 }; 523 524 pinctrl_lpi2c4: lpi2c4grp { 525 fsl,pins = < 526 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 527 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 528 >; 529 }; 530 531 pinctrl_lpi2c5: lpi2c5grp { 532 fsl,pins = < 533 IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 534 IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 535 >; 536 }; 537 538 pinctrl_lpi2c6: lpi2c6grp { 539 fsl,pins = < 540 IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e 541 IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e 542 >; 543 }; 544 545 pinctrl_lpi2c7: lpi2c7grp { 546 fsl,pins = < 547 IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e 548 IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e 549 >; 550 }; 551 552 pinctrl_pcie0: pcie0grp { 553 fsl,pins = < 554 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e 555 >; 556 }; 557 558 pinctrl_pcie1: pcie1grp { 559 fsl,pins = < 560 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 561 >; 562 }; 563 564 pinctrl_pcal6416: pcal6416grp { 565 fsl,pins = < 566 IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e 567 >; 568 }; 569 570 pinctrl_pdm: pdmgrp { 571 fsl,pins = < 572 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 573 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 574 >; 575 }; 576 577 pinctrl_sai1: sai1grp { 578 fsl,pins = < 579 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e 580 IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e 581 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e 582 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e 583 >; 584 }; 585 586 pinctrl_sai2: sai2grp { 587 fsl,pins = < 588 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e 589 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e 590 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e 591 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e 592 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e 593 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e 594 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e 595 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e 596 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e 597 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e 598 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e 599 >; 600 }; 601 602 pinctrl_sai3: sai3grp { 603 fsl,pins = < 604 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 605 IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 606 IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 607 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 608 IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e 609 >; 610 }; 611 612 pinctrl_tpm6: tpm6grp { 613 fsl,pins = < 614 IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e 615 >; 616 }; 617 618 pinctrl_uart1: uart1grp { 619 fsl,pins = < 620 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 621 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 622 >; 623 }; 624 625 pinctrl_usdhc1: usdhc1grp { 626 fsl,pins = < 627 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 628 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 629 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 630 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 631 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 632 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 633 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 634 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 635 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 636 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 637 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 638 >; 639 }; 640 641 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 642 fsl,pins = < 643 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 644 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 645 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 646 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 647 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 648 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 649 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 650 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 651 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 652 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 653 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 654 >; 655 }; 656 657 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 658 fsl,pins = < 659 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 660 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 661 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 662 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 663 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 664 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 665 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 666 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 667 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 668 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 669 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 670 >; 671 }; 672 673 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 674 fsl,pins = < 675 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 676 >; 677 }; 678 679 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 680 fsl,pins = < 681 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 682 >; 683 }; 684 685 pinctrl_usdhc2: usdhc2grp { 686 fsl,pins = < 687 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 688 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 689 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 690 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 691 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 692 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 693 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 694 >; 695 }; 696 697 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 698 fsl,pins = < 699 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 700 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 701 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 702 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 703 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 704 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 705 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 706 >; 707 }; 708 709 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 710 fsl,pins = < 711 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 712 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 713 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 714 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 715 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 716 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 717 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 718 >; 719 }; 720}; 721 722&thermal_zones { 723 a55-thermal { 724 trips { 725 atrip2: trip2 { 726 temperature = <55000>; 727 hysteresis = <2000>; 728 type = "active"; 729 }; 730 731 atrip3: trip3 { 732 temperature = <65000>; 733 hysteresis = <2000>; 734 type = "active"; 735 }; 736 737 atrip4: trip4 { 738 temperature = <75000>; 739 hysteresis = <2000>; 740 type = "active"; 741 }; 742 }; 743 744 cooling-maps { 745 map1 { 746 trip = <&atrip2>; 747 cooling-device = <&fan0 0 1>; 748 }; 749 750 map2 { 751 trip = <&atrip3>; 752 cooling-device = <&fan0 1 2>; 753 }; 754 755 map3 { 756 trip = <&atrip4>; 757 cooling-device = <&fan0 2 3>; 758 }; 759 }; 760 }; 761}; 762 763&tpm6 { 764 pinctrl-names = "default"; 765 pinctrl-0 = <&pinctrl_tpm6>; 766 status = "okay"; 767}; 768