1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 idle-states { 51 entry-method = "psci"; 52 53 cpu_pd_wait: cpu-pd-wait { 54 compatible = "arm,idle-state"; 55 arm,psci-suspend-param = <0x0010033>; 56 local-timer-stop; 57 entry-latency-us = <1000>; 58 exit-latency-us = <700>; 59 min-residency-us = <2700>; 60 wakeup-latency-us = <1500>; 61 }; 62 }; 63 64 A53_0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0>; 68 clock-latency = <61036>; 69 clocks = <&clk IMX8MP_CLK_ARM>; 70 enable-method = "psci"; 71 i-cache-size = <0x8000>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <256>; 74 d-cache-size = <0x8000>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&A53_L2>; 78 nvmem-cells = <&cpu_speed_grade>; 79 nvmem-cell-names = "speed_grade"; 80 operating-points-v2 = <&a53_opp_table>; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 }; 84 85 A53_1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x1>; 89 clock-latency = <61036>; 90 clocks = <&clk IMX8MP_CLK_ARM>; 91 enable-method = "psci"; 92 i-cache-size = <0x8000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <256>; 95 d-cache-size = <0x8000>; 96 d-cache-line-size = <64>; 97 d-cache-sets = <128>; 98 next-level-cache = <&A53_L2>; 99 operating-points-v2 = <&a53_opp_table>; 100 #cooling-cells = <2>; 101 cpu-idle-states = <&cpu_pd_wait>; 102 }; 103 104 A53_2: cpu@2 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 reg = <0x2>; 108 clock-latency = <61036>; 109 clocks = <&clk IMX8MP_CLK_ARM>; 110 enable-method = "psci"; 111 i-cache-size = <0x8000>; 112 i-cache-line-size = <64>; 113 i-cache-sets = <256>; 114 d-cache-size = <0x8000>; 115 d-cache-line-size = <64>; 116 d-cache-sets = <128>; 117 next-level-cache = <&A53_L2>; 118 operating-points-v2 = <&a53_opp_table>; 119 #cooling-cells = <2>; 120 cpu-idle-states = <&cpu_pd_wait>; 121 }; 122 123 A53_3: cpu@3 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53"; 126 reg = <0x3>; 127 clock-latency = <61036>; 128 clocks = <&clk IMX8MP_CLK_ARM>; 129 enable-method = "psci"; 130 i-cache-size = <0x8000>; 131 i-cache-line-size = <64>; 132 i-cache-sets = <256>; 133 d-cache-size = <0x8000>; 134 d-cache-line-size = <64>; 135 d-cache-sets = <128>; 136 next-level-cache = <&A53_L2>; 137 operating-points-v2 = <&a53_opp_table>; 138 #cooling-cells = <2>; 139 cpu-idle-states = <&cpu_pd_wait>; 140 }; 141 142 A53_L2: l2-cache0 { 143 compatible = "cache"; 144 cache-unified; 145 cache-level = <2>; 146 cache-size = <0x80000>; 147 cache-line-size = <64>; 148 cache-sets = <512>; 149 }; 150 }; 151 152 a53_opp_table: opp-table { 153 compatible = "operating-points-v2"; 154 opp-shared; 155 156 opp-1200000000 { 157 opp-hz = /bits/ 64 <1200000000>; 158 opp-microvolt = <850000>; 159 opp-supported-hw = <0x8a0>, <0x7>; 160 clock-latency-ns = <150000>; 161 opp-suspend; 162 }; 163 164 opp-1600000000 { 165 opp-hz = /bits/ 64 <1600000000>; 166 opp-microvolt = <950000>; 167 opp-supported-hw = <0xa0>, <0x7>; 168 clock-latency-ns = <150000>; 169 opp-suspend; 170 }; 171 172 opp-1800000000 { 173 opp-hz = /bits/ 64 <1800000000>; 174 opp-microvolt = <1000000>; 175 opp-supported-hw = <0x20>, <0x3>; 176 clock-latency-ns = <150000>; 177 opp-suspend; 178 }; 179 }; 180 181 osc_32k: clock-osc-32k { 182 compatible = "fixed-clock"; 183 #clock-cells = <0>; 184 clock-frequency = <32768>; 185 clock-output-names = "osc_32k"; 186 }; 187 188 osc_24m: clock-osc-24m { 189 compatible = "fixed-clock"; 190 #clock-cells = <0>; 191 clock-frequency = <24000000>; 192 clock-output-names = "osc_24m"; 193 }; 194 195 clk_ext1: clock-ext1 { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <133000000>; 199 clock-output-names = "clk_ext1"; 200 }; 201 202 clk_ext2: clock-ext2 { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <133000000>; 206 clock-output-names = "clk_ext2"; 207 }; 208 209 clk_ext3: clock-ext3 { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <133000000>; 213 clock-output-names = "clk_ext3"; 214 }; 215 216 clk_ext4: clock-ext4 { 217 compatible = "fixed-clock"; 218 #clock-cells = <0>; 219 clock-frequency = <133000000>; 220 clock-output-names = "clk_ext4"; 221 }; 222 223 funnel { 224 /* 225 * non-configurable funnel don't show up on the AMBA 226 * bus. As such no need to add "arm,primecell". 227 */ 228 compatible = "arm,coresight-static-funnel"; 229 230 in-ports { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 port@0 { 235 reg = <0>; 236 237 ca_funnel_in_port0: endpoint { 238 remote-endpoint = <&etm0_out_port>; 239 }; 240 }; 241 242 port@1 { 243 reg = <1>; 244 245 ca_funnel_in_port1: endpoint { 246 remote-endpoint = <&etm1_out_port>; 247 }; 248 }; 249 250 port@2 { 251 reg = <2>; 252 253 ca_funnel_in_port2: endpoint { 254 remote-endpoint = <&etm2_out_port>; 255 }; 256 }; 257 258 port@3 { 259 reg = <3>; 260 261 ca_funnel_in_port3: endpoint { 262 remote-endpoint = <&etm3_out_port>; 263 }; 264 }; 265 }; 266 267 out-ports { 268 port { 269 270 ca_funnel_out_port0: endpoint { 271 remote-endpoint = <&hugo_funnel_in_port0>; 272 }; 273 }; 274 }; 275 }; 276 277 reserved-memory { 278 #address-cells = <2>; 279 #size-cells = <2>; 280 ranges; 281 282 dsp_reserved: dsp@92400000 { 283 reg = <0 0x92400000 0 0x2000000>; 284 no-map; 285 status = "disabled"; 286 }; 287 }; 288 289 pmu { 290 compatible = "arm,cortex-a53-pmu"; 291 interrupts = <GIC_PPI 7 292 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 293 }; 294 295 psci { 296 compatible = "arm,psci-1.0"; 297 method = "smc"; 298 }; 299 300 thermal-zones { 301 cpu-thermal { 302 polling-delay-passive = <250>; 303 polling-delay = <2000>; 304 thermal-sensors = <&tmu 0>; 305 trips { 306 cpu_alert0: trip0 { 307 temperature = <85000>; 308 hysteresis = <2000>; 309 type = "passive"; 310 }; 311 312 cpu_crit0: trip1 { 313 temperature = <95000>; 314 hysteresis = <2000>; 315 type = "critical"; 316 }; 317 }; 318 319 cooling-maps { 320 map0 { 321 trip = <&cpu_alert0>; 322 cooling-device = 323 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 324 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 325 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 326 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 327 }; 328 }; 329 }; 330 331 soc-thermal { 332 polling-delay-passive = <250>; 333 polling-delay = <2000>; 334 thermal-sensors = <&tmu 1>; 335 trips { 336 soc_alert0: trip0 { 337 temperature = <85000>; 338 hysteresis = <2000>; 339 type = "passive"; 340 }; 341 342 soc_crit0: trip1 { 343 temperature = <95000>; 344 hysteresis = <2000>; 345 type = "critical"; 346 }; 347 }; 348 349 cooling-maps { 350 map0 { 351 trip = <&soc_alert0>; 352 cooling-device = 353 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 354 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 357 }; 358 }; 359 }; 360 }; 361 362 timer { 363 compatible = "arm,armv8-timer"; 364 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 365 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 366 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 367 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 368 clock-frequency = <8000000>; 369 arm,no-tick-in-suspend; 370 }; 371 372 soc: soc@0 { 373 compatible = "fsl,imx8mp-soc", "simple-bus"; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges = <0x0 0x0 0x0 0x3e000000>; 377 nvmem-cells = <&imx8mp_uid>; 378 nvmem-cell-names = "soc_unique_id"; 379 380 etm0: etm@28440000 { 381 compatible = "arm,coresight-etm4x", "arm,primecell"; 382 reg = <0x28440000 0x1000>; 383 cpu = <&A53_0>; 384 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 385 clock-names = "apb_pclk"; 386 387 out-ports { 388 port { 389 etm0_out_port: endpoint { 390 remote-endpoint = <&ca_funnel_in_port0>; 391 }; 392 }; 393 }; 394 }; 395 396 etm1: etm@28540000 { 397 compatible = "arm,coresight-etm4x", "arm,primecell"; 398 reg = <0x28540000 0x1000>; 399 cpu = <&A53_1>; 400 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 401 clock-names = "apb_pclk"; 402 403 out-ports { 404 port { 405 etm1_out_port: endpoint { 406 remote-endpoint = <&ca_funnel_in_port1>; 407 }; 408 }; 409 }; 410 }; 411 412 etm2: etm@28640000 { 413 compatible = "arm,coresight-etm4x", "arm,primecell"; 414 reg = <0x28640000 0x1000>; 415 cpu = <&A53_2>; 416 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 417 clock-names = "apb_pclk"; 418 419 out-ports { 420 port { 421 etm2_out_port: endpoint { 422 remote-endpoint = <&ca_funnel_in_port2>; 423 }; 424 }; 425 }; 426 }; 427 428 etm3: etm@28740000 { 429 compatible = "arm,coresight-etm4x", "arm,primecell"; 430 reg = <0x28740000 0x1000>; 431 cpu = <&A53_3>; 432 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 433 clock-names = "apb_pclk"; 434 435 out-ports { 436 port { 437 etm3_out_port: endpoint { 438 remote-endpoint = <&ca_funnel_in_port3>; 439 }; 440 }; 441 }; 442 }; 443 444 funnel@28c03000 { 445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 446 reg = <0x28c03000 0x1000>; 447 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 448 clock-names = "apb_pclk"; 449 450 in-ports { 451 #address-cells = <1>; 452 #size-cells = <0>; 453 454 port@0 { 455 reg = <0>; 456 457 hugo_funnel_in_port0: endpoint { 458 remote-endpoint = <&ca_funnel_out_port0>; 459 }; 460 }; 461 462 port@1 { 463 reg = <1>; 464 465 hugo_funnel_in_port1: endpoint { 466 /* M7 input */ 467 }; 468 }; 469 470 port@2 { 471 reg = <2>; 472 473 hugo_funnel_in_port2: endpoint { 474 /* DSP input */ 475 }; 476 }; 477 /* the other input ports are not connect to anything */ 478 }; 479 480 out-ports { 481 port { 482 hugo_funnel_out_port0: endpoint { 483 remote-endpoint = <&etf_in_port>; 484 }; 485 }; 486 }; 487 }; 488 489 etf@28c04000 { 490 compatible = "arm,coresight-tmc", "arm,primecell"; 491 reg = <0x28c04000 0x1000>; 492 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 493 clock-names = "apb_pclk"; 494 495 in-ports { 496 port { 497 etf_in_port: endpoint { 498 remote-endpoint = <&hugo_funnel_out_port0>; 499 }; 500 }; 501 }; 502 503 out-ports { 504 port { 505 etf_out_port: endpoint { 506 remote-endpoint = <&etr_in_port>; 507 }; 508 }; 509 }; 510 }; 511 512 etr@28c06000 { 513 compatible = "arm,coresight-tmc", "arm,primecell"; 514 reg = <0x28c06000 0x1000>; 515 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 516 clock-names = "apb_pclk"; 517 518 in-ports { 519 port { 520 etr_in_port: endpoint { 521 remote-endpoint = <&etf_out_port>; 522 }; 523 }; 524 }; 525 }; 526 527 aips1: bus@30000000 { 528 compatible = "fsl,aips-bus", "simple-bus"; 529 reg = <0x30000000 0x400000>; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges; 533 534 gpio1: gpio@30200000 { 535 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 536 reg = <0x30200000 0x10000>; 537 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 interrupt-controller; 543 #interrupt-cells = <2>; 544 gpio-ranges = <&iomuxc 0 5 30>; 545 }; 546 547 gpio2: gpio@30210000 { 548 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 549 reg = <0x30210000 0x10000>; 550 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 553 gpio-controller; 554 #gpio-cells = <2>; 555 interrupt-controller; 556 #interrupt-cells = <2>; 557 gpio-ranges = <&iomuxc 0 35 21>; 558 }; 559 560 gpio3: gpio@30220000 { 561 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 562 reg = <0x30220000 0x10000>; 563 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 566 gpio-controller; 567 #gpio-cells = <2>; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 571 }; 572 573 gpio4: gpio@30230000 { 574 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 575 reg = <0x30230000 0x10000>; 576 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 579 gpio-controller; 580 #gpio-cells = <2>; 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 gpio-ranges = <&iomuxc 0 82 32>; 584 }; 585 586 gpio5: gpio@30240000 { 587 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 588 reg = <0x30240000 0x10000>; 589 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 592 gpio-controller; 593 #gpio-cells = <2>; 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 gpio-ranges = <&iomuxc 0 114 30>; 597 }; 598 599 tmu: tmu@30260000 { 600 compatible = "fsl,imx8mp-tmu"; 601 reg = <0x30260000 0x10000>; 602 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 603 nvmem-cells = <&tmu_calib>; 604 nvmem-cell-names = "calib"; 605 #thermal-sensor-cells = <1>; 606 }; 607 608 wdog1: watchdog@30280000 { 609 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 610 reg = <0x30280000 0x10000>; 611 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 613 status = "disabled"; 614 }; 615 616 wdog2: watchdog@30290000 { 617 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 618 reg = <0x30290000 0x10000>; 619 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 621 status = "disabled"; 622 }; 623 624 wdog3: watchdog@302a0000 { 625 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 626 reg = <0x302a0000 0x10000>; 627 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 629 status = "disabled"; 630 }; 631 632 gpt1: timer@302d0000 { 633 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 634 reg = <0x302d0000 0x10000>; 635 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 637 clock-names = "ipg", "per"; 638 }; 639 640 gpt2: timer@302e0000 { 641 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 642 reg = <0x302e0000 0x10000>; 643 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 645 clock-names = "ipg", "per"; 646 }; 647 648 gpt3: timer@302f0000 { 649 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 650 reg = <0x302f0000 0x10000>; 651 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 653 clock-names = "ipg", "per"; 654 }; 655 656 iomuxc: pinctrl@30330000 { 657 compatible = "fsl,imx8mp-iomuxc"; 658 reg = <0x30330000 0x10000>; 659 }; 660 661 gpr: syscon@30340000 { 662 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 663 reg = <0x30340000 0x10000>; 664 }; 665 666 ocotp: efuse@30350000 { 667 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 668 reg = <0x30350000 0x10000>; 669 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 670 /* For nvmem subnodes */ 671 #address-cells = <1>; 672 #size-cells = <1>; 673 674 /* 675 * The register address below maps to the MX8M 676 * Fusemap Description Table entries this way. 677 * Assuming 678 * reg = <ADDR SIZE>; 679 * then 680 * Fuse Address = (ADDR * 4) + 0x400 681 * Note that if SIZE is greater than 4, then 682 * each subsequent fuse is located at offset 683 * +0x10 in Fusemap Description Table (e.g. 684 * reg = <0x8 0x8> describes fuses 0x420 and 685 * 0x430). 686 */ 687 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 688 reg = <0x8 0x8>; 689 }; 690 691 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 692 reg = <0x10 4>; 693 }; 694 695 eth_mac1: mac-address@90 { /* 0x640 */ 696 reg = <0x90 6>; 697 }; 698 699 eth_mac2: mac-address@96 { /* 0x658 */ 700 reg = <0x96 6>; 701 }; 702 703 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 704 reg = <0x264 0x10>; 705 }; 706 }; 707 708 anatop: clock-controller@30360000 { 709 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 710 reg = <0x30360000 0x10000>; 711 #clock-cells = <1>; 712 }; 713 714 snvs: snvs@30370000 { 715 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 716 reg = <0x30370000 0x10000>; 717 718 snvs_rtc: snvs-rtc-lp { 719 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 720 regmap = <&snvs>; 721 offset = <0x34>; 722 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 725 clock-names = "snvs-rtc"; 726 }; 727 728 snvs_pwrkey: snvs-powerkey { 729 compatible = "fsl,sec-v4.0-pwrkey"; 730 regmap = <&snvs>; 731 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 733 clock-names = "snvs-pwrkey"; 734 linux,keycode = <KEY_POWER>; 735 wakeup-source; 736 status = "disabled"; 737 }; 738 739 snvs_lpgpr: snvs-lpgpr { 740 compatible = "fsl,imx8mp-snvs-lpgpr", 741 "fsl,imx7d-snvs-lpgpr"; 742 }; 743 }; 744 745 clk: clock-controller@30380000 { 746 compatible = "fsl,imx8mp-ccm"; 747 reg = <0x30380000 0x10000>; 748 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 750 #clock-cells = <1>; 751 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 752 <&clk_ext3>, <&clk_ext4>; 753 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 754 "clk_ext3", "clk_ext4"; 755 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 756 <&clk IMX8MP_CLK_A53_CORE>, 757 <&clk IMX8MP_CLK_NOC>, 758 <&clk IMX8MP_CLK_NOC_IO>, 759 <&clk IMX8MP_CLK_GIC>; 760 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 761 <&clk IMX8MP_ARM_PLL_OUT>, 762 <&clk IMX8MP_SYS_PLL2_1000M>, 763 <&clk IMX8MP_SYS_PLL1_800M>, 764 <&clk IMX8MP_SYS_PLL2_500M>; 765 assigned-clock-rates = <0>, <0>, 766 <1000000000>, 767 <800000000>, 768 <500000000>; 769 }; 770 771 src: reset-controller@30390000 { 772 compatible = "fsl,imx8mp-src", "syscon"; 773 reg = <0x30390000 0x10000>; 774 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 775 #reset-cells = <1>; 776 }; 777 778 gpc: gpc@303a0000 { 779 compatible = "fsl,imx8mp-gpc"; 780 reg = <0x303a0000 0x1000>; 781 interrupt-parent = <&gic>; 782 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 783 interrupt-controller; 784 #interrupt-cells = <3>; 785 786 pgc { 787 #address-cells = <1>; 788 #size-cells = <0>; 789 790 pgc_mipi_phy1: power-domain@0 { 791 #power-domain-cells = <0>; 792 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 793 }; 794 795 pgc_pcie_phy: power-domain@1 { 796 #power-domain-cells = <0>; 797 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 798 }; 799 800 pgc_usb1_phy: power-domain@2 { 801 #power-domain-cells = <0>; 802 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 803 }; 804 805 pgc_usb2_phy: power-domain@3 { 806 #power-domain-cells = <0>; 807 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 808 }; 809 810 pgc_mlmix: power-domain@4 { 811 #power-domain-cells = <0>; 812 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 813 clocks = <&clk IMX8MP_CLK_ML_AXI>, 814 <&clk IMX8MP_CLK_ML_AHB>, 815 <&clk IMX8MP_CLK_NPU_ROOT>; 816 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 817 <&clk IMX8MP_CLK_ML_AXI>, 818 <&clk IMX8MP_CLK_ML_AHB>; 819 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 820 <&clk IMX8MP_SYS_PLL1_800M>, 821 <&clk IMX8MP_SYS_PLL1_800M>; 822 assigned-clock-rates = <800000000>, 823 <800000000>, 824 <300000000>; 825 }; 826 827 pgc_audio: power-domain@5 { 828 #power-domain-cells = <0>; 829 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 830 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 831 <&clk IMX8MP_CLK_AUDIO_AXI>; 832 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 833 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 834 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 835 <&clk IMX8MP_SYS_PLL1_800M>; 836 assigned-clock-rates = <400000000>, 837 <800000000>; 838 }; 839 840 pgc_gpu2d: power-domain@6 { 841 #power-domain-cells = <0>; 842 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 843 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 844 power-domains = <&pgc_gpumix>; 845 }; 846 847 pgc_gpumix: power-domain@7 { 848 #power-domain-cells = <0>; 849 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 850 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 851 <&clk IMX8MP_CLK_GPU_AHB>; 852 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 853 <&clk IMX8MP_CLK_GPU_AHB>; 854 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 855 <&clk IMX8MP_SYS_PLL1_800M>; 856 assigned-clock-rates = <800000000>, <400000000>; 857 }; 858 859 pgc_vpumix: power-domain@8 { 860 #power-domain-cells = <0>; 861 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 862 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 863 }; 864 865 pgc_gpu3d: power-domain@9 { 866 #power-domain-cells = <0>; 867 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 868 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 869 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 870 power-domains = <&pgc_gpumix>; 871 }; 872 873 pgc_mediamix: power-domain@10 { 874 #power-domain-cells = <0>; 875 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 876 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 877 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 878 }; 879 880 pgc_vpu_g1: power-domain@11 { 881 #power-domain-cells = <0>; 882 power-domains = <&pgc_vpumix>; 883 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 884 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 885 }; 886 887 pgc_vpu_g2: power-domain@12 { 888 #power-domain-cells = <0>; 889 power-domains = <&pgc_vpumix>; 890 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 891 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 892 893 }; 894 895 pgc_vpu_vc8000e: power-domain@13 { 896 #power-domain-cells = <0>; 897 power-domains = <&pgc_vpumix>; 898 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 899 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 900 }; 901 902 pgc_hdmimix: power-domain@14 { 903 #power-domain-cells = <0>; 904 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; 905 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, 906 <&clk IMX8MP_CLK_HDMI_APB>; 907 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 908 <&clk IMX8MP_CLK_HDMI_APB>; 909 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, 910 <&clk IMX8MP_SYS_PLL1_133M>; 911 assigned-clock-rates = <500000000>, <133000000>; 912 }; 913 914 pgc_hdmi_phy: power-domain@15 { 915 #power-domain-cells = <0>; 916 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; 917 }; 918 919 pgc_mipi_phy2: power-domain@16 { 920 #power-domain-cells = <0>; 921 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 922 }; 923 924 pgc_hsiomix: power-domain@17 { 925 #power-domain-cells = <0>; 926 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 927 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 928 <&clk IMX8MP_CLK_HSIO_ROOT>; 929 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 930 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 931 assigned-clock-rates = <500000000>; 932 }; 933 934 pgc_ispdwp: power-domain@18 { 935 #power-domain-cells = <0>; 936 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 937 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 938 }; 939 }; 940 }; 941 }; 942 943 aips2: bus@30400000 { 944 compatible = "fsl,aips-bus", "simple-bus"; 945 reg = <0x30400000 0x400000>; 946 #address-cells = <1>; 947 #size-cells = <1>; 948 ranges; 949 950 pwm1: pwm@30660000 { 951 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 952 reg = <0x30660000 0x10000>; 953 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 955 <&clk IMX8MP_CLK_PWM1_ROOT>; 956 clock-names = "ipg", "per"; 957 #pwm-cells = <3>; 958 status = "disabled"; 959 }; 960 961 pwm2: pwm@30670000 { 962 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 963 reg = <0x30670000 0x10000>; 964 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 966 <&clk IMX8MP_CLK_PWM2_ROOT>; 967 clock-names = "ipg", "per"; 968 #pwm-cells = <3>; 969 status = "disabled"; 970 }; 971 972 pwm3: pwm@30680000 { 973 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 974 reg = <0x30680000 0x10000>; 975 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 977 <&clk IMX8MP_CLK_PWM3_ROOT>; 978 clock-names = "ipg", "per"; 979 #pwm-cells = <3>; 980 status = "disabled"; 981 }; 982 983 pwm4: pwm@30690000 { 984 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 985 reg = <0x30690000 0x10000>; 986 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 988 <&clk IMX8MP_CLK_PWM4_ROOT>; 989 clock-names = "ipg", "per"; 990 #pwm-cells = <3>; 991 status = "disabled"; 992 }; 993 994 system_counter: timer@306a0000 { 995 compatible = "nxp,sysctr-timer"; 996 reg = <0x306a0000 0x20000>; 997 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&osc_24m>; 999 clock-names = "per"; 1000 }; 1001 1002 gpt6: timer@306e0000 { 1003 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1004 reg = <0x306e0000 0x10000>; 1005 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 1007 clock-names = "ipg", "per"; 1008 }; 1009 1010 gpt5: timer@306f0000 { 1011 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1012 reg = <0x306f0000 0x10000>; 1013 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 1015 clock-names = "ipg", "per"; 1016 }; 1017 1018 gpt4: timer@30700000 { 1019 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1020 reg = <0x30700000 0x10000>; 1021 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 1023 clock-names = "ipg", "per"; 1024 }; 1025 }; 1026 1027 aips3: bus@30800000 { 1028 compatible = "fsl,aips-bus", "simple-bus"; 1029 reg = <0x30800000 0x400000>; 1030 #address-cells = <1>; 1031 #size-cells = <1>; 1032 ranges; 1033 1034 spba-bus@30800000 { 1035 compatible = "fsl,spba-bus", "simple-bus"; 1036 reg = <0x30800000 0x100000>; 1037 #address-cells = <1>; 1038 #size-cells = <1>; 1039 ranges; 1040 1041 ecspi1: spi@30820000 { 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1045 reg = <0x30820000 0x10000>; 1046 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1048 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1049 clock-names = "ipg", "per"; 1050 assigned-clock-rates = <80000000>; 1051 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1052 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1053 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1054 dma-names = "rx", "tx"; 1055 status = "disabled"; 1056 }; 1057 1058 ecspi2: spi@30830000 { 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1062 reg = <0x30830000 0x10000>; 1063 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1065 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1066 clock-names = "ipg", "per"; 1067 assigned-clock-rates = <80000000>; 1068 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1069 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1070 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1071 dma-names = "rx", "tx"; 1072 status = "disabled"; 1073 }; 1074 1075 ecspi3: spi@30840000 { 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1079 reg = <0x30840000 0x10000>; 1080 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1082 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1083 clock-names = "ipg", "per"; 1084 assigned-clock-rates = <80000000>; 1085 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1086 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1087 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1088 dma-names = "rx", "tx"; 1089 status = "disabled"; 1090 }; 1091 1092 uart1: serial@30860000 { 1093 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1094 reg = <0x30860000 0x10000>; 1095 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1097 <&clk IMX8MP_CLK_UART1_ROOT>; 1098 clock-names = "ipg", "per"; 1099 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1100 dma-names = "rx", "tx"; 1101 status = "disabled"; 1102 }; 1103 1104 uart3: serial@30880000 { 1105 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1106 reg = <0x30880000 0x10000>; 1107 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1109 <&clk IMX8MP_CLK_UART3_ROOT>; 1110 clock-names = "ipg", "per"; 1111 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1112 dma-names = "rx", "tx"; 1113 status = "disabled"; 1114 }; 1115 1116 uart2: serial@30890000 { 1117 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1118 reg = <0x30890000 0x10000>; 1119 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1121 <&clk IMX8MP_CLK_UART2_ROOT>; 1122 clock-names = "ipg", "per"; 1123 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1124 dma-names = "rx", "tx"; 1125 status = "disabled"; 1126 }; 1127 1128 flexcan1: can@308c0000 { 1129 compatible = "fsl,imx8mp-flexcan"; 1130 reg = <0x308c0000 0x10000>; 1131 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1133 <&clk IMX8MP_CLK_CAN1_ROOT>; 1134 clock-names = "ipg", "per"; 1135 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1136 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1137 assigned-clock-rates = <40000000>; 1138 fsl,clk-source = /bits/ 8 <0>; 1139 fsl,stop-mode = <&gpr 0x10 4>; 1140 status = "disabled"; 1141 }; 1142 1143 flexcan2: can@308d0000 { 1144 compatible = "fsl,imx8mp-flexcan"; 1145 reg = <0x308d0000 0x10000>; 1146 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1148 <&clk IMX8MP_CLK_CAN2_ROOT>; 1149 clock-names = "ipg", "per"; 1150 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1151 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1152 assigned-clock-rates = <40000000>; 1153 fsl,clk-source = /bits/ 8 <0>; 1154 fsl,stop-mode = <&gpr 0x10 5>; 1155 status = "disabled"; 1156 }; 1157 }; 1158 1159 crypto: crypto@30900000 { 1160 compatible = "fsl,sec-v4.0"; 1161 #address-cells = <1>; 1162 #size-cells = <1>; 1163 reg = <0x30900000 0x40000>; 1164 ranges = <0 0x30900000 0x40000>; 1165 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&clk IMX8MP_CLK_AHB>, 1167 <&clk IMX8MP_CLK_IPG_ROOT>; 1168 clock-names = "aclk", "ipg"; 1169 1170 sec_jr0: jr@1000 { 1171 compatible = "fsl,sec-v4.0-job-ring"; 1172 reg = <0x1000 0x1000>; 1173 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1174 status = "disabled"; 1175 }; 1176 1177 sec_jr1: jr@2000 { 1178 compatible = "fsl,sec-v4.0-job-ring"; 1179 reg = <0x2000 0x1000>; 1180 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1181 }; 1182 1183 sec_jr2: jr@3000 { 1184 compatible = "fsl,sec-v4.0-job-ring"; 1185 reg = <0x3000 0x1000>; 1186 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1187 }; 1188 }; 1189 1190 i2c1: i2c@30a20000 { 1191 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 reg = <0x30a20000 0x10000>; 1195 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c2: i2c@30a30000 { 1201 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 reg = <0x30a30000 0x10000>; 1205 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1207 status = "disabled"; 1208 }; 1209 1210 i2c3: i2c@30a40000 { 1211 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 reg = <0x30a40000 0x10000>; 1215 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1217 status = "disabled"; 1218 }; 1219 1220 i2c4: i2c@30a50000 { 1221 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 reg = <0x30a50000 0x10000>; 1225 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1226 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1227 status = "disabled"; 1228 }; 1229 1230 uart4: serial@30a60000 { 1231 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1232 reg = <0x30a60000 0x10000>; 1233 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1235 <&clk IMX8MP_CLK_UART4_ROOT>; 1236 clock-names = "ipg", "per"; 1237 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1238 dma-names = "rx", "tx"; 1239 status = "disabled"; 1240 }; 1241 1242 mu: mailbox@30aa0000 { 1243 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1244 reg = <0x30aa0000 0x10000>; 1245 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1247 #mbox-cells = <2>; 1248 }; 1249 1250 mu2: mailbox@30e60000 { 1251 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1252 reg = <0x30e60000 0x10000>; 1253 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1254 #mbox-cells = <2>; 1255 status = "disabled"; 1256 }; 1257 1258 i2c5: i2c@30ad0000 { 1259 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 reg = <0x30ad0000 0x10000>; 1263 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1265 status = "disabled"; 1266 }; 1267 1268 i2c6: i2c@30ae0000 { 1269 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 reg = <0x30ae0000 0x10000>; 1273 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1275 status = "disabled"; 1276 }; 1277 1278 usdhc1: mmc@30b40000 { 1279 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1280 reg = <0x30b40000 0x10000>; 1281 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1283 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1284 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1285 clock-names = "ipg", "ahb", "per"; 1286 fsl,tuning-start-tap = <20>; 1287 fsl,tuning-step = <2>; 1288 bus-width = <4>; 1289 status = "disabled"; 1290 }; 1291 1292 usdhc2: mmc@30b50000 { 1293 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1294 reg = <0x30b50000 0x10000>; 1295 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1296 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1297 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1298 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1299 clock-names = "ipg", "ahb", "per"; 1300 fsl,tuning-start-tap = <20>; 1301 fsl,tuning-step = <2>; 1302 bus-width = <4>; 1303 status = "disabled"; 1304 }; 1305 1306 usdhc3: mmc@30b60000 { 1307 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1308 reg = <0x30b60000 0x10000>; 1309 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1311 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1312 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1313 clock-names = "ipg", "ahb", "per"; 1314 fsl,tuning-start-tap = <20>; 1315 fsl,tuning-step = <2>; 1316 bus-width = <4>; 1317 status = "disabled"; 1318 }; 1319 1320 flexspi: spi@30bb0000 { 1321 compatible = "nxp,imx8mp-fspi"; 1322 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1323 reg-names = "fspi_base", "fspi_mmap"; 1324 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1326 <&clk IMX8MP_CLK_QSPI_ROOT>; 1327 clock-names = "fspi_en", "fspi"; 1328 assigned-clock-rates = <80000000>; 1329 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 sdma1: dma-controller@30bd0000 { 1336 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1337 reg = <0x30bd0000 0x10000>; 1338 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1340 <&clk IMX8MP_CLK_AHB>; 1341 clock-names = "ipg", "ahb"; 1342 #dma-cells = <3>; 1343 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1344 }; 1345 1346 fec: ethernet@30be0000 { 1347 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1348 reg = <0x30be0000 0x10000>; 1349 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1354 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1355 <&clk IMX8MP_CLK_ENET_TIMER>, 1356 <&clk IMX8MP_CLK_ENET_REF>, 1357 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1358 clock-names = "ipg", "ahb", "ptp", 1359 "enet_clk_ref", "enet_out"; 1360 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1361 <&clk IMX8MP_CLK_ENET_TIMER>, 1362 <&clk IMX8MP_CLK_ENET_REF>, 1363 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1364 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1365 <&clk IMX8MP_SYS_PLL2_100M>, 1366 <&clk IMX8MP_SYS_PLL2_125M>, 1367 <&clk IMX8MP_SYS_PLL2_50M>; 1368 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1369 fsl,num-tx-queues = <3>; 1370 fsl,num-rx-queues = <3>; 1371 nvmem-cells = <ð_mac1>; 1372 nvmem-cell-names = "mac-address"; 1373 fsl,stop-mode = <&gpr 0x10 3>; 1374 status = "disabled"; 1375 }; 1376 1377 eqos: ethernet@30bf0000 { 1378 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1379 reg = <0x30bf0000 0x10000>; 1380 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1382 interrupt-names = "macirq", "eth_wake_irq"; 1383 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1384 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1385 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1386 <&clk IMX8MP_CLK_ENET_QOS>; 1387 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1388 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1389 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1390 <&clk IMX8MP_CLK_ENET_QOS>; 1391 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1392 <&clk IMX8MP_SYS_PLL2_100M>, 1393 <&clk IMX8MP_SYS_PLL2_125M>; 1394 assigned-clock-rates = <0>, <100000000>, <125000000>; 1395 nvmem-cells = <ð_mac2>; 1396 nvmem-cell-names = "mac-address"; 1397 intf_mode = <&gpr 0x4>; 1398 status = "disabled"; 1399 }; 1400 }; 1401 1402 aips5: bus@30c00000 { 1403 compatible = "fsl,aips-bus", "simple-bus"; 1404 reg = <0x30c00000 0x400000>; 1405 #address-cells = <1>; 1406 #size-cells = <1>; 1407 ranges; 1408 1409 spba-bus@30c00000 { 1410 compatible = "fsl,spba-bus", "simple-bus"; 1411 reg = <0x30c00000 0x100000>; 1412 #address-cells = <1>; 1413 #size-cells = <1>; 1414 ranges; 1415 1416 sai1: sai@30c10000 { 1417 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1418 reg = <0x30c10000 0x10000>; 1419 #sound-dai-cells = <0>; 1420 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1421 <&clk IMX8MP_CLK_DUMMY>, 1422 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1423 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1424 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1425 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1426 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1427 dma-names = "rx", "tx"; 1428 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1429 status = "disabled"; 1430 }; 1431 1432 sai2: sai@30c20000 { 1433 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1434 reg = <0x30c20000 0x10000>; 1435 #sound-dai-cells = <0>; 1436 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1437 <&clk IMX8MP_CLK_DUMMY>, 1438 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1439 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1440 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1441 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1442 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1443 dma-names = "rx", "tx"; 1444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1445 status = "disabled"; 1446 }; 1447 1448 sai3: sai@30c30000 { 1449 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1450 reg = <0x30c30000 0x10000>; 1451 #sound-dai-cells = <0>; 1452 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1453 <&clk IMX8MP_CLK_DUMMY>, 1454 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1455 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1456 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1457 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1458 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1459 dma-names = "rx", "tx"; 1460 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1461 status = "disabled"; 1462 }; 1463 1464 sai5: sai@30c50000 { 1465 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1466 reg = <0x30c50000 0x10000>; 1467 #sound-dai-cells = <0>; 1468 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1469 <&clk IMX8MP_CLK_DUMMY>, 1470 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1471 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1472 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1473 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1474 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1475 dma-names = "rx", "tx"; 1476 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1477 status = "disabled"; 1478 }; 1479 1480 sai6: sai@30c60000 { 1481 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1482 reg = <0x30c60000 0x10000>; 1483 #sound-dai-cells = <0>; 1484 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1485 <&clk IMX8MP_CLK_DUMMY>, 1486 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1487 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1488 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1489 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1490 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1491 dma-names = "rx", "tx"; 1492 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1493 status = "disabled"; 1494 }; 1495 1496 sai7: sai@30c80000 { 1497 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1498 reg = <0x30c80000 0x10000>; 1499 #sound-dai-cells = <0>; 1500 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1501 <&clk IMX8MP_CLK_DUMMY>, 1502 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1503 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1504 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1505 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1506 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1507 dma-names = "rx", "tx"; 1508 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1509 status = "disabled"; 1510 }; 1511 1512 easrc: easrc@30c90000 { 1513 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; 1514 reg = <0x30c90000 0x10000>; 1515 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; 1517 clock-names = "mem"; 1518 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 1519 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 1520 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 1521 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 1522 dma-names = "ctx0_rx", "ctx0_tx", 1523 "ctx1_rx", "ctx1_tx", 1524 "ctx2_rx", "ctx2_tx", 1525 "ctx3_rx", "ctx3_tx"; 1526 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 1527 fsl,asrc-rate = <8000>; 1528 fsl,asrc-format = <2>; 1529 status = "disabled"; 1530 }; 1531 1532 micfil: audio-controller@30ca0000 { 1533 compatible = "fsl,imx8mp-micfil"; 1534 reg = <0x30ca0000 0x10000>; 1535 #sound-dai-cells = <0>; 1536 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1540 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, 1541 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, 1542 <&clk IMX8MP_AUDIO_PLL1_OUT>, 1543 <&clk IMX8MP_AUDIO_PLL2_OUT>, 1544 <&clk IMX8MP_CLK_EXT3>; 1545 clock-names = "ipg_clk", "ipg_clk_app", 1546 "pll8k", "pll11k", "clkext3"; 1547 dmas = <&sdma2 24 25 0x80000000>; 1548 dma-names = "rx"; 1549 status = "disabled"; 1550 }; 1551 1552 aud2htx: aud2htx@30cb0000 { 1553 compatible = "fsl,imx8mp-aud2htx"; 1554 reg = <0x30cb0000 0x10000>; 1555 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1556 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; 1557 clock-names = "bus"; 1558 dmas = <&sdma2 26 2 0>; 1559 dma-names = "tx"; 1560 status = "disabled"; 1561 }; 1562 1563 xcvr: xcvr@30cc0000 { 1564 compatible = "fsl,imx8mp-xcvr"; 1565 reg = <0x30cc0000 0x800>, 1566 <0x30cc0800 0x400>, 1567 <0x30cc0c00 0x080>, 1568 <0x30cc0e00 0x080>; 1569 reg-names = "ram", "regs", "rxfifo", 1570 "txfifo"; 1571 interrupts = /* XCVR IRQ 0 */ 1572 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1573 /* XCVR IRQ 1 */ 1574 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1575 /* XCVR PHY - SPDIF wakeup IRQ */ 1576 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1577 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, 1578 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, 1579 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, 1580 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; 1581 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1582 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; 1583 dma-names = "rx", "tx"; 1584 resets = <&audio_blk_ctrl 0>; 1585 status = "disabled"; 1586 }; 1587 }; 1588 1589 sdma3: dma-controller@30e00000 { 1590 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1591 reg = <0x30e00000 0x10000>; 1592 #dma-cells = <3>; 1593 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1594 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1595 clock-names = "ipg", "ahb"; 1596 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1597 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1598 }; 1599 1600 sdma2: dma-controller@30e10000 { 1601 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1602 reg = <0x30e10000 0x10000>; 1603 #dma-cells = <3>; 1604 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1605 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1606 clock-names = "ipg", "ahb"; 1607 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1608 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1609 }; 1610 1611 audio_blk_ctrl: clock-controller@30e20000 { 1612 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1613 reg = <0x30e20000 0x10000>; 1614 #clock-cells = <1>; 1615 #reset-cells = <1>; 1616 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1617 <&clk IMX8MP_CLK_SAI1>, 1618 <&clk IMX8MP_CLK_SAI2>, 1619 <&clk IMX8MP_CLK_SAI3>, 1620 <&clk IMX8MP_CLK_SAI5>, 1621 <&clk IMX8MP_CLK_SAI6>, 1622 <&clk IMX8MP_CLK_SAI7>, 1623 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; 1624 clock-names = "ahb", 1625 "sai1", "sai2", "sai3", 1626 "sai5", "sai6", "sai7", "axi"; 1627 power-domains = <&pgc_audio>; 1628 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, 1629 <&clk IMX8MP_AUDIO_PLL2>; 1630 assigned-clock-rates = <393216000>, <361267200>; 1631 }; 1632 }; 1633 1634 noc: interconnect@32700000 { 1635 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1636 reg = <0x32700000 0x100000>; 1637 clocks = <&clk IMX8MP_CLK_NOC>; 1638 #interconnect-cells = <1>; 1639 operating-points-v2 = <&noc_opp_table>; 1640 1641 noc_opp_table: opp-table { 1642 compatible = "operating-points-v2"; 1643 1644 opp-200000000 { 1645 opp-hz = /bits/ 64 <200000000>; 1646 }; 1647 1648 opp-1000000000 { 1649 opp-hz = /bits/ 64 <1000000000>; 1650 }; 1651 }; 1652 }; 1653 1654 aips4: bus@32c00000 { 1655 compatible = "fsl,aips-bus", "simple-bus"; 1656 reg = <0x32c00000 0x400000>; 1657 #address-cells = <1>; 1658 #size-cells = <1>; 1659 ranges; 1660 1661 isi_0: isi@32e00000 { 1662 compatible = "fsl,imx8mp-isi"; 1663 reg = <0x32e00000 0x4000>; 1664 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1666 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1667 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1668 clock-names = "axi", "apb"; 1669 fsl,blk-ctrl = <&media_blk_ctrl>; 1670 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1671 status = "disabled"; 1672 1673 ports { 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 1677 port@0 { 1678 reg = <0>; 1679 1680 isi_in_0: endpoint { 1681 remote-endpoint = <&mipi_csi_0_out>; 1682 }; 1683 }; 1684 1685 port@1 { 1686 reg = <1>; 1687 1688 isi_in_1: endpoint { 1689 remote-endpoint = <&mipi_csi_1_out>; 1690 }; 1691 }; 1692 }; 1693 }; 1694 1695 isp_0: isp@32e10000 { 1696 compatible = "fsl,imx8mp-isp"; 1697 reg = <0x32e10000 0x10000>; 1698 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1699 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1700 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1701 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1702 clock-names = "isp", "aclk", "hclk"; 1703 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; 1704 fsl,blk-ctrl = <&media_blk_ctrl 0>; 1705 status = "disabled"; 1706 1707 ports { 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 1711 port@1 { 1712 reg = <1>; 1713 }; 1714 }; 1715 }; 1716 1717 isp_1: isp@32e20000 { 1718 compatible = "fsl,imx8mp-isp"; 1719 reg = <0x32e20000 0x10000>; 1720 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1722 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1723 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1724 clock-names = "isp", "aclk", "hclk"; 1725 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; 1726 fsl,blk-ctrl = <&media_blk_ctrl 1>; 1727 status = "disabled"; 1728 1729 ports { 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 1733 port@1 { 1734 reg = <1>; 1735 }; 1736 }; 1737 }; 1738 1739 dewarp: dwe@32e30000 { 1740 compatible = "nxp,imx8mp-dw100"; 1741 reg = <0x32e30000 0x10000>; 1742 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1743 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1744 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1745 clock-names = "axi", "ahb"; 1746 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1747 }; 1748 1749 mipi_csi_0: csi@32e40000 { 1750 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1751 reg = <0x32e40000 0x10000>; 1752 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1753 clock-frequency = <250000000>; 1754 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1755 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1756 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1757 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1758 clock-names = "pclk", "wrap", "phy", "axi"; 1759 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, 1760 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1761 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1762 <&clk IMX8MP_CLK_24M>; 1763 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1764 status = "disabled"; 1765 1766 ports { 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 1770 port@0 { 1771 reg = <0>; 1772 }; 1773 1774 port@1 { 1775 reg = <1>; 1776 1777 mipi_csi_0_out: endpoint { 1778 remote-endpoint = <&isi_in_0>; 1779 }; 1780 }; 1781 }; 1782 }; 1783 1784 mipi_csi_1: csi@32e50000 { 1785 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1786 reg = <0x32e50000 0x10000>; 1787 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1788 clock-frequency = <250000000>; 1789 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1790 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1791 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1792 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1793 clock-names = "pclk", "wrap", "phy", "axi"; 1794 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, 1795 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1796 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1797 <&clk IMX8MP_CLK_24M>; 1798 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1799 status = "disabled"; 1800 1801 ports { 1802 #address-cells = <1>; 1803 #size-cells = <0>; 1804 1805 port@0 { 1806 reg = <0>; 1807 }; 1808 1809 port@1 { 1810 reg = <1>; 1811 1812 mipi_csi_1_out: endpoint { 1813 remote-endpoint = <&isi_in_1>; 1814 }; 1815 }; 1816 }; 1817 }; 1818 1819 mipi_dsi: dsi@32e60000 { 1820 compatible = "fsl,imx8mp-mipi-dsim"; 1821 reg = <0x32e60000 0x400>; 1822 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1823 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1824 clock-names = "bus_clk", "sclk_mipi"; 1825 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1826 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1827 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1828 <&clk IMX8MP_CLK_24M>; 1829 assigned-clock-rates = <200000000>, <24000000>; 1830 samsung,pll-clock-frequency = <24000000>; 1831 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1832 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1833 status = "disabled"; 1834 1835 ports { 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 1839 port@0 { 1840 reg = <0>; 1841 1842 dsim_from_lcdif1: endpoint { 1843 remote-endpoint = <&lcdif1_to_dsim>; 1844 }; 1845 }; 1846 1847 port@1 { 1848 reg = <1>; 1849 1850 mipi_dsi_out: endpoint { 1851 }; 1852 }; 1853 }; 1854 }; 1855 1856 lcdif1: display-controller@32e80000 { 1857 compatible = "fsl,imx8mp-lcdif"; 1858 reg = <0x32e80000 0x10000>; 1859 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1860 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1861 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1862 clock-names = "pix", "axi", "disp_axi"; 1863 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1864 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1865 status = "disabled"; 1866 1867 port { 1868 lcdif1_to_dsim: endpoint { 1869 remote-endpoint = <&dsim_from_lcdif1>; 1870 }; 1871 }; 1872 }; 1873 1874 lcdif2: display-controller@32e90000 { 1875 compatible = "fsl,imx8mp-lcdif"; 1876 reg = <0x32e90000 0x10000>; 1877 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1878 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1879 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1880 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1881 clock-names = "pix", "axi", "disp_axi"; 1882 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1883 status = "disabled"; 1884 1885 port { 1886 lcdif2_to_ldb: endpoint { 1887 remote-endpoint = <&ldb_from_lcdif2>; 1888 }; 1889 }; 1890 }; 1891 1892 media_blk_ctrl: blk-ctrl@32ec0000 { 1893 compatible = "fsl,imx8mp-media-blk-ctrl", 1894 "syscon"; 1895 reg = <0x32ec0000 0x10000>; 1896 #address-cells = <1>; 1897 #size-cells = <1>; 1898 power-domains = <&pgc_mediamix>, 1899 <&pgc_mipi_phy1>, 1900 <&pgc_mipi_phy1>, 1901 <&pgc_mediamix>, 1902 <&pgc_mediamix>, 1903 <&pgc_mipi_phy2>, 1904 <&pgc_mediamix>, 1905 <&pgc_ispdwp>, 1906 <&pgc_ispdwp>, 1907 <&pgc_mipi_phy2>; 1908 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1909 "lcdif1", "isi", "mipi-csi2", 1910 "lcdif2", "isp", "dwe", 1911 "mipi-dsi2"; 1912 interconnects = 1913 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1914 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1915 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1916 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1917 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1918 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1919 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1920 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1921 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1922 "isi1", "isi2", "isp0", "isp1", 1923 "dwe"; 1924 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1925 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1926 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1927 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1928 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1929 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1930 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1931 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1932 clock-names = "apb", "axi", "cam1", "cam2", 1933 "disp1", "disp2", "isp", "phy"; 1934 1935 /* 1936 * The ISP maximum frequency is 400MHz in normal mode 1937 * and 500MHz in overdrive mode. The 400MHz operating 1938 * point hasn't been successfully tested yet, so set 1939 * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. 1940 */ 1941 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1942 <&clk IMX8MP_CLK_MEDIA_APB>, 1943 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1944 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1945 <&clk IMX8MP_CLK_MEDIA_ISP>, 1946 <&clk IMX8MP_VIDEO_PLL1>; 1947 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1948 <&clk IMX8MP_SYS_PLL1_800M>, 1949 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1950 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1951 <&clk IMX8MP_SYS_PLL2_500M>; 1952 assigned-clock-rates = <500000000>, <200000000>, 1953 <0>, <0>, <500000000>, 1954 <1039500000>; 1955 #power-domain-cells = <1>; 1956 1957 lvds_bridge: bridge@5c { 1958 compatible = "fsl,imx8mp-ldb"; 1959 reg = <0x5c 0x4>, <0x128 0x4>; 1960 reg-names = "ldb", "lvds"; 1961 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; 1962 clock-names = "ldb"; 1963 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1964 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1965 status = "disabled"; 1966 1967 ports { 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 1971 port@0 { 1972 reg = <0>; 1973 1974 ldb_from_lcdif2: endpoint { 1975 remote-endpoint = <&lcdif2_to_ldb>; 1976 }; 1977 }; 1978 1979 port@1 { 1980 reg = <1>; 1981 1982 ldb_lvds_ch0: endpoint { 1983 }; 1984 }; 1985 1986 port@2 { 1987 reg = <2>; 1988 1989 ldb_lvds_ch1: endpoint { 1990 }; 1991 }; 1992 }; 1993 }; 1994 }; 1995 1996 pcie_phy: pcie-phy@32f00000 { 1997 compatible = "fsl,imx8mp-pcie-phy"; 1998 reg = <0x32f00000 0x10000>; 1999 resets = <&src IMX8MP_RESET_PCIEPHY>, 2000 <&src IMX8MP_RESET_PCIEPHY_PERST>; 2001 reset-names = "pciephy", "perst"; 2002 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 2003 #phy-cells = <0>; 2004 status = "disabled"; 2005 }; 2006 2007 hsio_blk_ctrl: blk-ctrl@32f10000 { 2008 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 2009 reg = <0x32f10000 0x24>; 2010 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2011 <&clk IMX8MP_CLK_PCIE_ROOT>; 2012 clock-names = "usb", "pcie"; 2013 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 2014 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 2015 <&pgc_hsiomix>, <&pgc_pcie_phy>; 2016 power-domain-names = "bus", "usb", "usb-phy1", 2017 "usb-phy2", "pcie", "pcie-phy"; 2018 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 2019 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 2020 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 2021 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 2022 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 2023 #power-domain-cells = <1>; 2024 #clock-cells = <0>; 2025 }; 2026 2027 hdmi_blk_ctrl: blk-ctrl@32fc0000 { 2028 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; 2029 reg = <0x32fc0000 0x1000>; 2030 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2031 <&clk IMX8MP_CLK_HDMI_ROOT>, 2032 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2033 <&clk IMX8MP_CLK_HDMI_24M>, 2034 <&clk IMX8MP_CLK_HDMI_FDCC_TST>; 2035 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; 2036 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, 2037 <&pgc_hdmimix>, <&pgc_hdmimix>, 2038 <&pgc_hdmimix>, <&pgc_hdmimix>, 2039 <&pgc_hdmimix>, <&pgc_hdmi_phy>, 2040 <&pgc_hdmimix>, <&pgc_hdmimix>; 2041 power-domain-names = "bus", "irqsteer", "lcdif", 2042 "pai", "pvi", "trng", 2043 "hdmi-tx", "hdmi-tx-phy", 2044 "hdcp", "hrv"; 2045 #power-domain-cells = <1>; 2046 }; 2047 2048 irqsteer_hdmi: interrupt-controller@32fc2000 { 2049 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; 2050 reg = <0x32fc2000 0x1000>; 2051 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 2052 interrupt-controller; 2053 #interrupt-cells = <1>; 2054 fsl,channel = <1>; 2055 fsl,num-irqs = <64>; 2056 clocks = <&clk IMX8MP_CLK_HDMI_APB>; 2057 clock-names = "ipg"; 2058 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; 2059 }; 2060 2061 hdmi_pvi: display-bridge@32fc4000 { 2062 compatible = "fsl,imx8mp-hdmi-pvi"; 2063 reg = <0x32fc4000 0x1000>; 2064 interrupt-parent = <&irqsteer_hdmi>; 2065 interrupts = <12>; 2066 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; 2067 status = "disabled"; 2068 2069 ports { 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 2073 port@0 { 2074 reg = <0>; 2075 pvi_from_lcdif3: endpoint { 2076 remote-endpoint = <&lcdif3_to_pvi>; 2077 }; 2078 }; 2079 2080 port@1 { 2081 reg = <1>; 2082 pvi_to_hdmi_tx: endpoint { 2083 remote-endpoint = <&hdmi_tx_from_pvi>; 2084 }; 2085 }; 2086 }; 2087 }; 2088 2089 lcdif3: display-controller@32fc6000 { 2090 compatible = "fsl,imx8mp-lcdif"; 2091 reg = <0x32fc6000 0x1000>; 2092 interrupt-parent = <&irqsteer_hdmi>; 2093 interrupts = <8>; 2094 clocks = <&hdmi_tx_phy>, 2095 <&clk IMX8MP_CLK_HDMI_APB>, 2096 <&clk IMX8MP_CLK_HDMI_ROOT>; 2097 clock-names = "pix", "axi", "disp_axi"; 2098 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; 2099 status = "disabled"; 2100 2101 port { 2102 lcdif3_to_pvi: endpoint { 2103 remote-endpoint = <&pvi_from_lcdif3>; 2104 }; 2105 }; 2106 }; 2107 2108 hdmi_tx: hdmi@32fd8000 { 2109 compatible = "fsl,imx8mp-hdmi-tx"; 2110 reg = <0x32fd8000 0x7eff>; 2111 interrupt-parent = <&irqsteer_hdmi>; 2112 interrupts = <0>; 2113 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2114 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2115 <&clk IMX8MP_CLK_32K>, 2116 <&hdmi_tx_phy>; 2117 clock-names = "iahb", "isfr", "cec", "pix"; 2118 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; 2119 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; 2120 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; 2121 reg-io-width = <1>; 2122 status = "disabled"; 2123 2124 ports { 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 2128 port@0 { 2129 reg = <0>; 2130 2131 hdmi_tx_from_pvi: endpoint { 2132 remote-endpoint = <&pvi_to_hdmi_tx>; 2133 }; 2134 }; 2135 2136 port@1 { 2137 reg = <1>; 2138 /* Point endpoint to the HDMI connector */ 2139 }; 2140 }; 2141 }; 2142 2143 hdmi_tx_phy: phy@32fdff00 { 2144 compatible = "fsl,imx8mp-hdmi-phy"; 2145 reg = <0x32fdff00 0x100>; 2146 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2147 <&clk IMX8MP_CLK_HDMI_24M>; 2148 clock-names = "apb", "ref"; 2149 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; 2150 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2151 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; 2152 #clock-cells = <0>; 2153 #phy-cells = <0>; 2154 status = "disabled"; 2155 }; 2156 }; 2157 2158 pcie: pcie@33800000 { 2159 compatible = "fsl,imx8mp-pcie"; 2160 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 2161 reg-names = "dbi", "config"; 2162 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2163 <&clk IMX8MP_CLK_HSIO_AXI>, 2164 <&clk IMX8MP_CLK_PCIE_ROOT>; 2165 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2166 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2167 assigned-clock-rates = <10000000>; 2168 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2169 #address-cells = <3>; 2170 #size-cells = <2>; 2171 device_type = "pci"; 2172 bus-range = <0x00 0xff>; 2173 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 2174 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 2175 num-lanes = <1>; 2176 num-viewport = <4>; 2177 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2178 interrupt-names = "msi"; 2179 #interrupt-cells = <1>; 2180 interrupt-map-mask = <0 0 0 0x7>; 2181 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2182 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2183 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2184 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2185 fsl,max-link-speed = <3>; 2186 linux,pci-domain = <0>; 2187 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2188 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2189 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2190 reset-names = "apps", "turnoff"; 2191 phys = <&pcie_phy>; 2192 phy-names = "pcie-phy"; 2193 status = "disabled"; 2194 }; 2195 2196 pcie_ep: pcie-ep@33800000 { 2197 compatible = "fsl,imx8mp-pcie-ep"; 2198 reg = <0x33800000 0x100000>, 2199 <0x18000000 0x8000000>, 2200 <0x33900000 0x100000>, 2201 <0x33b00000 0x100000>; 2202 reg-names = "dbi", "addr_space", "dbi2", "atu"; 2203 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2204 <&clk IMX8MP_CLK_HSIO_AXI>, 2205 <&clk IMX8MP_CLK_PCIE_ROOT>; 2206 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2207 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2208 assigned-clock-rates = <10000000>; 2209 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2210 num-lanes = <1>; 2211 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2212 interrupt-names = "dma"; 2213 fsl,max-link-speed = <3>; 2214 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2215 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2216 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2217 reset-names = "apps", "turnoff"; 2218 phys = <&pcie_phy>; 2219 phy-names = "pcie-phy"; 2220 num-ib-windows = <4>; 2221 num-ob-windows = <4>; 2222 status = "disabled"; 2223 }; 2224 2225 gpu3d: gpu@38000000 { 2226 compatible = "vivante,gc"; 2227 reg = <0x38000000 0x8000>; 2228 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2229 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 2230 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 2231 <&clk IMX8MP_CLK_GPU_ROOT>, 2232 <&clk IMX8MP_CLK_GPU_AHB>; 2233 clock-names = "core", "shader", "bus", "reg"; 2234 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 2235 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 2236 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 2237 <&clk IMX8MP_SYS_PLL1_800M>; 2238 assigned-clock-rates = <800000000>, <800000000>; 2239 power-domains = <&pgc_gpu3d>; 2240 }; 2241 2242 gpu2d: gpu@38008000 { 2243 compatible = "vivante,gc"; 2244 reg = <0x38008000 0x8000>; 2245 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2246 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 2247 <&clk IMX8MP_CLK_GPU_ROOT>, 2248 <&clk IMX8MP_CLK_GPU_AHB>; 2249 clock-names = "core", "bus", "reg"; 2250 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 2251 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 2252 assigned-clock-rates = <800000000>; 2253 power-domains = <&pgc_gpu2d>; 2254 }; 2255 2256 vpu_g1: video-codec@38300000 { 2257 compatible = "nxp,imx8mm-vpu-g1"; 2258 reg = <0x38300000 0x10000>; 2259 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2260 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 2261 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 2262 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2263 assigned-clock-rates = <600000000>; 2264 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 2265 }; 2266 2267 vpu_g2: video-codec@38310000 { 2268 compatible = "nxp,imx8mq-vpu-g2"; 2269 reg = <0x38310000 0x10000>; 2270 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2271 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 2272 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 2273 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2274 assigned-clock-rates = <500000000>; 2275 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 2276 }; 2277 2278 vpumix_blk_ctrl: blk-ctrl@38330000 { 2279 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2280 reg = <0x38330000 0x100>; 2281 #power-domain-cells = <1>; 2282 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2283 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2284 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2285 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2286 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2287 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2288 clock-names = "g1", "g2", "vc8000e"; 2289 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 2290 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2291 assigned-clock-rates = <600000000>, <600000000>; 2292 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2293 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2294 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2295 interconnect-names = "g1", "g2", "vc8000e"; 2296 }; 2297 2298 npu: npu@38500000 { 2299 compatible = "vivante,gc"; 2300 reg = <0x38500000 0x200000>; 2301 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2303 <&clk IMX8MP_CLK_NPU_ROOT>, 2304 <&clk IMX8MP_CLK_ML_AXI>, 2305 <&clk IMX8MP_CLK_ML_AHB>; 2306 clock-names = "core", "shader", "bus", "reg"; 2307 power-domains = <&pgc_mlmix>; 2308 }; 2309 2310 gic: interrupt-controller@38800000 { 2311 compatible = "arm,gic-v3"; 2312 reg = <0x38800000 0x10000>, 2313 <0x38880000 0xc0000>; 2314 #interrupt-cells = <3>; 2315 interrupt-controller; 2316 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2317 interrupt-parent = <&gic>; 2318 }; 2319 2320 edacmc: memory-controller@3d400000 { 2321 compatible = "snps,ddrc-3.80a"; 2322 reg = <0x3d400000 0x400000>; 2323 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2324 }; 2325 2326 ddr-pmu@3d800000 { 2327 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2328 reg = <0x3d800000 0x400000>; 2329 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2330 }; 2331 2332 usb3_phy0: usb-phy@381f0040 { 2333 compatible = "fsl,imx8mp-usb-phy"; 2334 reg = <0x381f0040 0x40>; 2335 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2336 clock-names = "phy"; 2337 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2338 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2339 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2340 #phy-cells = <0>; 2341 status = "disabled"; 2342 }; 2343 2344 usb3_0: usb@32f10100 { 2345 compatible = "fsl,imx8mp-dwc3"; 2346 reg = <0x32f10100 0x8>, 2347 <0x381f0000 0x20>; 2348 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2349 <&clk IMX8MP_CLK_USB_SUSP>; 2350 clock-names = "hsio", "suspend"; 2351 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2352 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2353 #address-cells = <1>; 2354 #size-cells = <1>; 2355 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2356 ranges; 2357 status = "disabled"; 2358 2359 usb_dwc3_0: usb@38100000 { 2360 compatible = "snps,dwc3"; 2361 reg = <0x38100000 0x10000>; 2362 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2363 <&clk IMX8MP_CLK_USB_CORE_REF>, 2364 <&clk IMX8MP_CLK_USB_SUSP>; 2365 clock-names = "bus_early", "ref", "suspend"; 2366 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2367 phys = <&usb3_phy0>, <&usb3_phy0>; 2368 phy-names = "usb2-phy", "usb3-phy"; 2369 snps,gfladj-refclk-lpm-sel-quirk; 2370 snps,parkmode-disable-ss-quirk; 2371 }; 2372 2373 }; 2374 2375 usb3_phy1: usb-phy@382f0040 { 2376 compatible = "fsl,imx8mp-usb-phy"; 2377 reg = <0x382f0040 0x40>; 2378 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2379 clock-names = "phy"; 2380 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2381 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2382 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2383 #phy-cells = <0>; 2384 status = "disabled"; 2385 }; 2386 2387 usb3_1: usb@32f10108 { 2388 compatible = "fsl,imx8mp-dwc3"; 2389 reg = <0x32f10108 0x8>, 2390 <0x382f0000 0x20>; 2391 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2392 <&clk IMX8MP_CLK_USB_SUSP>; 2393 clock-names = "hsio", "suspend"; 2394 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2395 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2396 #address-cells = <1>; 2397 #size-cells = <1>; 2398 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2399 ranges; 2400 status = "disabled"; 2401 2402 usb_dwc3_1: usb@38200000 { 2403 compatible = "snps,dwc3"; 2404 reg = <0x38200000 0x10000>; 2405 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2406 <&clk IMX8MP_CLK_USB_CORE_REF>, 2407 <&clk IMX8MP_CLK_USB_SUSP>; 2408 clock-names = "bus_early", "ref", "suspend"; 2409 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2410 phys = <&usb3_phy1>, <&usb3_phy1>; 2411 phy-names = "usb2-phy", "usb3-phy"; 2412 snps,gfladj-refclk-lpm-sel-quirk; 2413 snps,parkmode-disable-ss-quirk; 2414 }; 2415 }; 2416 2417 dsp: dsp@3b6e8000 { 2418 compatible = "fsl,imx8mp-dsp"; 2419 reg = <0x3b6e8000 0x88000>; 2420 mbox-names = "txdb0", "txdb1", 2421 "rxdb0", "rxdb1"; 2422 mboxes = <&mu2 2 0>, <&mu2 2 1>, 2423 <&mu2 3 0>, <&mu2 3 1>; 2424 memory-region = <&dsp_reserved>; 2425 status = "disabled"; 2426 }; 2427 }; 2428}; 2429