1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2021-2025 TQ-Systems GmbH <[email protected]>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
12	compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
13
14	memory@40000000 {
15		device_type = "memory";
16		reg = <0x0 0x40000000 0 0x80000000>;
17	};
18
19	/* identical to buck4_reg, but should never change */
20	reg_vcc3v3: regulator-vcc3v3 {
21		compatible = "regulator-fixed";
22		regulator-name = "VCC3V3";
23		regulator-min-microvolt = <3300000>;
24		regulator-max-microvolt = <3300000>;
25		regulator-always-on;
26	};
27};
28
29&A53_0 {
30	cpu-supply = <&buck2_reg>;
31};
32
33&flexspi {
34	pinctrl-names = "default";
35	pinctrl-0 = <&pinctrl_flexspi0>;
36	status = "okay";
37
38	flash0: flash@0 {
39		reg = <0>;
40		compatible = "jedec,spi-nor";
41		spi-max-frequency = <80000000>;
42		spi-tx-bus-width = <1>;
43		spi-rx-bus-width = <4>;
44
45		partitions {
46			compatible = "fixed-partitions";
47			#address-cells = <1>;
48			#size-cells = <1>;
49		};
50	};
51};
52
53&i2c1 {
54	clock-frequency = <384000>;
55	pinctrl-names = "default", "gpio";
56	pinctrl-0 = <&pinctrl_i2c1>;
57	pinctrl-1 = <&pinctrl_i2c1_gpio>;
58	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
59	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
60	status = "okay";
61
62	se97: temperature-sensor@1b {
63		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
64		reg = <0x1b>;
65	};
66
67	pmic: pmic@25 {
68		reg = <0x25>;
69		compatible = "nxp,pca9450c";
70
71		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
72		pinctrl-0 = <&pinctrl_pmic>;
73		pinctrl-names = "default";
74		interrupt-parent = <&gpio1>;
75		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
76
77		regulators {
78			/* V_0V85_SOC: 0.85 .. 0.95 */
79			buck1_reg: BUCK1 {
80				regulator-name = "BUCK1";
81				regulator-min-microvolt = <850000>;
82				regulator-max-microvolt = <950000>;
83				regulator-boot-on;
84				regulator-always-on;
85				regulator-ramp-delay = <3125>;
86			};
87
88			/* VDD_ARM */
89			buck2_reg: BUCK2 {
90				regulator-name = "BUCK2";
91				regulator-min-microvolt = <850000>;
92				regulator-max-microvolt = <1000000>;
93				regulator-boot-on;
94				regulator-always-on;
95				nxp,dvs-run-voltage = <950000>;
96				nxp,dvs-standby-voltage = <850000>;
97				regulator-ramp-delay = <3125>;
98			};
99
100			/* VCC3V3 -> VMMC, ... must not be changed */
101			buck4_reg: BUCK4 {
102				regulator-name = "BUCK4";
103				regulator-min-microvolt = <3300000>;
104				regulator-max-microvolt = <3300000>;
105				regulator-boot-on;
106				regulator-always-on;
107			};
108
109			/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
110			buck5_reg: BUCK5 {
111				regulator-name = "BUCK5";
112				regulator-min-microvolt = <1800000>;
113				regulator-max-microvolt = <1800000>;
114				regulator-boot-on;
115				regulator-always-on;
116			};
117
118			/* V_1V1 -> RAM, ... must not be changed */
119			buck6_reg: BUCK6 {
120				regulator-name = "BUCK6";
121				regulator-min-microvolt = <1100000>;
122				regulator-max-microvolt = <1100000>;
123				regulator-boot-on;
124				regulator-always-on;
125			};
126
127			/* V_1V8_SNVS */
128			ldo1_reg: LDO1 {
129				regulator-name = "LDO1";
130				regulator-min-microvolt = <1800000>;
131				regulator-max-microvolt = <1800000>;
132				regulator-boot-on;
133				regulator-always-on;
134			};
135
136			/* V_1V8_ANA */
137			ldo3_reg: LDO3 {
138				regulator-name = "LDO3";
139				regulator-min-microvolt = <1800000>;
140				regulator-max-microvolt = <1800000>;
141				regulator-boot-on;
142				regulator-always-on;
143			};
144
145			/* unused */
146			ldo4_reg: LDO4 {
147				regulator-name = "LDO4";
148				regulator-min-microvolt = <800000>;
149				regulator-max-microvolt = <3300000>;
150			};
151
152			/* VCC SD IO - switched using SD2 VSELECT */
153			ldo5_reg: LDO5 {
154				regulator-name = "LDO5";
155				regulator-min-microvolt = <1800000>;
156				regulator-max-microvolt = <3300000>;
157			};
158		};
159	};
160
161	pcf85063: rtc@51 {
162		compatible = "nxp,pcf85063a";
163		reg = <0x51>;
164	};
165
166	at24c02: eeprom@53 {
167		compatible = "nxp,se97b", "atmel,24c02";
168		read-only;
169		reg = <0x53>;
170		pagesize = <16>;
171		vcc-supply = <&reg_vcc3v3>;
172	};
173
174	m24c64: eeprom@57 {
175		compatible = "atmel,24c64";
176		reg = <0x57>;
177		pagesize = <32>;
178		vcc-supply = <&reg_vcc3v3>;
179	};
180};
181
182&usdhc3 {
183	pinctrl-names = "default", "state_100mhz", "state_200mhz";
184	pinctrl-0 = <&pinctrl_usdhc3>;
185	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
186	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
187	bus-width = <8>;
188	non-removable;
189	no-sd;
190	no-sdio;
191	vmmc-supply = <&reg_vcc3v3>;
192	vqmmc-supply = <&buck5_reg>;
193	status = "okay";
194};
195
196&wdog1 {
197	pinctrl-names = "default";
198	pinctrl-0 = <&pinctrl_wdog>;
199	fsl,ext-reset-output;
200	status = "okay";
201};
202
203&iomuxc {
204	pinctrl_flexspi0: flexspi0grp {
205		fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK	0x142>,
206			   <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
207			   <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
208			   <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
209			   <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
210			   <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>;
211	};
212
213	pinctrl_i2c1: i2c1grp {
214		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e2>,
215			   <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e2>;
216	};
217
218	pinctrl_i2c1_gpio: i2c1-gpiogrp {
219		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001e2>,
220			   <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001e2>;
221	};
222
223	pinctrl_pmic: pmicirqgrp {
224		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x1c0>;
225	};
226
227	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
228		fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x10>;
229	};
230
231	pinctrl_usdhc3: usdhc3grp {
232		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
233			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
234			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
235			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
236			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
237			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
238			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
239			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
240			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
241			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
242			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
243			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
244	};
245
246	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
247		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
248			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
249			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
250			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
251			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
252			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
253			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
254			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
255			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
256			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
257			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
258			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
259	};
260
261	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
262		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
263			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
264			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
265			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
266			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
267			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
268			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
269			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
270			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
271			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
272			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
273			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
274	};
275
276	pinctrl_wdog: wdoggrp {
277		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x1c4>;
278	};
279};
280