1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 3#include "imx8mp.dtsi" 4 5#include <dt-bindings/leds/common.h> 6 7/ { 8 aliases { 9 /* some of this aliases like backlight0, ethernetX and switch0 10 * are needed for the bootloader. 11 */ 12 backlight0 = &backlight; 13 ethernet0 = &eqos; 14 ethernet1 = &lan1; 15 ethernet2 = &lan2; 16 rtc0 = &i2c_rtc; 17 rtc1 = &snvs_rtc; 18 switch0 = &switch; 19 }; 20 21 /* 22 * Backlight is present only on some of boards, so it is disabled by 23 * default. 24 */ 25 backlight: backlight { 26 compatible = "pwm-backlight"; 27 pinctrl-0 = <&pinctrl_backlight>; 28 pwms = <&pwm1 0 20000 0>; 29 power-supply = <®_24v>; 30 enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 31 brightness-levels = <0 255>; 32 num-interpolated-steps = <17>; 33 default-brightness-level = <8>; 34 status = "disabled"; 35 }; 36 37 leds { 38 compatible = "gpio-leds"; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_gpio_led>; 41 42 led-0 { 43 label = "D1"; 44 color = <LED_COLOR_ID_GREEN>; 45 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 46 function = LED_FUNCTION_STATUS; 47 default-state = "on"; 48 linux,default-trigger = "heartbeat"; 49 }; 50 51 led-1 { 52 label = "D2"; 53 color = <LED_COLOR_ID_GREEN>; 54 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 55 default-state = "off"; 56 }; 57 58 led-2 { 59 label = "D3"; 60 color = <LED_COLOR_ID_GREEN>; 61 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 62 default-state = "on"; 63 }; 64 }; 65 66 reg_1v2: regulator-1v2 { 67 compatible = "regulator-fixed"; 68 vin-supply = <®_5v_p>; 69 regulator-name = "1V2"; 70 regulator-min-microvolt = <1200000>; 71 regulator-max-microvolt = <1200000>; 72 }; 73 74 reg_2v5: regulator-2v5 { 75 compatible = "regulator-fixed"; 76 vin-supply = <®_5v_s>; 77 regulator-name = "2V5"; 78 regulator-min-microvolt = <2500000>; 79 regulator-max-microvolt = <2500000>; 80 }; 81 82 reg_3v3: regulator-3v3 { 83 compatible = "regulator-fixed"; 84 vin-supply = <®_5v_s>; 85 regulator-name = "3V3"; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 }; 89 90 /* 91 * This regulator will provide power as long as possible even if 92 * undervoltage is detected. 93 */ 94 reg_5v_p: regulator-5v-p { 95 compatible = "regulator-fixed"; 96 regulator-name = "5V_P"; 97 vin-supply = <®_24v>; 98 regulator-min-microvolt = <5000000>; 99 regulator-max-microvolt = <5000000>; 100 }; 101 102 /* 103 * This regulator will be automatically shutdown if undervoltage is 104 * detected. 105 */ 106 reg_5v_s: regulator-5v-s { 107 compatible = "regulator-fixed"; 108 regulator-name = "5V_S"; 109 vin-supply = <®_24v>; 110 regulator-min-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>; 112 }; 113 114 reg_24v: regulator-24v { 115 compatible = "regulator-fixed"; 116 regulator-name = "24V"; 117 regulator-min-microvolt = <24000000>; 118 regulator-max-microvolt = <24000000>; 119 }; 120 121 reg_can2rs: regulator-can2rs { 122 compatible = "regulator-fixed"; 123 regulator-name = "CAN2RS"; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_can2rs>; 126 regulator-min-microvolt = <3300000>; 127 regulator-max-microvolt = <3300000>; 128 gpio = <&gpio4 22 GPIO_ACTIVE_LOW>; 129 }; 130 131 reg_canrs: regulator-canrs { 132 compatible = "regulator-fixed"; 133 regulator-name = "CANRS"; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_canrs>; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; 139 }; 140 141 reg_tft_vcom: regulator-tft-vcom { 142 compatible = "pwm-regulator"; 143 pwms = <&pwm4 0 20000 0>; 144 regulator-name = "VCOM"; 145 vin-supply = <®_5v_s>; 146 regulator-min-microvolt = <3600000>; 147 regulator-max-microvolt = <3600000>; 148 regulator-always-on; 149 voltage-table = <3600000 26>; 150 status = "disabled"; 151 }; 152 153 reg_vsd_3v3: regulator-vsd-3v3 { 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_reg_vsd_3v3>; 156 vin-supply = <®_vdd_3v3>; 157 compatible = "regulator-fixed"; 158 regulator-name = "VSD_3V3"; 159 regulator-min-microvolt = <3300000>; 160 regulator-max-microvolt = <3300000>; 161 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 162 enable-active-high; 163 }; 164}; 165 166/* 167 * Board is passively cooled and heatsink is specced for continuous operation 168 * at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be done 169 * intentionally, not as part of suspend/resume cycles. 170 */ 171&{/opp-table/opp-1600000000} { 172 /delete-property/ opp-suspend; 173}; 174 175&{/opp-table/opp-1800000000} { 176 /delete-property/ opp-suspend; 177}; 178 179&A53_0 { 180 cpu-supply = <®_vdd_arm>; 181}; 182 183&A53_1 { 184 cpu-supply = <®_vdd_arm>; 185}; 186 187&A53_2 { 188 cpu-supply = <®_vdd_arm>; 189}; 190 191&A53_3 { 192 cpu-supply = <®_vdd_arm>; 193}; 194 195&ecspi2 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_ecspi2>; 198 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 199 status = "okay"; 200 201 adc: adc@0 { 202 compatible = "microchip,mcp3002"; 203 reg = <0>; 204 vref-supply = <®_vdd_3v3>; 205 spi-max-frequency = <1000000>; 206 #io-channel-cells = <1>; 207 }; 208}; 209 210&eqos { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_eqos>; 213 phy-mode = "rgmii-txid"; 214 status = "okay"; 215 216 fixed-link { 217 speed = <1000>; 218 full-duplex; 219 }; 220}; 221 222&flexcan1 { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_flexcan1>; 225 xceiver-supply = <®_canrs>; 226 status = "okay"; 227}; 228 229&flexcan2 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_flexcan2>; 232 xceiver-supply = <®_can2rs>; 233 status = "okay"; 234}; 235 236&i2c1 { 237 clock-frequency = <100000>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_i2c1>; 240 status = "okay"; 241 242 pmic@25 { 243 compatible = "nxp,pca9450c"; 244 reg = <0x25>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_pmic>; 247 interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>; 248 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 249 250 regulators { 251 reg_vdd_soc: BUCK1 { 252 regulator-name = "VDD_SOC"; 253 regulator-min-microvolt = <600000>; 254 regulator-max-microvolt = <2187500>; 255 vin-supply = <®_5v_p>; 256 regulator-boot-on; 257 regulator-always-on; 258 regulator-ramp-delay = <3125>; 259 }; 260 261 reg_vdd_arm: BUCK2 { 262 regulator-name = "VDD_ARM"; 263 regulator-min-microvolt = <850000>; 264 regulator-max-microvolt = <1000000>; 265 vin-supply = <®_5v_p>; 266 regulator-boot-on; 267 regulator-always-on; 268 regulator-ramp-delay = <3125>; 269 nxp,dvs-run-voltage = <850000>; 270 nxp,dvs-standby-voltage = <850000>; 271 }; 272 273 reg_vdd_3v3: BUCK4 { 274 regulator-name = "VDD_3V3"; 275 regulator-min-microvolt = <3300000>; 276 regulator-max-microvolt = <3300000>; 277 vin-supply = <®_5v_p>; 278 regulator-boot-on; 279 regulator-always-on; 280 }; 281 282 reg_vdd_1v8: BUCK5 { 283 regulator-name = "VDD_1V8"; 284 regulator-min-microvolt = <1800000>; 285 regulator-max-microvolt = <1800000>; 286 vin-supply = <®_5v_p>; 287 regulator-boot-on; 288 regulator-always-on; 289 }; 290 291 reg_nvcc_dram_1v1: BUCK6 { 292 regulator-name = "NVCC_DRAM_1V1"; 293 regulator-min-microvolt = <1100000>; 294 regulator-max-microvolt = <1100000>; 295 vin-supply = <®_5v_p>; 296 regulator-boot-on; 297 regulator-always-on; 298 }; 299 300 reg_nvcc_snvs_1v8: LDO1 { 301 regulator-name = "NVCC_SNVS_1V8"; 302 regulator-min-microvolt = <1800000>; 303 regulator-max-microvolt = <1800000>; 304 vin-supply = <®_5v_p>; 305 regulator-boot-on; 306 regulator-always-on; 307 }; 308 309 reg_vdda_1v8: LDO3 { 310 regulator-name = "VDDA_1V8"; 311 regulator-min-microvolt = <1800000>; 312 regulator-max-microvolt = <1800000>; 313 vin-supply = <®_5v_p>; 314 regulator-boot-on; 315 regulator-always-on; 316 }; 317 318 reg_nvcc_sd2: LDO5 { 319 regulator-name = "NVCC_SD2"; 320 regulator-min-microvolt = <1800000>; 321 regulator-max-microvolt = <3300000>; 322 vin-supply = <®_5v_p>; 323 regulator-boot-on; 324 regulator-always-on; 325 }; 326 }; 327 }; 328}; 329 330&i2c3 { 331 clock-frequency = <100000>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_i2c3>; 334 status = "okay"; 335 336 i2c_rtc: rtc@51 { 337 compatible = "nxp,pcf85063tp"; 338 reg = <0x51>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_rtc>; 341 interrupts-extended = <&gpio4 31 IRQ_TYPE_EDGE_FALLING>; 342 quartz-load-femtofarads = <12500>; 343 }; 344}; 345 346&i2c4 { 347 clock-frequency = <380000>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_i2c4>; 350 status = "okay"; 351 352 switch: switch@5f { 353 compatible = "microchip,ksz9893"; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_switch>; 356 reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; 357 reg = <0x5f>; 358 359 ethernet-ports { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 lan1: port@0 { 364 reg = <0>; 365 phy-mode = "internal"; 366 label = "lan1"; 367 }; 368 369 lan2: port@1 { 370 reg = <1>; 371 phy-mode = "internal"; 372 label = "lan2"; 373 }; 374 375 port@2 { 376 reg = <2>; 377 label = "cpu"; 378 ethernet = <&eqos>; 379 phy-mode = "rgmii"; 380 /* 2ns RX delay is implemented on PCB */ 381 tx-internal-delay-ps = <2000>; 382 rx-internal-delay-ps = <0>; 383 384 fixed-link { 385 speed = <1000>; 386 full-duplex; 387 }; 388 }; 389 }; 390 }; 391}; 392 393&pwm1 { 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pinctrl_pwm1>; 396}; 397 398&pwm4 { 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_pwm4>; 401}; 402 403&uart1 { 404 pinctrl-names = "default"; 405 pinctrl-0 = <&pinctrl_uart1>; 406 status = "okay"; 407}; 408 409&uart2 { 410 /* console */ 411 pinctrl-names = "default"; 412 pinctrl-0 = <&pinctrl_uart2>; 413 status = "okay"; 414}; 415 416&usb3_0 { 417 status = "okay"; 418}; 419 420&usb3_1 { 421 status = "okay"; 422}; 423 424&usb3_phy0 { 425 vbus-supply = <®_3v3>; 426 status = "okay"; 427}; 428 429&usb3_phy1 { 430 vbus-supply = <®_3v3>; 431 status = "okay"; 432}; 433 434&usb_dwc3_0 { 435 dr_mode = "host"; 436}; 437 438&usb_dwc3_1 { 439 dr_mode = "host"; 440}; 441 442/* SD Card */ 443&usdhc2 { 444 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 445 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 446 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 447 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 448 vmmc-supply = <®_vsd_3v3>; 449 vqmmc-supply = <®_nvcc_sd2>; 450 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 451 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 452 bus-width = <4>; 453 status = "okay"; 454}; 455 456/* eMMC */ 457&usdhc3 { 458 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 459 assigned-clock-rates = <400000000>; 460 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 461 pinctrl-0 = <&pinctrl_usdhc3>; 462 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 463 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 464 vmmc-supply = <®_vdd_3v3>; 465 vqmmc-supply = <®_vdd_1v8>; 466 bus-width = <8>; 467 no-sd; 468 no-sdio; 469 non-removable; 470 status = "okay"; 471}; 472 473&wdog1 { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pinctrl_wdog>; 476 fsl,ext-reset-output; 477 status = "okay"; 478}; 479 480&iomuxc { 481 pinctrl_backlight: backlightgrp { 482 fsl,pins = < 483 MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0100 484 >; 485 }; 486 487 pinctrl_can2rs: can2rsgrp { 488 fsl,pins = < 489 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x154 490 >; 491 }; 492 493 pinctrl_canrs: canrsgrp { 494 fsl,pins = < 495 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x154 496 >; 497 }; 498 499 pinctrl_ecspi2: ecspi2grp { 500 fsl,pins = < 501 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 502 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 503 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 504 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 505 >; 506 }; 507 508 pinctrl_eqos: eqosgrp { 509 fsl,pins = < 510 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 511 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 512 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 513 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 514 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 515 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 516 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 517 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 518 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 519 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 520 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 521 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 522 >; 523 }; 524 525 pinctrl_flexcan1: flexcan1grp { 526 fsl,pins = < 527 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 528 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 529 >; 530 }; 531 532 pinctrl_flexcan2: flexcan2grp { 533 fsl,pins = < 534 MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 535 MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 536 >; 537 }; 538 539 pinctrl_gpio_led: gpioledgrp { 540 fsl,pins = < 541 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 542 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 543 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 544 >; 545 }; 546 547 pinctrl_i2c1: i2c1grp { 548 fsl,pins = < 549 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 550 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 551 >; 552 }; 553 554 pinctrl_i2c3: i2c3grp { 555 fsl,pins = < 556 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 557 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 558 >; 559 }; 560 561 pinctrl_i2c4: i2c4grp { 562 fsl,pins = < 563 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 564 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 565 >; 566 }; 567 568 pinctrl_pmic: pmicirqgrp { 569 fsl,pins = < 570 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 571 MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41 572 >; 573 }; 574 575 pinctrl_pwm1: pwm1grp { 576 fsl,pins = < 577 MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 578 >; 579 }; 580 581 pinctrl_pwm4: pwm4grp { 582 fsl,pins = < 583 MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116 584 >; 585 }; 586 587 pinctrl_reg_vsd_3v3: regvsd3v3grp { 588 fsl,pins = < 589 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 590 >; 591 }; 592 593 pinctrl_rtc: rtcgrp { 594 fsl,pins = < 595 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x41 596 >; 597 }; 598 599 pinctrl_switch: switchgrp { 600 fsl,pins = < 601 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x41 602 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x41 603 >; 604 }; 605 606 pinctrl_touchscreen: touchscreengrp { 607 fsl,pins = < 608 /* external 10 k pull up */ 609 /* CTP_INT */ 610 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41 611 /* CTP_RST */ 612 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41 613 >; 614 }; 615 616 pinctrl_uart1: uart1grp { 617 fsl,pins = < 618 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 619 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 620 MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140 621 >; 622 }; 623 624 pinctrl_uart2: uart2grp { 625 fsl,pins = < 626 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f 627 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f 628 >; 629 }; 630 631 pinctrl_usdhc2: usdhc2grp { 632 fsl,pins = < 633 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 634 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 635 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 636 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 637 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 638 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 639 >; 640 }; 641 642 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 643 fsl,pins = < 644 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 645 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 646 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 647 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 648 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 649 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 650 >; 651 }; 652 653 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 654 fsl,pins = < 655 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 656 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 657 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 658 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 659 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 660 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 661 >; 662 }; 663 664 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 665 fsl,pins = < 666 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 667 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4 668 >; 669 }; 670 671 pinctrl_usdhc3: usdhc3grp { 672 fsl,pins = < 673 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 674 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 675 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 676 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 677 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 678 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 679 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 680 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 681 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 682 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 683 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 684 >; 685 }; 686 687 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 688 fsl,pins = < 689 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 690 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 691 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 692 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 693 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 694 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 695 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 696 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 697 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 698 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 699 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 700 >; 701 }; 702 703 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 704 fsl,pins = < 705 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 706 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 707 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 708 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 709 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 710 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 711 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 712 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 713 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 714 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 715 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 716 >; 717 }; 718 719 pinctrl_wdog: wdoggrp { 720 fsl,pins = < 721 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 722 >; 723 }; 724}; 725