1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2024 Heiko Schocher <[email protected]>
4 */
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/pwm/pwm.h>
9
10/dts-v1/;
11/plugin/;
12
13&{/} {
14	model = "Aristainetos3 helios carrier with LVDS";
15	compatible = "abb,imx8mp-aristanetos3-helios",
16		     "abb,imx8mp-aristanetos3-som",
17		     "fsl,imx8mp";
18
19	panel_lvds: panel-lvds {
20		compatible = "lg,lb070wv8";
21		power-supply = <&reg_vcc_disp>;
22		backlight = <&lvds_backlight>;
23
24		port {
25			in_lvds0: endpoint {
26				remote-endpoint = <&ldb_lvds_ch0>;
27			};
28		};
29	};
30
31	reg_vcc_disp: regulator-disp {
32		pinctrl-names = "default";
33		pinctrl-0 = <&pinctrl_lcd0_vcc_en>;
34		compatible = "regulator-fixed";
35		regulator-name = "disp_power_en_2v8";
36		regulator-min-microvolt = <2800000>;
37		regulator-max-microvolt = <2800000>;
38		gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40		regulator-boot-on;
41		regulator-always-on;
42	};
43};
44
45&gpio3 {
46	pinctrl-names = "default";
47	pinctrl-0 = <&pinctrl_gpio3_hog>;
48
49	lvdssel-hog {
50		gpio-hog;
51		gpios = <23 GPIO_ACTIVE_HIGH>;
52		output-low;
53		line-name = "LVDSSEL";
54	};
55};
56
57&hdmi_blk_ctrl {
58	status = "disabled";
59};
60
61&hdmi_pvi {
62	status = "disabled";
63};
64
65&hdmi_tx {
66	status = "disabled";
67};
68
69&hdmi_tx_phy {
70	status = "disabled";
71};
72
73&irqsteer_hdmi {
74	status = "disabled";
75};
76
77&ldb_lvds_ch0 {
78	remote-endpoint = <&in_lvds0>;
79};
80
81&lcdif1 {
82	status = "disabled";
83};
84
85&lcdif2 {
86	status = "okay";
87};
88
89&lcdif3 {
90	status = "disabled";
91};
92
93&lvds_backlight {
94	status = "okay";
95};
96
97&lvds_bridge {
98	/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
99	assigned-clock-rates = <232820000>;
100	status = "okay";
101};
102
103&media_blk_ctrl {
104	/*
105	 * currently it is not possible to let display clocks configure
106	 * automatically, so we need to set them manually
107	 */
108	assigned-clock-rates = <500000000>, <200000000>, <0>,
109		/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
110		<33260000>, <0>,
111		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
112		<465640000>;
113};
114