1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's ExynosAutov920 SoC device tree source
4 *
5 * Copyright (c) 2023 Samsung Electronics Co., Ltd.
6 *
7 */
8
9#include <dt-bindings/clock/samsung,exynosautov920.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/soc/samsung,exynos-usi.h>
12
13/ {
14	compatible = "samsung,exynosautov920";
15	#address-cells = <2>;
16	#size-cells = <1>;
17
18	interrupt-parent = <&gic>;
19
20	aliases {
21		pinctrl0 = &pinctrl_alive;
22		pinctrl1 = &pinctrl_aud;
23		pinctrl2 = &pinctrl_hsi0;
24		pinctrl3 = &pinctrl_hsi1;
25		pinctrl4 = &pinctrl_hsi2;
26		pinctrl5 = &pinctrl_hsi2ufs;
27		pinctrl6 = &pinctrl_peric0;
28		pinctrl7 = &pinctrl_peric1;
29	};
30
31	arm-pmu {
32		compatible = "arm,cortex-a78-pmu";
33		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
34	};
35
36	xtcxo: clock {
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		clock-output-names = "oscclk";
40	};
41
42	cpus: cpus {
43		#address-cells = <2>;
44		#size-cells = <0>;
45
46		cpu-map {
47			cluster0 {
48				core0 {
49					cpu = <&cpu0>;
50				};
51				core1 {
52					cpu = <&cpu1>;
53				};
54				core2 {
55					cpu = <&cpu2>;
56				};
57				core3 {
58					cpu = <&cpu3>;
59				};
60			};
61
62			cluster1 {
63				core0 {
64					cpu = <&cpu4>;
65				};
66				core1 {
67					cpu = <&cpu5>;
68				};
69				core2 {
70					cpu = <&cpu6>;
71				};
72				core3 {
73					cpu = <&cpu7>;
74				};
75			};
76
77			cluster2 {
78				core0 {
79					cpu = <&cpu8>;
80				};
81				core1 {
82					cpu = <&cpu9>;
83				};
84			};
85		};
86
87		cpu0: cpu@0 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a78ae";
90			reg = <0x0 0x0>;
91			enable-method = "psci";
92		};
93
94		cpu1: cpu@100 {
95			device_type = "cpu";
96			compatible = "arm,cortex-a78ae";
97			reg = <0x0 0x100>;
98			enable-method = "psci";
99		};
100
101		cpu2: cpu@200 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a78ae";
104			reg = <0x0 0x200>;
105			enable-method = "psci";
106		};
107
108		cpu3: cpu@300 {
109			device_type = "cpu";
110			compatible = "arm,cortex-a78ae";
111			reg = <0x0 0x300>;
112			enable-method = "psci";
113		};
114
115		cpu4: cpu@10000 {
116			device_type = "cpu";
117			compatible = "arm,cortex-a78ae";
118			reg = <0x0 0x10000>;
119			enable-method = "psci";
120		};
121
122		cpu5: cpu@10100 {
123			device_type = "cpu";
124			compatible = "arm,cortex-a78ae";
125			reg = <0x0 0x10100>;
126			enable-method = "psci";
127		};
128
129		cpu6: cpu@10200 {
130			device_type = "cpu";
131			compatible = "arm,cortex-a78ae";
132			reg = <0x0 0x10200>;
133			enable-method = "psci";
134		};
135
136		cpu7: cpu@10300 {
137			device_type = "cpu";
138			compatible = "arm,cortex-a78ae";
139			reg = <0x0 0x10300>;
140			enable-method = "psci";
141		};
142
143		cpu8: cpu@20000 {
144			device_type = "cpu";
145			compatible = "arm,cortex-a78ae";
146			reg = <0x0 0x20000>;
147			enable-method = "psci";
148		};
149
150		cpu9: cpu@20100 {
151			device_type = "cpu";
152			compatible = "arm,cortex-a78ae";
153			reg = <0x0 0x20100>;
154			enable-method = "psci";
155		};
156	};
157
158	psci {
159		compatible = "arm,psci-1.0";
160		method = "smc";
161	};
162
163	soc: soc@0 {
164		compatible = "simple-bus";
165		#address-cells = <1>;
166		#size-cells = <1>;
167		ranges = <0x0 0x0 0x0 0x20000000>;
168
169		chipid@10000000 {
170			compatible = "samsung,exynosautov920-chipid",
171				     "samsung,exynos850-chipid";
172			reg = <0x10000000 0x24>;
173		};
174
175		cmu_misc: clock-controller@10020000 {
176			compatible = "samsung,exynosautov920-cmu-misc";
177			reg = <0x10020000 0x8000>;
178			#clock-cells = <1>;
179
180			clocks = <&xtcxo>,
181				 <&cmu_top DOUT_CLKCMU_MISC_NOC>;
182			clock-names = "oscclk",
183				      "noc";
184		};
185
186		watchdog_cl0: watchdog@10060000 {
187			compatible = "samsung,exynosautov920-wdt";
188			reg = <0x10060000 0x100>;
189			interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>;
190			clocks = <&xtcxo>, <&xtcxo>;
191			clock-names = "watchdog", "watchdog_src";
192			samsung,syscon-phandle = <&pmu_system_controller>;
193			samsung,cluster-index = <0>;
194		};
195
196		watchdog_cl1: watchdog@10070000 {
197			compatible = "samsung,exynosautov920-wdt";
198			reg = <0x10070000 0x100>;
199			interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>;
200			clocks = <&xtcxo>, <&xtcxo>;
201			clock-names = "watchdog", "watchdog_src";
202			samsung,syscon-phandle = <&pmu_system_controller>;
203			samsung,cluster-index = <1>;
204		};
205
206		gic: interrupt-controller@10400000 {
207			compatible = "arm,gic-v3";
208			#interrupt-cells = <3>;
209			#address-cells = <0>;
210			interrupt-controller;
211			reg = <0x10400000 0x10000>,
212			      <0x10460000 0x140000>;
213			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
214		};
215
216		spdma0: dma-controller@10180000 {
217			compatible = "arm,pl330", "arm,primecell";
218			reg = <0x10180000 0x1000>;
219			interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>;
220			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
221			clock-names = "apb_pclk";
222			#dma-cells = <1>;
223		};
224
225		spdma1: dma-controller@10190000 {
226			compatible = "arm,pl330", "arm,primecell";
227			reg = <0x10190000 0x1000>;
228			interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>;
229			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
230			clock-names = "apb_pclk";
231			#dma-cells = <1>;
232		};
233
234		pdma0: dma-controller@101a0000 {
235			compatible = "arm,pl330", "arm,primecell";
236			reg = <0x101a0000 0x1000>;
237			interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>;
238			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
239			clock-names = "apb_pclk";
240			#dma-cells = <1>;
241		};
242
243		pdma1: dma-controller@101b0000 {
244			compatible = "arm,pl330", "arm,primecell";
245			reg = <0x101b0000 0x1000>;
246			interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>;
247			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
248			clock-names = "apb_pclk";
249			#dma-cells = <1>;
250		};
251
252		pdma2: dma-controller@101c0000 {
253			compatible = "arm,pl330", "arm,primecell";
254			reg = <0x101c0000 0x1000>;
255			interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>;
256			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
257			clock-names = "apb_pclk";
258			#dma-cells = <1>;
259		};
260
261		pdma3: dma-controller@101d0000 {
262			compatible = "arm,pl330", "arm,primecell";
263			reg = <0x101d0000 0x1000>;
264			interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>;
265			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
266			clock-names = "apb_pclk";
267			#dma-cells = <1>;
268		};
269
270		pdma4: dma-controller@101e0000 {
271			compatible = "arm,pl330", "arm,primecell";
272			reg = <0x101e0000 0x1000>;
273			interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>;
274			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
275			clock-names = "apb_pclk";
276			#dma-cells = <1>;
277		};
278
279		cmu_peric0: clock-controller@10800000 {
280			compatible = "samsung,exynosautov920-cmu-peric0";
281			reg = <0x10800000 0x8000>;
282			#clock-cells = <1>;
283
284			clocks = <&xtcxo>,
285				 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
286				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
287			clock-names = "oscclk",
288				      "noc",
289				      "ip";
290		};
291
292		syscon_peric0: syscon@10820000 {
293			compatible = "samsung,exynosautov920-peric0-sysreg",
294				     "syscon";
295			reg = <0x10820000 0x2000>;
296		};
297
298		pinctrl_peric0: pinctrl@10830000 {
299			compatible = "samsung,exynosautov920-pinctrl";
300			reg = <0x10830000 0x10000>;
301			interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
302		};
303
304		usi_0: usi@108800c0 {
305			compatible = "samsung,exynosautov920-usi",
306				     "samsung,exynos850-usi";
307			reg = <0x108800c0 0x20>;
308			samsung,sysreg = <&syscon_peric0 0x1000>;
309			samsung,mode = <USI_V2_UART>;
310			#address-cells = <1>;
311			#size-cells = <1>;
312			ranges;
313			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
314				 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
315			clock-names = "pclk", "ipclk";
316			status = "disabled";
317
318			serial_0: serial@10880000 {
319				compatible = "samsung,exynosautov920-uart",
320					     "samsung,exynos850-uart";
321				reg = <0x10880000 0xc0>;
322				interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
323				pinctrl-names = "default";
324				pinctrl-0 = <&uart0_bus>;
325				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
326					 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
327				clock-names = "uart", "clk_uart_baud0";
328				samsung,uart-fifosize = <256>;
329				status = "disabled";
330			};
331		};
332
333		pwm: pwm@109b0000 {
334			compatible = "samsung,exynosautov920-pwm",
335				     "samsung,exynos4210-pwm";
336			reg = <0x109b0000 0x100>;
337			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
338			#pwm-cells = <3>;
339			clocks = <&xtcxo>;
340			clock-names = "timers";
341			status = "disabled";
342		};
343
344		cmu_peric1: clock-controller@10c00000 {
345			compatible = "samsung,exynosautov920-cmu-peric1";
346			reg = <0x10c00000 0x8000>;
347			#clock-cells = <1>;
348
349			clocks = <&xtcxo>,
350				 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>,
351				 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
352			clock-names = "oscclk",
353				      "noc",
354				      "ip";
355		};
356
357		syscon_peric1: syscon@10c20000 {
358			compatible = "samsung,exynosautov920-peric1-sysreg",
359				     "syscon";
360			reg = <0x10c20000 0x2000>;
361		};
362
363		pinctrl_peric1: pinctrl@10c30000 {
364			compatible = "samsung,exynosautov920-pinctrl";
365			reg = <0x10c30000 0x10000>;
366			interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
367		};
368
369		cmu_top: clock-controller@11000000 {
370			compatible = "samsung,exynosautov920-cmu-top";
371			reg = <0x11000000 0x8000>;
372			#clock-cells = <1>;
373
374			clocks = <&xtcxo>;
375			clock-names = "oscclk";
376		};
377
378		pinctrl_alive: pinctrl@11850000 {
379			compatible = "samsung,exynosautov920-pinctrl";
380			reg = <0x11850000 0x10000>;
381
382			wakeup-interrupt-controller {
383				compatible = "samsung,exynosautov920-wakeup-eint";
384			};
385		};
386
387		pmu_system_controller: system-controller@11860000 {
388			compatible = "samsung,exynosautov920-pmu",
389				     "samsung,exynos7-pmu","syscon";
390			reg = <0x11860000 0x10000>;
391		};
392
393		cmu_hsi0: clock-controller@16000000 {
394			compatible = "samsung,exynosautov920-cmu-hsi0";
395			reg = <0x16000000 0x8000>;
396			#clock-cells = <1>;
397
398			clocks = <&xtcxo>,
399				 <&cmu_top DOUT_CLKCMU_HSI0_NOC>;
400			clock-names = "oscclk",
401				      "noc";
402		};
403
404		pinctrl_hsi0: pinctrl@16040000 {
405			compatible = "samsung,exynosautov920-pinctrl";
406			reg = <0x16040000 0x10000>;
407			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
408		};
409
410		cmu_hsi1: clock-controller@16400000 {
411			compatible = "samsung,exynosautov920-cmu-hsi1";
412			reg = <0x16400000 0x8000>;
413			#clock-cells = <1>;
414
415			clocks = <&xtcxo>,
416				 <&cmu_top DOUT_CLKCMU_HSI1_NOC>,
417				 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>,
418				 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>;
419			clock-names = "oscclk",
420				      "noc",
421				      "usbdrd",
422				      "mmc_card";
423		};
424
425		pinctrl_hsi1: pinctrl@16450000 {
426			compatible = "samsung,exynosautov920-pinctrl";
427			reg = <0x16450000 0x10000>;
428			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
429		};
430
431		pinctrl_hsi2: pinctrl@16c10000 {
432			compatible = "samsung,exynosautov920-pinctrl";
433			reg = <0x16c10000 0x10000>;
434			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
435		};
436
437		pinctrl_hsi2ufs: pinctrl@16d20000 {
438			compatible = "samsung,exynosautov920-pinctrl";
439			reg = <0x16d20000 0x10000>;
440			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
441		};
442
443		pinctrl_aud: pinctrl@1a460000 {
444			compatible = "samsung,exynosautov920-pinctrl";
445			reg = <0x1a460000 0x10000>;
446		};
447	};
448
449	timer {
450		compatible = "arm,armv8-timer";
451		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
452			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
453			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
454			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
455			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
456	};
457};
458
459#include "exynosautov920-pinctrl.dtsi"
460