1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Samsung Exynos 9810 SoC device tree source
4 *
5 * Copyright (c) 2024 Markuss Broks <[email protected]>
6 * Copyright (c) 2024 Maksym Holovach <[email protected]>
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "samsung,exynos9810";
13	#address-cells = <2>;
14	#size-cells = <1>;
15
16	interrupt-parent = <&gic>;
17
18	aliases {
19		pinctrl0 = &pinctrl_alive;
20		pinctrl1 = &pinctrl_aud;
21		pinctrl2 = &pinctrl_chub;
22		pinctrl3 = &pinctrl_cmgp;
23		pinctrl4 = &pinctrl_fsys0;
24		pinctrl5 = &pinctrl_fsys1;
25		pinctrl6 = &pinctrl_peric0;
26		pinctrl7 = &pinctrl_peric1;
27		pinctrl8 = &pinctrl_vts;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu-map {
35			cluster0 {
36				core0 {
37					cpu = <&cpu0>;
38				};
39				core1 {
40					cpu = <&cpu1>;
41				};
42				core2 {
43					cpu = <&cpu2>;
44				};
45				core3 {
46					cpu = <&cpu3>;
47				};
48			};
49
50			cluster1 {
51				core0 {
52					cpu = <&cpu4>;
53				};
54				core1 {
55					cpu = <&cpu5>;
56				};
57				core2 {
58					cpu = <&cpu6>;
59				};
60				core3 {
61					cpu = <&cpu7>;
62				};
63			};
64		};
65
66		cpu0: cpu@0 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a55";
69			reg = <0x0>;
70			enable-method = "psci";
71		};
72
73		cpu1: cpu@1 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a55";
76			reg = <0x1>;
77			enable-method = "psci";
78		};
79
80		cpu2: cpu@2 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a55";
83			reg = <0x2>;
84			enable-method = "psci";
85		};
86
87		cpu3: cpu@3 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a55";
90			reg = <0x3>;
91			enable-method = "psci";
92		};
93
94		cpu4: cpu@100 {
95			device_type = "cpu";
96			compatible = "samsung,mongoose-m3";
97			reg = <0x100>;
98			enable-method = "psci";
99		};
100
101		cpu5: cpu@101 {
102			device_type = "cpu";
103			compatible = "samsung,mongoose-m3";
104			reg = <0x101>;
105			enable-method = "psci";
106		};
107
108		cpu6: cpu@102 {
109			device_type = "cpu";
110			compatible = "samsung,mongoose-m3";
111			reg = <0x102>;
112			enable-method = "psci";
113		};
114
115		cpu7: cpu@103 {
116			device_type = "cpu";
117			compatible = "samsung,mongoose-m3";
118			reg = <0x103>;
119			enable-method = "psci";
120		};
121	};
122
123	oscclk: osc-clock {
124		compatible = "fixed-clock";
125		#clock-cells = <0>;
126		clock-output-names = "oscclk";
127	};
128
129	pmu-a55 {
130		compatible = "arm,cortex-a55-pmu";
131		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
132			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
133			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
134			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
135		interrupt-affinity = <&cpu0>,
136				     <&cpu1>,
137				     <&cpu2>,
138				     <&cpu3>;
139	};
140
141	pmu-mongoose-m3 {
142		compatible = "samsung,mongoose-pmu";
143		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
144			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
145			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
146			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
147		interrupt-affinity = <&cpu4>,
148				     <&cpu5>,
149				     <&cpu6>,
150				     <&cpu7>;
151	};
152
153	psci {
154		compatible = "arm,psci";
155		method = "smc";
156		cpu_off = <0x84000002>;
157		cpu_on = <0xc4000003>;
158		cpu_suspend = <0xc4000001>;
159	};
160
161	soc: soc@0 {
162		compatible = "simple-bus";
163		ranges = <0x0 0x0 0x0 0x20000000>;
164
165		#address-cells = <1>;
166		#size-cells = <1>;
167
168		chipid@10000000 {
169			compatible = "samsung,exynos9810-chipid",
170				     "samsung,exynos850-chipid";
171			reg = <0x10000000 0x100>;
172		};
173
174		gic: interrupt-controller@10101000 {
175			compatible = "arm,gic-400";
176			reg = <0x10101000 0x1000>,
177			      <0x10102000 0x1000>,
178			      <0x10104000 0x2000>,
179			      <0x10106000 0x2000>;
180			#interrupt-cells = <3>;
181			interrupt-controller;
182			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
183						 IRQ_TYPE_LEVEL_HIGH)>;
184			#address-cells = <0>;
185			#size-cells = <1>;
186		};
187
188		pinctrl_peric0: pinctrl@10430000 {
189			compatible = "samsung,exynos9810-pinctrl";
190			reg = <0x10430000 0x1000>;
191			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
192		};
193
194		pinctrl_peric1: pinctrl@10830000 {
195			compatible = "samsung,exynos9810-pinctrl";
196			reg = <0x10830000 0x1000>;
197			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
198		};
199
200		pinctrl_fsys0: pinctrl@11050000 {
201			compatible = "samsung,exynos9810-pinctrl";
202			reg = <0x11050000 0x1000>;
203			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
204		};
205
206		pinctrl_fsys1: pinctrl@11430000 {
207			compatible = "samsung,exynos9810-pinctrl";
208			reg = <0x11430000 0x1000>;
209			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
210		};
211
212		pinctrl_vts: pinctrl@13880000 {
213			compatible = "samsung,exynos9810-pinctrl";
214			reg = <0x13880000 0x1000>;
215		};
216
217		pinctrl_chub: pinctrl@13a80000 {
218			compatible = "samsung,exynos9810-pinctrl";
219			reg = <0x13a80000 0x1000>;
220			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
221		};
222
223		pinctrl_alive: pinctrl@14050000 {
224			compatible = "samsung,exynos9810-pinctrl";
225			reg = <0x14050000 0x1000>;
226
227			wakeup-interrupt-controller {
228				compatible = "samsung,exynos9810-wakeup-eint",
229					     "samsung,exynos850-wakeup-eint",
230					     "samsung,exynos7-wakeup-eint";
231			};
232		};
233
234		pmu_system_controller: system-controller@14060000 {
235			compatible = "samsung,exynos9810-pmu",
236				     "samsung,exynos7-pmu", "syscon";
237			reg = <0x14060000 0x10000>;
238		};
239
240		pinctrl_cmgp: pinctrl@14220000 {
241			compatible = "samsung,exynos9810-pinctrl";
242			reg = <0x14220000 0x1000>;
243
244			wakeup-interrupt-controller {
245				compatible = "samsung,exynos9810-wakeup-eint",
246					     "samsung,exynos850-wakeup-eint",
247					     "samsung,exynos7-wakeup-eint";
248			};
249		};
250
251		pinctrl_aud: pinctrl@17c60000 {
252			compatible = "samsung,exynos9810-pinctrl";
253			reg = <0x17c60000 0x1000>;
254		};
255	};
256
257	timer {
258		compatible = "arm,armv8-timer";
259		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
260		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
261			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
262			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
263			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
264		/*
265		 * Non-updatable, broken stock Samsung bootloader does not
266		 * configure CNTFRQ_EL0
267		 */
268		clock-frequency = <26000000>;
269	};
270};
271
272#include "exynos9810-pinctrl.dtsi"
273#include "arm/samsung/exynos-syscon-restart.dtsi"
274