1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Samsung's Exynos 8895 SoC device tree source
4 *
5 * Copyright (c) 2024, Ivaylo Ivanov <[email protected]>
6 */
7
8#include <dt-bindings/clock/samsung,exynos8895.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "samsung,exynos8895";
13	#address-cells = <2>;
14	#size-cells = <1>;
15
16	interrupt-parent = <&gic>;
17
18	aliases {
19		pinctrl0 = &pinctrl_alive;
20		pinctrl1 = &pinctrl_abox;
21		pinctrl2 = &pinctrl_vts;
22		pinctrl3 = &pinctrl_fsys0;
23		pinctrl4 = &pinctrl_fsys1;
24		pinctrl5 = &pinctrl_busc;
25		pinctrl6 = &pinctrl_peric0;
26		pinctrl7 = &pinctrl_peric1;
27	};
28
29	arm-a53-pmu {
30		compatible = "arm,cortex-a53-pmu";
31		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
35		interrupt-affinity = <&cpu0>,
36				     <&cpu1>,
37				     <&cpu2>,
38				     <&cpu3>;
39	};
40
41	mongoose-m2-pmu {
42		compatible = "samsung,mongoose-pmu";
43		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
44			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
45			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
46			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
47		interrupt-affinity = <&cpu4>,
48				     <&cpu5>,
49				     <&cpu6>,
50				     <&cpu7>;
51	};
52
53	cpus {
54		#address-cells = <1>;
55		#size-cells = <0>;
56
57		cpu-map {
58			cluster0 {
59				core0 {
60					cpu = <&cpu0>;
61				};
62				core1 {
63					cpu = <&cpu1>;
64				};
65				core2 {
66					cpu = <&cpu2>;
67				};
68				core3 {
69					cpu = <&cpu3>;
70				};
71			};
72
73			cluster1 {
74				core0 {
75					cpu = <&cpu4>;
76				};
77				core1 {
78					cpu = <&cpu5>;
79				};
80				core2 {
81					cpu = <&cpu6>;
82				};
83				core3 {
84					cpu = <&cpu7>;
85				};
86			};
87		};
88
89		cpu4: cpu@0 {
90			device_type = "cpu";
91			compatible = "samsung,mongoose-m2";
92			reg = <0x0>;
93			enable-method = "psci";
94		};
95
96		cpu5: cpu@1 {
97			device_type = "cpu";
98			compatible = "samsung,mongoose-m2";
99			reg = <0x1>;
100			enable-method = "psci";
101		};
102
103		cpu6: cpu@2 {
104			device_type = "cpu";
105			compatible = "samsung,mongoose-m2";
106			reg = <0x2>;
107			enable-method = "psci";
108		};
109
110		cpu7: cpu@3 {
111			device_type = "cpu";
112			compatible = "samsung,mongoose-m2";
113			reg = <0x3>;
114			enable-method = "psci";
115		};
116
117		cpu0: cpu@100 {
118			device_type = "cpu";
119			compatible = "arm,cortex-a53";
120			reg = <0x100>;
121			enable-method = "psci";
122		};
123
124		cpu1: cpu@101 {
125			device_type = "cpu";
126			compatible = "arm,cortex-a53";
127			reg = <0x101>;
128			enable-method = "psci";
129		};
130
131		cpu2: cpu@102 {
132			device_type = "cpu";
133			compatible = "arm,cortex-a53";
134			reg = <0x102>;
135			enable-method = "psci";
136		};
137
138		cpu3: cpu@103 {
139			device_type = "cpu";
140			compatible = "arm,cortex-a53";
141			reg = <0x103>;
142			enable-method = "psci";
143		};
144	};
145
146	oscclk: osc-clock {
147		compatible = "fixed-clock";
148		#clock-cells = <0>;
149		clock-output-names = "oscclk";
150	};
151
152	psci {
153		compatible = "arm,psci";
154		method = "smc";
155		cpu_off = <0x84000002>;
156		cpu_on = <0xc4000003>;
157		cpu_suspend = <0xc4000001>;
158	};
159
160	soc: soc@0 {
161		compatible = "simple-bus";
162		ranges = <0x0 0x0 0x0 0x20000000>;
163
164		#address-cells = <1>;
165		#size-cells = <1>;
166
167		chipid@10000000 {
168			compatible = "samsung,exynos8895-chipid",
169				     "samsung,exynos850-chipid";
170			reg = <0x10000000 0x24>;
171		};
172
173		cmu_peris: clock-controller@10010000 {
174			compatible = "samsung,exynos8895-cmu-peris";
175			reg = <0x10010000 0x8000>;
176			#clock-cells = <1>;
177			clocks = <&oscclk>,
178				 <&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
179			clock-names = "oscclk", "bus";
180		};
181
182		timer@10040000 {
183			compatible = "samsung,exynos8895-mct",
184				     "samsung,exynos4210-mct";
185			reg = <0x10040000 0x800>;
186			clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
187			clock-names = "fin_pll", "mct";
188			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
189				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
190				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
191				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
192				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
193				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
194				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
195				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
196				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
197				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
198				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
199				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
200		};
201
202		gic: interrupt-controller@10201000 {
203			compatible = "arm,gic-400";
204			reg = <0x10201000 0x1000>,
205			      <0x10202000 0x1000>,
206			      <0x10204000 0x2000>,
207			      <0x10206000 0x2000>;
208			#interrupt-cells = <3>;
209			interrupt-controller;
210			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
211						 IRQ_TYPE_LEVEL_HIGH)>;
212			#address-cells = <0>;
213			#size-cells = <1>;
214		};
215
216		cmu_peric0: clock-controller@10400000 {
217			compatible = "samsung,exynos8895-cmu-peric0";
218			reg = <0x10400000 0x8000>;
219			#clock-cells = <1>;
220			clocks = <&oscclk>,
221				 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
222				 <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>,
223				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>,
224				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>,
225				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>,
226				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>;
227			clock-names = "oscclk", "bus", "uart", "usi0",
228				      "usi1", "usi2", "usi3";
229		};
230
231		serial_0: serial@10430000 {
232			compatible = "samsung,exynos8895-uart";
233			reg = <0x10430000 0x100>;
234			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>,
235				 <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>;
236			clock-names = "uart", "clk_uart_baud0";
237			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
238			pinctrl-names = "default";
239			pinctrl-0 = <&uart0_bus>;
240			samsung,uart-fifosize = <256>;
241			status = "disabled";
242		};
243
244		pinctrl_peric0: pinctrl@104d0000 {
245			compatible = "samsung,exynos8895-pinctrl";
246			reg = <0x104d0000 0x1000>;
247			interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
248		};
249
250		cmu_peric1: clock-controller@10800000 {
251			compatible = "samsung,exynos8895-cmu-peric1";
252			reg = <0x10800000 0x8000>;
253			#clock-cells = <1>;
254			clocks = <&oscclk>,
255				 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
256				 <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>,
257				 <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>,
258				 <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>,
259				 <&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>,
260				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI04>,
261				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI05>,
262				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI06>,
263				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI07>,
264				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI08>,
265				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI09>,
266				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI10>,
267				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI11>,
268				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI12>,
269				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI13>;
270			clock-names = "oscclk", "bus", "speedy", "cam0",
271				      "cam1", "uart", "usi4", "usi5",
272				      "usi6", "usi7", "usi8", "usi9",
273				      "usi10", "usi11", "usi12", "usi13";
274		};
275
276		serial_1: serial@10830000 {
277			compatible = "samsung,exynos8895-uart";
278			reg = <0x10830000 0x100>;
279			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>,
280				 <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>;
281			clock-names = "uart", "clk_uart_baud0";
282			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
283			pinctrl-names = "default";
284			pinctrl-0 = <&uart1_bus>;
285			samsung,uart-fifosize = <256>;
286			status = "disabled";
287		};
288
289		pinctrl_peric1: pinctrl@10980000 {
290			compatible = "samsung,exynos8895-pinctrl";
291			reg = <0x10980000 0x1000>;
292			interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
293		};
294
295		hsi2c_1: i2c@10990000 {
296			compatible = "samsung,exynos8895-hsi2c";
297			reg = <0x10990000 0x1000>;
298			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK>;
299			clock-names = "hsi2c";
300			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
301			pinctrl-0 = <&hsi2c1_bus>;
302			pinctrl-names = "default";
303			status = "disabled";
304		};
305
306		hsi2c_2: i2c@109a0000 {
307			compatible = "samsung,exynos8895-hsi2c";
308			reg = <0x109a0000 0x1000>;
309			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK>;
310			clock-names = "hsi2c";
311			interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
312			pinctrl-0 = <&hsi2c2_bus>;
313			pinctrl-names = "default";
314			status = "disabled";
315		};
316
317		hsi2c_3: i2c@109b0000 {
318			compatible = "samsung,exynos8895-hsi2c";
319			reg = <0x109b0000 0x1000>;
320			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK>;
321			clock-names = "hsi2c";
322			interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
323			pinctrl-0 = <&hsi2c3_bus>;
324			pinctrl-names = "default";
325			status = "disabled";
326		};
327
328		hsi2c_4: i2c@109c0000 {
329			compatible = "samsung,exynos8895-hsi2c";
330			reg = <0x109c0000 0x1000>;
331			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK>;
332			clock-names = "hsi2c";
333			interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
334			pinctrl-0 = <&hsi2c4_bus>;
335			pinctrl-names = "default";
336			status = "disabled";
337		};
338
339		spi_0: spi@109d0000 {
340			compatible = "samsung,exynos8895-spi",
341				     "samsung,exynos850-spi";
342			reg = <0x109d0000 0x100>;
343			#address-cells = <1>;
344			#size-cells = <0>;
345			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_PCLK>,
346				 <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK>;
347			clock-names = "spi", "spi_busclk0";
348			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
349			pinctrl-0 = <&spi0_bus>;
350			pinctrl-names = "default";
351			status = "disabled";
352		};
353
354		spi_1: spi@109e0000 {
355			compatible = "samsung,exynos8895-spi",
356				     "samsung,exynos850-spi";
357			reg = <0x109e0000 0x100>;
358			#address-cells = <1>;
359			#size-cells = <0>;
360			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_PCLK>,
361				 <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK>;
362			clock-names = "spi", "spi_busclk0";
363			interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
364			pinctrl-0 = <&spi1_bus>;
365			pinctrl-names = "default";
366			status = "disabled";
367		};
368
369		cmu_fsys0: clock-controller@11000000 {
370			compatible = "samsung,exynos8895-cmu-fsys0";
371			reg = <0x11000000 0x8000>;
372			#clock-cells = <1>;
373			clocks = <&oscclk>,
374				 <&cmu_top CLK_DOUT_CMU_FSYS0_BUS>,
375				 <&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>,
376				 <&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>,
377				 <&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>,
378				 <&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>;
379			clock-names = "oscclk", "bus", "dpgtc", "mmc",
380				      "ufs", "usbdrd30";
381		};
382
383		pinctrl_fsys0: pinctrl@11050000 {
384			compatible = "samsung,exynos8895-pinctrl";
385			reg = <0x11050000 0x1000>;
386			interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
387		};
388
389		cmu_fsys1: clock-controller@11400000 {
390			compatible = "samsung,exynos8895-cmu-fsys1";
391			reg = <0x11400000 0x8000>;
392			#clock-cells = <1>;
393			clocks = <&oscclk>,
394				 <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
395				 <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
396				 <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
397				 <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
398			clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
399		};
400
401		pinctrl_fsys1: pinctrl@11430000 {
402			compatible = "samsung,exynos8895-pinctrl";
403			reg = <0x11430000 0x1000>;
404			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
405		};
406
407		pinctrl_abox: pinctrl@13e60000 {
408			compatible = "samsung,exynos8895-pinctrl";
409			reg = <0x13e60000 0x1000>;
410		};
411
412		pinctrl_vts: pinctrl@14080000 {
413			compatible = "samsung,exynos8895-pinctrl";
414			reg = <0x14080000 0x1000>;
415		};
416
417		pinctrl_busc: pinctrl@15a30000 {
418			compatible = "samsung,exynos8895-pinctrl";
419			reg = <0x15a30000 0x1000>;
420			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
421		};
422
423		cmu_top: clock-controller@15a80000 {
424			compatible = "samsung,exynos8895-cmu-top";
425			reg = <0x15a80000 0x8000>;
426			#clock-cells = <1>;
427			clocks = <&oscclk>;
428			clock-names = "oscclk";
429		};
430
431		pmu_system_controller: system-controller@16480000 {
432			compatible = "samsung,exynos8895-pmu",
433				     "samsung,exynos7-pmu", "syscon";
434			reg = <0x16480000 0x10000>;
435		};
436
437		pinctrl_alive: pinctrl@164b0000 {
438			compatible = "samsung,exynos8895-pinctrl";
439			reg = <0x164b0000 0x1000>;
440
441			wakeup-interrupt-controller {
442				compatible = "samsung,exynos8895-wakeup-eint",
443					     "samsung,exynos7-wakeup-eint";
444				interrupt-parent = <&gic>;
445				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
446			};
447		};
448	};
449
450	timer {
451		compatible = "arm,armv8-timer";
452		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
453		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
454			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
455			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
456			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
457		/*
458		 * Non-updatable, broken stock Samsung bootloader does not
459		 * configure CNTFRQ_EL0
460		 */
461		clock-frequency = <26000000>;
462	};
463};
464
465#include "exynos8895-pinctrl.dtsi"
466#include "arm/samsung/exynos-syscon-restart.dtsi"
467