1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3 4/ { 5 compatible = "brcm,bcm2712"; 6 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 interrupt-parent = <&gicv2>; 11 12 clocks { 13 /* The oscillator is the root of the clock tree. */ 14 clk_osc: clk-osc { 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-output-names = "osc"; 18 clock-frequency = <54000000>; 19 }; 20 21 clk_vpu: clk-vpu { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <750000000>; 25 clock-output-names = "vpu-clock"; 26 }; 27 28 clk_uart: clk-uart { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <9216000>; 32 clock-output-names = "uart-clock"; 33 }; 34 35 clk_emmc2: clk-emmc2 { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <200000000>; 39 clock-output-names = "emmc2-clock"; 40 }; 41 }; 42 43 cpus: cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 /* Source for L1 d/i cache-line-size, cache-sets, cache-size 48 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en 49 * Source for L2 cache-line-size and cache-sets: 50 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en 51 * and for cache-size: 52 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 53 */ 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a76"; 57 reg = <0x000>; 58 enable-method = "psci"; 59 d-cache-size = <0x10000>; 60 d-cache-line-size = <64>; 61 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 62 i-cache-size = <0x10000>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 65 next-level-cache = <&l2_cache_l0>; 66 67 l2_cache_l0: l2-cache-l0 { 68 compatible = "cache"; 69 cache-size = <0x80000>; 70 cache-line-size = <64>; 71 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 72 cache-level = <2>; 73 cache-unified; 74 next-level-cache = <&l3_cache>; 75 }; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a76"; 81 reg = <0x100>; 82 enable-method = "psci"; 83 d-cache-size = <0x10000>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 86 i-cache-size = <0x10000>; 87 i-cache-line-size = <64>; 88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 89 next-level-cache = <&l2_cache_l1>; 90 91 l2_cache_l1: l2-cache-l1 { 92 compatible = "cache"; 93 cache-size = <0x80000>; 94 cache-line-size = <64>; 95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_cache>; 99 }; 100 }; 101 102 cpu2: cpu@2 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x200>; 106 enable-method = "psci"; 107 d-cache-size = <0x10000>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 110 i-cache-size = <0x10000>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 113 next-level-cache = <&l2_cache_l2>; 114 115 l2_cache_l2: l2-cache-l2 { 116 compatible = "cache"; 117 cache-size = <0x80000>; 118 cache-line-size = <64>; 119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_cache>; 123 }; 124 }; 125 126 cpu3: cpu@3 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a76"; 129 reg = <0x300>; 130 enable-method = "psci"; 131 d-cache-size = <0x10000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 134 i-cache-size = <0x10000>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 137 next-level-cache = <&l2_cache_l3>; 138 139 l2_cache_l3: l2-cache-l3 { 140 compatible = "cache"; 141 cache-size = <0x80000>; 142 cache-line-size = <64>; 143 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&l3_cache>; 147 }; 148 }; 149 150 /* Source for cache-line-size and cache-sets: 151 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en 152 * Source for cache-size: 153 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 154 */ 155 l3_cache: l3-cache { 156 compatible = "cache"; 157 cache-size = <0x200000>; 158 cache-line-size = <64>; 159 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set 160 cache-level = <3>; 161 cache-unified; 162 }; 163 }; 164 165 psci { 166 method = "smc"; 167 compatible = "arm,psci-1.0", "arm,psci-0.2"; 168 }; 169 170 rmem: reserved-memory { 171 ranges; 172 #address-cells = <2>; 173 #size-cells = <2>; 174 175 atf@0 { 176 reg = <0x0 0x0 0x0 0x80000>; 177 no-map; 178 }; 179 180 cma: linux,cma { 181 compatible = "shared-dma-pool"; 182 size = <0x0 0x4000000>; /* 64MB */ 183 reusable; 184 linux,cma-default; 185 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; 186 }; 187 }; 188 189 soc: soc@107c000000 { 190 compatible = "simple-bus"; 191 ranges = <0x00000000 0x10 0x00000000 0x80000000>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 195 sdio1: mmc@fff000 { 196 compatible = "brcm,bcm2712-sdhci", 197 "brcm,sdhci-brcmstb"; 198 reg = <0x00fff000 0x260>, 199 <0x00fff400 0x200>; 200 reg-names = "host", "cfg"; 201 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&clk_emmc2>; 203 clock-names = "sw_sdio"; 204 mmc-ddr-3_3v; 205 }; 206 207 system_timer: timer@7c003000 { 208 compatible = "brcm,bcm2835-system-timer"; 209 reg = <0x7c003000 0x1000>; 210 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 214 clock-frequency = <1000000>; 215 }; 216 217 mailbox: mailbox@7c013880 { 218 compatible = "brcm,bcm2835-mbox"; 219 reg = <0x7c013880 0x40>; 220 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 221 #mbox-cells = <0>; 222 }; 223 224 uart10: serial@7d001000 { 225 compatible = "arm,pl011", "arm,primecell"; 226 reg = <0x7d001000 0x200>; 227 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&clk_uart>, <&clk_vpu>; 229 clock-names = "uartclk", "apb_pclk"; 230 arm,primecell-periphid = <0x00341011>; 231 status = "disabled"; 232 }; 233 234 interrupt-controller@7d517000 { 235 compatible = "brcm,bcm7271-l2-intc"; 236 reg = <0x7d517000 0x10>; 237 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-controller; 239 #interrupt-cells = <1>; 240 }; 241 242 gio_aon: gpio@7d517c00 { 243 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 244 reg = <0x7d517c00 0x40>; 245 gpio-controller; 246 #gpio-cells = <2>; 247 brcm,gpio-bank-widths = <17 6>; 248 /* The lack of 'interrupt-controller' property here is intended: 249 * don't use GIO_AON as an interrupt controller because it will 250 * clash with the firmware monitoring the PMIC interrupt via the VPU. 251 */ 252 }; 253 254 gicv2: interrupt-controller@7fff9000 { 255 compatible = "arm,gic-400"; 256 reg = <0x7fff9000 0x1000>, 257 <0x7fffa000 0x2000>, 258 <0x7fffc000 0x2000>, 259 <0x7fffe000 0x2000>; 260 interrupt-controller; 261 #interrupt-cells = <3>; 262 }; 263 264 aon_intr: interrupt-controller@7d510600 { 265 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 266 reg = <0x7d510600 0x30>; 267 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-controller; 269 #interrupt-cells = <1>; 270 }; 271 272 pixelvalve0: pixelvalve@7c410000 { 273 compatible = "brcm,bcm2712-pixelvalve0"; 274 reg = <0x7c410000 0x100>; 275 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 pixelvalve1: pixelvalve@7c411000 { 279 compatible = "brcm,bcm2712-pixelvalve1"; 280 reg = <0x7c411000 0x100>; 281 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 282 }; 283 284 mop: mop@7c500000 { 285 compatible = "brcm,bcm2712-mop"; 286 reg = <0x7c500000 0x28>; 287 interrupt-parent = <&disp_intr>; 288 interrupts = <1>; 289 }; 290 291 moplet: moplet@7c501000 { 292 compatible = "brcm,bcm2712-moplet"; 293 reg = <0x7c501000 0x20>; 294 interrupt-parent = <&disp_intr>; 295 interrupts = <0>; 296 }; 297 298 disp_intr: interrupt-controller@7c502000 { 299 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 300 reg = <0x7c502000 0x30>; 301 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-controller; 303 #interrupt-cells = <1>; 304 }; 305 306 dvp: clock@7c700000 { 307 compatible = "brcm,brcm2711-dvp"; 308 reg = <0x7c700000 0x10>; 309 clocks = <&clk_108MHz>; 310 #clock-cells = <1>; 311 #reset-cells = <1>; 312 }; 313 314 ddc0: i2c@7d508200 { 315 compatible = "brcm,brcmstb-i2c"; 316 reg = <0x7d508200 0x58>; 317 interrupt-parent = <&bsc_irq>; 318 interrupts = <1>; 319 clock-frequency = <97500>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 }; 323 324 ddc1: i2c@7d508280 { 325 compatible = "brcm,brcmstb-i2c"; 326 reg = <0x7d508280 0x58>; 327 interrupt-parent = <&bsc_irq>; 328 interrupts = <2>; 329 clock-frequency = <97500>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 }; 333 334 bsc_irq: interrupt-controller@7d508380 { 335 compatible = "brcm,bcm7271-l2-intc"; 336 reg = <0x7d508380 0x10>; 337 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 338 interrupt-controller; 339 #interrupt-cells = <1>; 340 }; 341 342 main_irq: interrupt-controller@7d508400 { 343 compatible = "brcm,bcm7271-l2-intc"; 344 reg = <0x7d508400 0x10>; 345 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-controller; 347 #interrupt-cells = <1>; 348 }; 349 350 hdmi0: hdmi@7c701400 { 351 compatible = "brcm,bcm2712-hdmi0"; 352 reg = <0x7c701400 0x300>, 353 <0x7c701000 0x200>, 354 <0x7c701d00 0x300>, 355 <0x7c702000 0x80>, 356 <0x7c703800 0x200>, 357 <0x7c704000 0x800>, 358 <0x7c700100 0x80>, 359 <0x7d510800 0x100>, 360 <0x7c720000 0x100>; 361 reg-names = "hdmi", 362 "dvp", 363 "phy", 364 "rm", 365 "packet", 366 "metadata", 367 "csc", 368 "cec", 369 "hd"; 370 resets = <&dvp 1>; 371 interrupt-parent = <&aon_intr>; 372 interrupts = <1>, <2>, <3>, 373 <7>, <8>; 374 interrupt-names = "cec-tx", "cec-rx", "cec-low", 375 "hpd-connected", "hpd-removed"; 376 ddc = <&ddc0>; 377 }; 378 379 hdmi1: hdmi@7c706400 { 380 compatible = "brcm,bcm2712-hdmi1"; 381 reg = <0x7c706400 0x300>, 382 <0x7c706000 0x200>, 383 <0x7c706d00 0x300>, 384 <0x7c707000 0x80>, 385 <0x7c708800 0x200>, 386 <0x7c709000 0x800>, 387 <0x7c700180 0x80>, 388 <0x7d511000 0x100>, 389 <0x7c720000 0x100>; 390 reg-names = "hdmi", 391 "dvp", 392 "phy", 393 "rm", 394 "packet", 395 "metadata", 396 "csc", 397 "cec", 398 "hd"; 399 resets = <&dvp 2>; 400 interrupt-parent = <&aon_intr>; 401 interrupts = <11>, <12>, <13>, 402 <14>, <15>; 403 interrupt-names = "cec-tx", "cec-rx", "cec-low", 404 "hpd-connected", "hpd-removed"; 405 ddc = <&ddc1>; 406 }; 407 }; 408 409 axi: axi { 410 compatible = "simple-bus"; 411 #address-cells = <2>; 412 #size-cells = <2>; 413 414 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 415 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 416 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 417 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 418 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 419 420 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 421 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 422 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 423 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 424 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 425 426 vc4: gpu { 427 compatible = "brcm,bcm2712-vc6"; 428 }; 429 }; 430 431 timer { 432 compatible = "arm,armv8-timer"; 433 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 434 IRQ_TYPE_LEVEL_LOW)>, 435 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 436 IRQ_TYPE_LEVEL_LOW)>, 437 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 438 IRQ_TYPE_LEVEL_LOW)>, 439 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 440 IRQ_TYPE_LEVEL_LOW)>, 441 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | 442 IRQ_TYPE_LEVEL_LOW)>; 443 }; 444 445 clk_27MHz: clk-27M { 446 #clock-cells = <0>; 447 compatible = "fixed-clock"; 448 clock-frequency = <27000000>; 449 clock-output-names = "27MHz-clock"; 450 }; 451 452 clk_108MHz: clk-108M { 453 #clock-cells = <0>; 454 compatible = "fixed-clock"; 455 clock-frequency = <108000000>; 456 clock-output-names = "108MHz-clock"; 457 }; 458 459 hvs: hvs@107c580000 { 460 compatible = "brcm,bcm2712-hvs"; 461 reg = <0x10 0x7c580000 0x0 0x1a000>; 462 interrupt-parent = <&disp_intr>; 463 interrupts = <2>, <9>, <16>; 464 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; 465 }; 466}; 467