1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2024 Blaize, Inc. All rights reserved.
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	interrupt-parent = <&gic>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-a53";
22			reg = <0x0 0x0>;
23			device_type = "cpu";
24			enable-method = "psci";
25			next-level-cache = <&l2>;
26		};
27
28		cpu1: cpu@1 {
29			compatible = "arm,cortex-a53";
30			reg = <0x0 0x1>;
31			device_type = "cpu";
32			enable-method = "psci";
33			next-level-cache = <&l2>;
34		};
35
36		l2: l2-cache0 {
37			compatible = "cache";
38			cache-level = <2>;
39			cache-unified;
40		};
41	};
42
43	firmware {
44		scmi {
45			compatible = "arm,scmi-smc";
46			arm,smc-id = <0x82002000>;
47			#address-cells = <1>;
48			#size-cells = <0>;
49
50			shmem = <&scmi0_shm>;
51
52			scmi_clk: protocol@14 {
53				reg = <0x14>;
54				#clock-cells = <1>;
55			};
56
57			scmi_rst: protocol@16 {
58				reg = <0x16>;
59				#reset-cells = <1>;
60			};
61		};
62	};
63
64	pmu {
65		compatible = "arm,cortex-a53-pmu";
66		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
67			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
68		interrupt-affinity = <&cpu0>, <&cpu1>;
69	};
70
71	psci {
72		compatible = "arm,psci-1.0", "arm,psci-0.2";
73		method = "smc";
74	};
75
76	reserved-memory {
77		#address-cells = <2>;
78		#size-cells = <2>;
79		ranges;
80
81		/* SCMI reserved buffer space on DDR space */
82		scmi0_shm: scmi-shmem@800 {
83			compatible = "arm,scmi-shmem";
84			reg = <0x0 0x800 0x0 0x80>;
85		};
86	};
87
88	timer {
89		compatible = "arm,armv8-timer";
90		interrupts = /* Physical Secure PPI */
91			     <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
92					  IRQ_TYPE_LEVEL_LOW)>,
93			     /* Physical Non-Secure PPI */
94			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
95					  IRQ_TYPE_LEVEL_LOW)>,
96			     /* Hypervisor PPI */
97			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
98					  IRQ_TYPE_LEVEL_LOW)>,
99			     /* Virtual PPI */
100			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
101					  IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	soc@200000000 {
105		compatible = "simple-bus";
106		#address-cells = <1>;
107		#size-cells = <1>;
108		ranges = <0x0 0x2 0x0 0x850000>;
109
110		gic: interrupt-controller@410000 {
111			compatible = "arm,gic-400";
112			reg = <0x410000 0x20000>,
113			      <0x420000 0x20000>,
114			      <0x440000 0x20000>,
115			      <0x460000 0x20000>;
116			#interrupt-cells = <3>;
117			#address-cells = <0>;
118			interrupt-controller;
119			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
120						 IRQ_TYPE_LEVEL_LOW)>;
121		};
122
123		uart0: serial@4d0000 {
124			compatible = "ns16550a";
125			reg = <0x4d0000 0x1000>;
126			clocks = <&scmi_clk 59>;
127			resets = <&scmi_rst 59>;
128			reg-shift = <2>;
129			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
130			status = "disabled";
131		};
132
133		uart1: serial@4e0000 {
134			compatible = "ns16550a";
135			reg = <0x4e0000 0x1000>;
136			clocks = <&scmi_clk 60>;
137			resets = <&scmi_rst 60>;
138			reg-shift = <2>;
139			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
140			status = "disabled";
141		};
142
143		i2c0: i2c@4f0000 {
144			compatible = "snps,designware-i2c";
145			reg = <0x4f0000 0x1000>;
146			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
147			clocks = <&scmi_clk 54>;
148			resets = <&scmi_rst 54>;
149			#address-cells = <1>;
150			#size-cells = <0>;
151			status = "disabled";
152		};
153
154		i2c1: i2c@500000 {
155			compatible = "snps,designware-i2c";
156			reg = <0x500000 0x1000>;
157			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
158			clocks = <&scmi_clk 55>;
159			resets = <&scmi_rst 55>;
160			#address-cells = <1>;
161			#size-cells = <0>;
162			status = "disabled";
163		};
164
165		i2c2: i2c@510000 {
166			compatible = "snps,designware-i2c";
167			reg = <0x510000 0x1000>;
168			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
169			clocks = <&scmi_clk 56>;
170			resets = <&scmi_rst 56>;
171			#address-cells = <1>;
172			#size-cells = <0>;
173			status = "disabled";
174		};
175
176		i2c3: i2c@520000 {
177			compatible = "snps,designware-i2c";
178			reg = <0x520000 0x1000>;
179			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
180			clocks = <&scmi_clk 57>;
181			resets = <&scmi_rst 57>;
182			#address-cells = <1>;
183			#size-cells = <0>;
184			status = "disabled";
185		};
186
187		i2c4: i2c@530000 {
188			compatible = "snps,designware-i2c";
189			reg = <0x530000 0x1000>;
190			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
191			clocks = <&scmi_clk 58>;
192			resets = <&scmi_rst 58>;
193			#address-cells = <1>;
194			#size-cells = <0>;
195			status = "disabled";
196		};
197
198		arm_cc712: crypto@550000 {
199			compatible = "arm,cryptocell-712-ree";
200			reg = <0x550000 0x1000>;
201			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
202			clocks = <&scmi_clk 7>;
203		};
204	};
205};
206