1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <[email protected]> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun6i-rtc.h> 8#include <dt-bindings/clock/sun8i-de2.h> 9#include <dt-bindings/clock/sun8i-r-ccu.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/sun50i-a64-ccu.h> 12#include <dt-bindings/reset/sun8i-de2.h> 13#include <dt-bindings/reset/sun8i-r-ccu.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 chosen { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges; 25 26 simplefb_lcd: framebuffer-lcd { 27 compatible = "allwinner,simple-framebuffer", 28 "simple-framebuffer"; 29 allwinner,pipeline = "mixer0-lcd0"; 30 clocks = <&ccu CLK_TCON0>, 31 <&display_clocks CLK_MIXER0>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "allwinner,simple-framebuffer", 37 "simple-framebuffer"; 38 allwinner,pipeline = "mixer1-lcd1-hdmi"; 39 clocks = <&display_clocks CLK_MIXER1>, 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 41 status = "disabled"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a53"; 51 device_type = "cpu"; 52 reg = <0>; 53 enable-method = "psci"; 54 clocks = <&ccu CLK_CPUX>; 55 clock-names = "cpu"; 56 #cooling-cells = <2>; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&l2_cache>; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53"; 68 device_type = "cpu"; 69 reg = <1>; 70 enable-method = "psci"; 71 clocks = <&ccu CLK_CPUX>; 72 clock-names = "cpu"; 73 #cooling-cells = <2>; 74 i-cache-size = <0x8000>; 75 i-cache-line-size = <64>; 76 i-cache-sets = <256>; 77 d-cache-size = <0x8000>; 78 d-cache-line-size = <64>; 79 d-cache-sets = <128>; 80 next-level-cache = <&l2_cache>; 81 }; 82 83 cpu2: cpu@2 { 84 compatible = "arm,cortex-a53"; 85 device_type = "cpu"; 86 reg = <2>; 87 enable-method = "psci"; 88 clocks = <&ccu CLK_CPUX>; 89 clock-names = "cpu"; 90 #cooling-cells = <2>; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&l2_cache>; 98 }; 99 100 cpu3: cpu@3 { 101 compatible = "arm,cortex-a53"; 102 device_type = "cpu"; 103 reg = <3>; 104 enable-method = "psci"; 105 clocks = <&ccu CLK_CPUX>; 106 clock-names = "cpu"; 107 #cooling-cells = <2>; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <256>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&l2_cache>; 115 }; 116 117 l2_cache: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 cache-unified; 121 cache-size = <0x80000>; 122 cache-line-size = <64>; 123 cache-sets = <512>; 124 }; 125 }; 126 127 de: display-engine { 128 compatible = "allwinner,sun50i-a64-display-engine"; 129 allwinner,pipelines = <&mixer0>, 130 <&mixer1>; 131 status = "disabled"; 132 }; 133 134 gpu_opp_table: opp-table-gpu { 135 compatible = "operating-points-v2"; 136 137 opp-432000000 { 138 opp-hz = /bits/ 64 <432000000>; 139 }; 140 }; 141 142 osc24M: osc24M-clk { 143 #clock-cells = <0>; 144 compatible = "fixed-clock"; 145 clock-frequency = <24000000>; 146 clock-output-names = "osc24M"; 147 }; 148 149 osc32k: osc32k-clk { 150 #clock-cells = <0>; 151 compatible = "fixed-clock"; 152 clock-frequency = <32768>; 153 clock-output-names = "ext-osc32k"; 154 }; 155 156 pmu { 157 compatible = "arm,cortex-a53-pmu"; 158 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 162 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 163 }; 164 165 psci { 166 compatible = "arm,psci-0.2"; 167 method = "smc"; 168 }; 169 170 sound: sound { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 compatible = "simple-audio-card"; 174 simple-audio-card,name = "sun50i-a64-audio"; 175 simple-audio-card,aux-devs = <&codec_analog>; 176 simple-audio-card,routing = 177 "Left DAC", "DACL", 178 "Right DAC", "DACR", 179 "ADCL", "Left ADC", 180 "ADCR", "Right ADC"; 181 status = "disabled"; 182 183 simple-audio-card,dai-link@0 { 184 format = "i2s"; 185 frame-master = <&link0_cpu>; 186 bitclock-master = <&link0_cpu>; 187 mclk-fs = <128>; 188 189 link0_cpu: cpu { 190 sound-dai = <&dai>; 191 }; 192 193 link0_codec: codec { 194 sound-dai = <&codec 0>; 195 }; 196 }; 197 }; 198 199 timer { 200 compatible = "arm,armv8-timer"; 201 allwinner,erratum-unknown1; 202 arm,no-tick-in-suspend; 203 interrupts = <GIC_PPI 13 204 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 205 <GIC_PPI 14 206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 209 <GIC_PPI 10 210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 211 }; 212 213 thermal-zones { 214 cpu_thermal: cpu0-thermal { 215 /* milliseconds */ 216 polling-delay-passive = <0>; 217 polling-delay = <0>; 218 thermal-sensors = <&ths 0>; 219 220 cooling-maps { 221 map0 { 222 trip = <&cpu_alert0>; 223 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 224 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 225 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 226 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 227 }; 228 map1 { 229 trip = <&cpu_alert1>; 230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 234 }; 235 }; 236 237 trips { 238 cpu_alert0: cpu-alert0 { 239 /* milliCelsius */ 240 temperature = <75000>; 241 hysteresis = <2000>; 242 type = "passive"; 243 }; 244 245 cpu_alert1: cpu-alert1 { 246 /* milliCelsius */ 247 temperature = <90000>; 248 hysteresis = <2000>; 249 type = "hot"; 250 }; 251 252 cpu_crit: cpu-crit { 253 /* milliCelsius */ 254 temperature = <110000>; 255 hysteresis = <2000>; 256 type = "critical"; 257 }; 258 }; 259 }; 260 261 gpu0_thermal: gpu0-thermal { 262 /* milliseconds */ 263 polling-delay-passive = <0>; 264 polling-delay = <0>; 265 thermal-sensors = <&ths 1>; 266 267 trips { 268 gpu0_crit: gpu0-crit { 269 temperature = <110000>; 270 hysteresis = <2000>; 271 type = "critical"; 272 }; 273 }; 274 }; 275 276 gpu1_thermal: gpu1-thermal { 277 /* milliseconds */ 278 polling-delay-passive = <0>; 279 polling-delay = <0>; 280 thermal-sensors = <&ths 2>; 281 282 trips { 283 gpu1_crit: gpu1-crit { 284 temperature = <110000>; 285 hysteresis = <2000>; 286 type = "critical"; 287 }; 288 }; 289 }; 290 }; 291 292 soc { 293 compatible = "simple-bus"; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 ranges; 297 298 bus@1000000 { 299 compatible = "allwinner,sun50i-a64-de2"; 300 reg = <0x1000000 0x400000>; 301 allwinner,sram = <&de2_sram 1>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges = <0 0x1000000 0x400000>; 305 306 display_clocks: clock@0 { 307 compatible = "allwinner,sun50i-a64-de2-clk"; 308 reg = <0x0 0x10000>; 309 clocks = <&ccu CLK_BUS_DE>, 310 <&ccu CLK_DE>; 311 clock-names = "bus", 312 "mod"; 313 resets = <&ccu RST_BUS_DE>; 314 #clock-cells = <1>; 315 #reset-cells = <1>; 316 }; 317 318 rotate: rotate@20000 { 319 compatible = "allwinner,sun50i-a64-de2-rotate", 320 "allwinner,sun8i-a83t-de2-rotate"; 321 reg = <0x20000 0x10000>; 322 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&display_clocks CLK_BUS_ROT>, 324 <&display_clocks CLK_ROT>; 325 clock-names = "bus", 326 "mod"; 327 resets = <&display_clocks RST_ROT>; 328 }; 329 330 mixer0: mixer@100000 { 331 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 332 reg = <0x100000 0x100000>; 333 clocks = <&display_clocks CLK_BUS_MIXER0>, 334 <&display_clocks CLK_MIXER0>; 335 clock-names = "bus", 336 "mod"; 337 resets = <&display_clocks RST_MIXER0>; 338 339 ports { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 343 mixer0_out: port@1 { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 reg = <1>; 347 348 mixer0_out_tcon0: endpoint@0 { 349 reg = <0>; 350 remote-endpoint = <&tcon0_in_mixer0>; 351 }; 352 353 mixer0_out_tcon1: endpoint@1 { 354 reg = <1>; 355 remote-endpoint = <&tcon1_in_mixer0>; 356 }; 357 }; 358 }; 359 }; 360 361 mixer1: mixer@200000 { 362 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 363 reg = <0x200000 0x100000>; 364 clocks = <&display_clocks CLK_BUS_MIXER1>, 365 <&display_clocks CLK_MIXER1>; 366 clock-names = "bus", 367 "mod"; 368 resets = <&display_clocks RST_MIXER1>; 369 370 ports { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 mixer1_out: port@1 { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 reg = <1>; 378 379 mixer1_out_tcon0: endpoint@0 { 380 reg = <0>; 381 remote-endpoint = <&tcon0_in_mixer1>; 382 }; 383 384 mixer1_out_tcon1: endpoint@1 { 385 reg = <1>; 386 remote-endpoint = <&tcon1_in_mixer1>; 387 }; 388 }; 389 }; 390 }; 391 }; 392 393 syscon: syscon@1c00000 { 394 compatible = "allwinner,sun50i-a64-system-control"; 395 reg = <0x01c00000 0x1000>; 396 #address-cells = <1>; 397 #size-cells = <1>; 398 ranges; 399 400 sram_c: sram@18000 { 401 compatible = "mmio-sram"; 402 reg = <0x00018000 0x28000>; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 ranges = <0 0x00018000 0x28000>; 406 407 de2_sram: sram-section@0 { 408 compatible = "allwinner,sun50i-a64-sram-c"; 409 reg = <0x0000 0x28000>; 410 }; 411 }; 412 413 sram_c1: sram@1d00000 { 414 compatible = "mmio-sram"; 415 reg = <0x01d00000 0x40000>; 416 #address-cells = <1>; 417 #size-cells = <1>; 418 ranges = <0 0x01d00000 0x40000>; 419 420 ve_sram: sram-section@0 { 421 compatible = "allwinner,sun50i-a64-sram-c1", 422 "allwinner,sun4i-a10-sram-c1"; 423 reg = <0x000000 0x40000>; 424 }; 425 }; 426 }; 427 428 dma: dma-controller@1c02000 { 429 compatible = "allwinner,sun50i-a64-dma"; 430 reg = <0x01c02000 0x1000>; 431 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&ccu CLK_BUS_DMA>; 433 dma-channels = <8>; 434 dma-requests = <27>; 435 resets = <&ccu RST_BUS_DMA>; 436 #dma-cells = <1>; 437 }; 438 439 tcon0: lcd-controller@1c0c000 { 440 compatible = "allwinner,sun50i-a64-tcon-lcd", 441 "allwinner,sun8i-a83t-tcon-lcd"; 442 reg = <0x01c0c000 0x1000>; 443 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 445 clock-names = "ahb", "tcon-ch0"; 446 clock-output-names = "tcon-data-clock"; 447 #clock-cells = <0>; 448 assigned-clocks = <&ccu CLK_TCON0>; 449 assigned-clock-parents = <&ccu CLK_PLL_MIPI>; 450 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 451 reset-names = "lcd", "lvds"; 452 453 ports { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 457 tcon0_in: port@0 { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 reg = <0>; 461 462 tcon0_in_mixer0: endpoint@0 { 463 reg = <0>; 464 remote-endpoint = <&mixer0_out_tcon0>; 465 }; 466 467 tcon0_in_mixer1: endpoint@1 { 468 reg = <1>; 469 remote-endpoint = <&mixer1_out_tcon0>; 470 }; 471 }; 472 473 tcon0_out: port@1 { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 reg = <1>; 477 478 tcon0_out_dsi: endpoint@1 { 479 reg = <1>; 480 remote-endpoint = <&dsi_in_tcon0>; 481 allwinner,tcon-channel = <1>; 482 }; 483 }; 484 }; 485 }; 486 487 tcon1: lcd-controller@1c0d000 { 488 compatible = "allwinner,sun50i-a64-tcon-tv", 489 "allwinner,sun8i-a83t-tcon-tv"; 490 reg = <0x01c0d000 0x1000>; 491 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 493 clock-names = "ahb", "tcon-ch1"; 494 resets = <&ccu RST_BUS_TCON1>; 495 reset-names = "lcd"; 496 497 ports { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 tcon1_in: port@0 { 502 #address-cells = <1>; 503 #size-cells = <0>; 504 reg = <0>; 505 506 tcon1_in_mixer0: endpoint@0 { 507 reg = <0>; 508 remote-endpoint = <&mixer0_out_tcon1>; 509 }; 510 511 tcon1_in_mixer1: endpoint@1 { 512 reg = <1>; 513 remote-endpoint = <&mixer1_out_tcon1>; 514 }; 515 }; 516 517 tcon1_out: port@1 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <1>; 521 522 tcon1_out_hdmi: endpoint@1 { 523 reg = <1>; 524 remote-endpoint = <&hdmi_in_tcon1>; 525 }; 526 }; 527 }; 528 }; 529 530 video-codec@1c0e000 { 531 compatible = "allwinner,sun50i-a64-video-engine"; 532 reg = <0x01c0e000 0x1000>; 533 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 534 <&ccu CLK_DRAM_VE>; 535 clock-names = "ahb", "mod", "ram"; 536 resets = <&ccu RST_BUS_VE>; 537 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 538 allwinner,sram = <&ve_sram 1>; 539 }; 540 541 mmc0: mmc@1c0f000 { 542 compatible = "allwinner,sun50i-a64-mmc"; 543 reg = <0x01c0f000 0x1000>; 544 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 545 clock-names = "ahb", "mmc"; 546 resets = <&ccu RST_BUS_MMC0>; 547 reset-names = "ahb"; 548 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 549 max-frequency = <150000000>; 550 status = "disabled"; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 }; 554 555 mmc1: mmc@1c10000 { 556 compatible = "allwinner,sun50i-a64-mmc"; 557 reg = <0x01c10000 0x1000>; 558 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 559 clock-names = "ahb", "mmc"; 560 resets = <&ccu RST_BUS_MMC1>; 561 reset-names = "ahb"; 562 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 563 max-frequency = <150000000>; 564 status = "disabled"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 }; 568 569 mmc2: mmc@1c11000 { 570 compatible = "allwinner,sun50i-a64-emmc"; 571 reg = <0x01c11000 0x1000>; 572 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 573 clock-names = "ahb", "mmc"; 574 resets = <&ccu RST_BUS_MMC2>; 575 reset-names = "ahb"; 576 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 577 max-frequency = <150000000>; 578 status = "disabled"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 }; 582 583 sid: eeprom@1c14000 { 584 compatible = "allwinner,sun50i-a64-sid"; 585 reg = <0x1c14000 0x400>; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 589 ths_calibration: thermal-sensor-calibration@34 { 590 reg = <0x34 0x8>; 591 }; 592 }; 593 594 crypto: crypto@1c15000 { 595 compatible = "allwinner,sun50i-a64-crypto"; 596 reg = <0x01c15000 0x1000>; 597 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 599 clock-names = "bus", "mod"; 600 resets = <&ccu RST_BUS_CE>; 601 }; 602 603 msgbox: mailbox@1c17000 { 604 compatible = "allwinner,sun50i-a64-msgbox", 605 "allwinner,sun6i-a31-msgbox"; 606 reg = <0x01c17000 0x1000>; 607 clocks = <&ccu CLK_BUS_MSGBOX>; 608 resets = <&ccu RST_BUS_MSGBOX>; 609 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 610 #mbox-cells = <1>; 611 }; 612 613 usb_otg: usb@1c19000 { 614 compatible = "allwinner,sun8i-a33-musb"; 615 reg = <0x01c19000 0x0400>; 616 clocks = <&ccu CLK_BUS_OTG>; 617 resets = <&ccu RST_BUS_OTG>; 618 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 619 interrupt-names = "mc"; 620 phys = <&usbphy 0>; 621 phy-names = "usb"; 622 extcon = <&usbphy 0>; 623 dr_mode = "otg"; 624 status = "disabled"; 625 }; 626 627 usbphy: phy@1c19400 { 628 compatible = "allwinner,sun50i-a64-usb-phy"; 629 reg = <0x01c19400 0x14>, 630 <0x01c1a800 0x4>, 631 <0x01c1b800 0x4>; 632 reg-names = "phy_ctrl", 633 "pmu0", 634 "pmu1"; 635 clocks = <&ccu CLK_USB_PHY0>, 636 <&ccu CLK_USB_PHY1>; 637 clock-names = "usb0_phy", 638 "usb1_phy"; 639 resets = <&ccu RST_USB_PHY0>, 640 <&ccu RST_USB_PHY1>; 641 reset-names = "usb0_reset", 642 "usb1_reset"; 643 status = "disabled"; 644 #phy-cells = <1>; 645 }; 646 647 ehci0: usb@1c1a000 { 648 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 649 reg = <0x01c1a000 0x100>; 650 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&ccu CLK_BUS_OHCI0>, 652 <&ccu CLK_BUS_EHCI0>, 653 <&ccu CLK_USB_OHCI0>; 654 resets = <&ccu RST_BUS_OHCI0>, 655 <&ccu RST_BUS_EHCI0>; 656 phys = <&usbphy 0>; 657 phy-names = "usb"; 658 status = "disabled"; 659 }; 660 661 ohci0: usb@1c1a400 { 662 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 663 reg = <0x01c1a400 0x100>; 664 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&ccu CLK_BUS_OHCI0>, 666 <&ccu CLK_USB_OHCI0>; 667 resets = <&ccu RST_BUS_OHCI0>; 668 phys = <&usbphy 0>; 669 phy-names = "usb"; 670 status = "disabled"; 671 }; 672 673 ehci1: usb@1c1b000 { 674 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 675 reg = <0x01c1b000 0x100>; 676 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&ccu CLK_BUS_OHCI1>, 678 <&ccu CLK_BUS_EHCI1>, 679 <&ccu CLK_USB_OHCI1>; 680 resets = <&ccu RST_BUS_OHCI1>, 681 <&ccu RST_BUS_EHCI1>; 682 phys = <&usbphy 1>; 683 phy-names = "usb"; 684 status = "disabled"; 685 }; 686 687 ohci1: usb@1c1b400 { 688 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 689 reg = <0x01c1b400 0x100>; 690 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&ccu CLK_BUS_OHCI1>, 692 <&ccu CLK_USB_OHCI1>; 693 resets = <&ccu RST_BUS_OHCI1>; 694 phys = <&usbphy 1>; 695 phy-names = "usb"; 696 status = "disabled"; 697 }; 698 699 ccu: clock@1c20000 { 700 compatible = "allwinner,sun50i-a64-ccu"; 701 reg = <0x01c20000 0x400>; 702 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 703 clock-names = "hosc", "losc"; 704 #clock-cells = <1>; 705 #reset-cells = <1>; 706 }; 707 708 pio: pinctrl@1c20800 { 709 compatible = "allwinner,sun50i-a64-pinctrl"; 710 reg = <0x01c20800 0x400>; 711 interrupt-parent = <&r_intc>; 712 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 716 <&rtc CLK_OSC32K>; 717 clock-names = "apb", "hosc", "losc"; 718 gpio-controller; 719 #gpio-cells = <3>; 720 interrupt-controller; 721 #interrupt-cells = <3>; 722 723 /omit-if-no-ref/ 724 aif2_pins: aif2-pins { 725 pins = "PB4", "PB5", "PB6", "PB7"; 726 function = "aif2"; 727 }; 728 729 /omit-if-no-ref/ 730 aif3_pins: aif3-pins { 731 pins = "PG10", "PG11", "PG12", "PG13"; 732 function = "aif3"; 733 }; 734 735 csi_pins: csi-pins { 736 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 737 "PE7", "PE8", "PE9", "PE10", "PE11"; 738 function = "csi"; 739 }; 740 741 /omit-if-no-ref/ 742 csi_mclk_pin: csi-mclk-pin { 743 pins = "PE1"; 744 function = "csi"; 745 }; 746 747 i2c0_pins: i2c0-pins { 748 pins = "PH0", "PH1"; 749 function = "i2c0"; 750 }; 751 752 i2c1_pins: i2c1-pins { 753 pins = "PH2", "PH3"; 754 function = "i2c1"; 755 }; 756 757 i2c2_pins: i2c2-pins { 758 pins = "PE14", "PE15"; 759 function = "i2c2"; 760 }; 761 762 /omit-if-no-ref/ 763 lcd_rgb666_pins: lcd-rgb666-pins { 764 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 765 "PD5", "PD6", "PD7", "PD8", "PD9", 766 "PD10", "PD11", "PD12", "PD13", 767 "PD14", "PD15", "PD16", "PD17", 768 "PD18", "PD19", "PD20", "PD21"; 769 function = "lcd0"; 770 }; 771 772 mmc0_pins: mmc0-pins { 773 pins = "PF0", "PF1", "PF2", "PF3", 774 "PF4", "PF5"; 775 function = "mmc0"; 776 drive-strength = <30>; 777 bias-pull-up; 778 }; 779 780 mmc1_pins: mmc1-pins { 781 pins = "PG0", "PG1", "PG2", "PG3", 782 "PG4", "PG5"; 783 function = "mmc1"; 784 drive-strength = <30>; 785 bias-pull-up; 786 }; 787 788 mmc2_pins: mmc2-pins { 789 pins = "PC5", "PC6", "PC8", "PC9", 790 "PC10","PC11", "PC12", "PC13", 791 "PC14", "PC15", "PC16"; 792 function = "mmc2"; 793 drive-strength = <30>; 794 bias-pull-up; 795 }; 796 797 mmc2_ds_pin: mmc2-ds-pin { 798 pins = "PC1"; 799 function = "mmc2"; 800 drive-strength = <30>; 801 bias-pull-up; 802 }; 803 804 pwm_pin: pwm-pin { 805 pins = "PD22"; 806 function = "pwm"; 807 }; 808 809 rmii_pins: rmii-pins { 810 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 811 "PD18", "PD19", "PD20", "PD22", "PD23"; 812 function = "emac"; 813 drive-strength = <40>; 814 }; 815 816 rgmii_pins: rgmii-pins { 817 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 818 "PD13", "PD15", "PD16", "PD17", "PD18", 819 "PD19", "PD20", "PD21", "PD22", "PD23"; 820 function = "emac"; 821 drive-strength = <40>; 822 }; 823 824 spdif_tx_pin: spdif-tx-pin { 825 pins = "PH8"; 826 function = "spdif"; 827 }; 828 829 spi0_pins: spi0-pins { 830 pins = "PC0", "PC1", "PC2", "PC3"; 831 function = "spi0"; 832 }; 833 834 spi1_pins: spi1-pins { 835 pins = "PD0", "PD1", "PD2", "PD3"; 836 function = "spi1"; 837 }; 838 839 uart0_pb_pins: uart0-pb-pins { 840 pins = "PB8", "PB9"; 841 function = "uart0"; 842 }; 843 844 uart1_pins: uart1-pins { 845 pins = "PG6", "PG7"; 846 function = "uart1"; 847 }; 848 849 uart1_rts_cts_pins: uart1-rts-cts-pins { 850 pins = "PG8", "PG9"; 851 function = "uart1"; 852 }; 853 854 uart2_pins: uart2-pins { 855 pins = "PB0", "PB1"; 856 function = "uart2"; 857 }; 858 859 uart3_pins: uart3-pins { 860 pins = "PD0", "PD1"; 861 function = "uart3"; 862 }; 863 864 uart4_pins: uart4-pins { 865 pins = "PD2", "PD3"; 866 function = "uart4"; 867 }; 868 869 uart4_rts_cts_pins: uart4-rts-cts-pins { 870 pins = "PD4", "PD5"; 871 function = "uart4"; 872 }; 873 }; 874 875 timer@1c20c00 { 876 compatible = "allwinner,sun50i-a64-timer", 877 "allwinner,sun8i-a23-timer"; 878 reg = <0x01c20c00 0xa0>; 879 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&osc24M>; 882 }; 883 884 wdt0: watchdog@1c20ca0 { 885 compatible = "allwinner,sun50i-a64-wdt", 886 "allwinner,sun6i-a31-wdt"; 887 reg = <0x01c20ca0 0x20>; 888 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&osc24M>; 890 }; 891 892 spdif: spdif@1c21000 { 893 #sound-dai-cells = <0>; 894 compatible = "allwinner,sun50i-a64-spdif", 895 "allwinner,sun8i-h3-spdif"; 896 reg = <0x01c21000 0x400>; 897 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 899 resets = <&ccu RST_BUS_SPDIF>; 900 clock-names = "apb", "spdif"; 901 dmas = <&dma 2>; 902 dma-names = "tx"; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&spdif_tx_pin>; 905 status = "disabled"; 906 }; 907 908 lradc: lradc@1c21800 { 909 compatible = "allwinner,sun50i-a64-lradc", 910 "allwinner,sun8i-a83t-r-lradc"; 911 reg = <0x01c21800 0x400>; 912 interrupt-parent = <&r_intc>; 913 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 914 status = "disabled"; 915 }; 916 917 i2s0: i2s@1c22000 { 918 #sound-dai-cells = <0>; 919 compatible = "allwinner,sun50i-a64-i2s", 920 "allwinner,sun8i-h3-i2s"; 921 reg = <0x01c22000 0x400>; 922 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 924 clock-names = "apb", "mod"; 925 resets = <&ccu RST_BUS_I2S0>; 926 dma-names = "rx", "tx"; 927 dmas = <&dma 3>, <&dma 3>; 928 status = "disabled"; 929 }; 930 931 i2s1: i2s@1c22400 { 932 #sound-dai-cells = <0>; 933 compatible = "allwinner,sun50i-a64-i2s", 934 "allwinner,sun8i-h3-i2s"; 935 reg = <0x01c22400 0x400>; 936 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 938 clock-names = "apb", "mod"; 939 resets = <&ccu RST_BUS_I2S1>; 940 dma-names = "rx", "tx"; 941 dmas = <&dma 4>, <&dma 4>; 942 status = "disabled"; 943 }; 944 945 i2s2: i2s@1c22800 { 946 #sound-dai-cells = <0>; 947 compatible = "allwinner,sun50i-a64-i2s", 948 "allwinner,sun8i-h3-i2s"; 949 reg = <0x01c22800 0x400>; 950 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 952 clock-names = "apb", "mod"; 953 resets = <&ccu RST_BUS_I2S2>; 954 dma-names = "rx", "tx"; 955 dmas = <&dma 27>, <&dma 27>; 956 status = "disabled"; 957 }; 958 959 dai: dai@1c22c00 { 960 #sound-dai-cells = <0>; 961 compatible = "allwinner,sun50i-a64-codec-i2s"; 962 reg = <0x01c22c00 0x200>; 963 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 965 clock-names = "apb", "mod"; 966 resets = <&ccu RST_BUS_CODEC>; 967 dmas = <&dma 15>, <&dma 15>; 968 dma-names = "rx", "tx"; 969 status = "disabled"; 970 }; 971 972 codec: codec@1c22e00 { 973 #sound-dai-cells = <1>; 974 compatible = "allwinner,sun50i-a64-codec", 975 "allwinner,sun8i-a33-codec"; 976 reg = <0x01c22e00 0x600>; 977 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 979 clock-names = "bus", "mod"; 980 status = "disabled"; 981 }; 982 983 ths: thermal-sensor@1c25000 { 984 compatible = "allwinner,sun50i-a64-ths"; 985 reg = <0x01c25000 0x100>; 986 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 987 clock-names = "bus", "mod"; 988 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 989 resets = <&ccu RST_BUS_THS>; 990 nvmem-cells = <&ths_calibration>; 991 nvmem-cell-names = "calibration"; 992 #thermal-sensor-cells = <1>; 993 }; 994 995 uart0: serial@1c28000 { 996 compatible = "snps,dw-apb-uart"; 997 reg = <0x01c28000 0x400>; 998 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 999 reg-shift = <2>; 1000 reg-io-width = <4>; 1001 clocks = <&ccu CLK_BUS_UART0>; 1002 resets = <&ccu RST_BUS_UART0>; 1003 status = "disabled"; 1004 }; 1005 1006 uart1: serial@1c28400 { 1007 compatible = "snps,dw-apb-uart"; 1008 reg = <0x01c28400 0x400>; 1009 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1010 reg-shift = <2>; 1011 reg-io-width = <4>; 1012 clocks = <&ccu CLK_BUS_UART1>; 1013 resets = <&ccu RST_BUS_UART1>; 1014 status = "disabled"; 1015 }; 1016 1017 uart2: serial@1c28800 { 1018 compatible = "snps,dw-apb-uart"; 1019 reg = <0x01c28800 0x400>; 1020 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1021 reg-shift = <2>; 1022 reg-io-width = <4>; 1023 clocks = <&ccu CLK_BUS_UART2>; 1024 resets = <&ccu RST_BUS_UART2>; 1025 status = "disabled"; 1026 }; 1027 1028 uart3: serial@1c28c00 { 1029 compatible = "snps,dw-apb-uart"; 1030 reg = <0x01c28c00 0x400>; 1031 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1032 reg-shift = <2>; 1033 reg-io-width = <4>; 1034 clocks = <&ccu CLK_BUS_UART3>; 1035 resets = <&ccu RST_BUS_UART3>; 1036 status = "disabled"; 1037 }; 1038 1039 uart4: serial@1c29000 { 1040 compatible = "snps,dw-apb-uart"; 1041 reg = <0x01c29000 0x400>; 1042 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1043 reg-shift = <2>; 1044 reg-io-width = <4>; 1045 clocks = <&ccu CLK_BUS_UART4>; 1046 resets = <&ccu RST_BUS_UART4>; 1047 status = "disabled"; 1048 }; 1049 1050 i2c0: i2c@1c2ac00 { 1051 compatible = "allwinner,sun6i-a31-i2c"; 1052 reg = <0x01c2ac00 0x400>; 1053 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&ccu CLK_BUS_I2C0>; 1055 resets = <&ccu RST_BUS_I2C0>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&i2c0_pins>; 1058 status = "disabled"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 }; 1062 1063 i2c1: i2c@1c2b000 { 1064 compatible = "allwinner,sun6i-a31-i2c"; 1065 reg = <0x01c2b000 0x400>; 1066 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&ccu CLK_BUS_I2C1>; 1068 resets = <&ccu RST_BUS_I2C1>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&i2c1_pins>; 1071 status = "disabled"; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 }; 1075 1076 i2c2: i2c@1c2b400 { 1077 compatible = "allwinner,sun6i-a31-i2c"; 1078 reg = <0x01c2b400 0x400>; 1079 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&ccu CLK_BUS_I2C2>; 1081 resets = <&ccu RST_BUS_I2C2>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&i2c2_pins>; 1084 status = "disabled"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 }; 1088 1089 spi0: spi@1c68000 { 1090 compatible = "allwinner,sun8i-h3-spi"; 1091 reg = <0x01c68000 0x1000>; 1092 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1094 clock-names = "ahb", "mod"; 1095 dmas = <&dma 23>, <&dma 23>; 1096 dma-names = "rx", "tx"; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&spi0_pins>; 1099 resets = <&ccu RST_BUS_SPI0>; 1100 status = "disabled"; 1101 num-cs = <1>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 }; 1105 1106 spi1: spi@1c69000 { 1107 compatible = "allwinner,sun8i-h3-spi"; 1108 reg = <0x01c69000 0x1000>; 1109 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1111 clock-names = "ahb", "mod"; 1112 dmas = <&dma 24>, <&dma 24>; 1113 dma-names = "rx", "tx"; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&spi1_pins>; 1116 resets = <&ccu RST_BUS_SPI1>; 1117 status = "disabled"; 1118 num-cs = <1>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 }; 1122 1123 emac: ethernet@1c30000 { 1124 compatible = "allwinner,sun50i-a64-emac"; 1125 syscon = <&syscon>; 1126 reg = <0x01c30000 0x10000>; 1127 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1128 interrupt-names = "macirq"; 1129 resets = <&ccu RST_BUS_EMAC>; 1130 reset-names = "stmmaceth"; 1131 clocks = <&ccu CLK_BUS_EMAC>; 1132 clock-names = "stmmaceth"; 1133 status = "disabled"; 1134 1135 mdio: mdio { 1136 compatible = "snps,dwmac-mdio"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 }; 1140 }; 1141 1142 mali: gpu@1c40000 { 1143 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 1144 reg = <0x01c40000 0x10000>; 1145 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1152 interrupt-names = "gp", 1153 "gpmmu", 1154 "pp0", 1155 "ppmmu0", 1156 "pp1", 1157 "ppmmu1", 1158 "pmu"; 1159 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 1160 clock-names = "bus", "core"; 1161 resets = <&ccu RST_BUS_GPU>; 1162 operating-points-v2 = <&gpu_opp_table>; 1163 }; 1164 1165 gic: interrupt-controller@1c81000 { 1166 compatible = "arm,gic-400"; 1167 reg = <0x01c81000 0x1000>, 1168 <0x01c82000 0x2000>, 1169 <0x01c84000 0x2000>, 1170 <0x01c86000 0x2000>; 1171 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1172 interrupt-controller; 1173 #interrupt-cells = <3>; 1174 }; 1175 1176 pwm: pwm@1c21400 { 1177 compatible = "allwinner,sun50i-a64-pwm", 1178 "allwinner,sun5i-a13-pwm"; 1179 reg = <0x01c21400 0x400>; 1180 clocks = <&osc24M>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&pwm_pin>; 1183 #pwm-cells = <3>; 1184 status = "disabled"; 1185 }; 1186 1187 mbus: dram-controller@1c62000 { 1188 compatible = "allwinner,sun50i-a64-mbus"; 1189 reg = <0x01c62000 0x1000>, 1190 <0x01c63000 0x1000>; 1191 reg-names = "mbus", "dram"; 1192 clocks = <&ccu CLK_MBUS>, 1193 <&ccu CLK_DRAM>, 1194 <&ccu CLK_BUS_DRAM>; 1195 clock-names = "mbus", "dram", "bus"; 1196 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <1>; 1199 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1200 #interconnect-cells = <1>; 1201 }; 1202 1203 csi: csi@1cb0000 { 1204 compatible = "allwinner,sun50i-a64-csi"; 1205 reg = <0x01cb0000 0x1000>; 1206 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&ccu CLK_BUS_CSI>, 1208 <&ccu CLK_CSI_SCLK>, 1209 <&ccu CLK_DRAM_CSI>; 1210 clock-names = "bus", "mod", "ram"; 1211 resets = <&ccu RST_BUS_CSI>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&csi_pins>; 1214 status = "disabled"; 1215 }; 1216 1217 dsi: dsi@1ca0000 { 1218 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1219 reg = <0x01ca0000 0x1000>; 1220 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1222 resets = <&ccu RST_BUS_MIPI_DSI>; 1223 phys = <&dphy>; 1224 phy-names = "dphy"; 1225 status = "disabled"; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 1229 port { 1230 dsi_in_tcon0: endpoint { 1231 remote-endpoint = <&tcon0_out_dsi>; 1232 }; 1233 }; 1234 }; 1235 1236 dphy: d-phy@1ca1000 { 1237 compatible = "allwinner,sun50i-a64-mipi-dphy", 1238 "allwinner,sun6i-a31-mipi-dphy"; 1239 reg = <0x01ca1000 0x1000>; 1240 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1242 <&ccu CLK_DSI_DPHY>; 1243 clock-names = "bus", "mod"; 1244 resets = <&ccu RST_BUS_MIPI_DSI>; 1245 status = "disabled"; 1246 #phy-cells = <0>; 1247 }; 1248 1249 deinterlace: deinterlace@1e00000 { 1250 compatible = "allwinner,sun50i-a64-deinterlace", 1251 "allwinner,sun8i-h3-deinterlace"; 1252 reg = <0x01e00000 0x20000>; 1253 clocks = <&ccu CLK_BUS_DEINTERLACE>, 1254 <&ccu CLK_DEINTERLACE>, 1255 <&ccu CLK_DRAM_DEINTERLACE>; 1256 clock-names = "bus", "mod", "ram"; 1257 resets = <&ccu RST_BUS_DEINTERLACE>; 1258 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1259 interconnects = <&mbus 9>; 1260 interconnect-names = "dma-mem"; 1261 }; 1262 1263 hdmi: hdmi@1ee0000 { 1264 compatible = "allwinner,sun50i-a64-dw-hdmi", 1265 "allwinner,sun8i-a83t-dw-hdmi"; 1266 reg = <0x01ee0000 0x10000>; 1267 reg-io-width = <1>; 1268 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1270 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 1271 clock-names = "iahb", "isfr", "tmds", "cec"; 1272 resets = <&ccu RST_BUS_HDMI1>; 1273 reset-names = "ctrl"; 1274 phys = <&hdmi_phy>; 1275 phy-names = "phy"; 1276 status = "disabled"; 1277 1278 ports { 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 1282 hdmi_in: port@0 { 1283 reg = <0>; 1284 1285 hdmi_in_tcon1: endpoint { 1286 remote-endpoint = <&tcon1_out_hdmi>; 1287 }; 1288 }; 1289 1290 hdmi_out: port@1 { 1291 reg = <1>; 1292 }; 1293 }; 1294 }; 1295 1296 hdmi_phy: hdmi-phy@1ef0000 { 1297 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1298 reg = <0x01ef0000 0x10000>; 1299 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1300 <&ccu CLK_PLL_VIDEO0>; 1301 clock-names = "bus", "mod", "pll-0"; 1302 resets = <&ccu RST_BUS_HDMI0>; 1303 reset-names = "phy"; 1304 #phy-cells = <0>; 1305 }; 1306 1307 rtc: rtc@1f00000 { 1308 compatible = "allwinner,sun50i-a64-rtc", 1309 "allwinner,sun8i-h3-rtc"; 1310 reg = <0x01f00000 0x400>; 1311 interrupt-parent = <&r_intc>; 1312 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1314 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1315 clocks = <&osc32k>; 1316 #clock-cells = <1>; 1317 }; 1318 1319 r_intc: interrupt-controller@1f00c00 { 1320 compatible = "allwinner,sun50i-a64-r-intc", 1321 "allwinner,sun6i-a31-r-intc"; 1322 interrupt-controller; 1323 #interrupt-cells = <3>; 1324 reg = <0x01f00c00 0x400>; 1325 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1326 }; 1327 1328 r_ccu: clock@1f01400 { 1329 compatible = "allwinner,sun50i-a64-r-ccu"; 1330 reg = <0x01f01400 0x100>; 1331 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 1332 <&ccu CLK_PLL_PERIPH0>; 1333 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1334 #clock-cells = <1>; 1335 #reset-cells = <1>; 1336 }; 1337 1338 codec_analog: codec-analog@1f015c0 { 1339 compatible = "allwinner,sun50i-a64-codec-analog"; 1340 reg = <0x01f015c0 0x4>; 1341 status = "disabled"; 1342 }; 1343 1344 r_i2c: i2c@1f02400 { 1345 compatible = "allwinner,sun50i-a64-i2c", 1346 "allwinner,sun6i-a31-i2c"; 1347 reg = <0x01f02400 0x400>; 1348 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&r_ccu CLK_APB0_I2C>; 1350 resets = <&r_ccu RST_APB0_I2C>; 1351 status = "disabled"; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 }; 1355 1356 r_ir: ir@1f02000 { 1357 compatible = "allwinner,sun50i-a64-ir", 1358 "allwinner,sun6i-a31-ir"; 1359 reg = <0x01f02000 0x400>; 1360 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1361 clock-names = "apb", "ir"; 1362 resets = <&r_ccu RST_APB0_IR>; 1363 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&r_ir_rx_pin>; 1366 status = "disabled"; 1367 }; 1368 1369 r_pwm: pwm@1f03800 { 1370 compatible = "allwinner,sun50i-a64-pwm", 1371 "allwinner,sun5i-a13-pwm"; 1372 reg = <0x01f03800 0x400>; 1373 clocks = <&osc24M>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&r_pwm_pin>; 1376 #pwm-cells = <3>; 1377 status = "disabled"; 1378 }; 1379 1380 r_pio: pinctrl@1f02c00 { 1381 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1382 reg = <0x01f02c00 0x400>; 1383 interrupt-parent = <&r_intc>; 1384 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1385 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1386 clock-names = "apb", "hosc", "losc"; 1387 gpio-controller; 1388 #gpio-cells = <3>; 1389 interrupt-controller; 1390 #interrupt-cells = <3>; 1391 1392 r_i2c_pl89_pins: r-i2c-pl89-pins { 1393 pins = "PL8", "PL9"; 1394 function = "s_i2c"; 1395 }; 1396 1397 r_ir_rx_pin: r-ir-rx-pin { 1398 pins = "PL11"; 1399 function = "s_cir_rx"; 1400 }; 1401 1402 r_pwm_pin: r-pwm-pin { 1403 pins = "PL10"; 1404 function = "s_pwm"; 1405 }; 1406 1407 r_rsb_pins: r-rsb-pins { 1408 pins = "PL0", "PL1"; 1409 function = "s_rsb"; 1410 }; 1411 }; 1412 1413 r_rsb: rsb@1f03400 { 1414 compatible = "allwinner,sun8i-a23-rsb"; 1415 reg = <0x01f03400 0x400>; 1416 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1417 clocks = <&r_ccu 6>; 1418 clock-frequency = <3000000>; 1419 resets = <&r_ccu 2>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&r_rsb_pins>; 1422 status = "disabled"; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 }; 1426 }; 1427}; 1428