1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Yangtao Li <[email protected]> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-a100-ccu.h> 8#include <dt-bindings/clock/sun50i-a100-r-ccu.h> 9#include <dt-bindings/reset/sun50i-a100-ccu.h> 10#include <dt-bindings/reset/sun50i-a100-r-ccu.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a53"; 23 device_type = "cpu"; 24 reg = <0x0>; 25 enable-method = "psci"; 26 }; 27 28 cpu1: cpu@1 { 29 compatible = "arm,cortex-a53"; 30 device_type = "cpu"; 31 reg = <0x1>; 32 enable-method = "psci"; 33 }; 34 35 cpu2: cpu@2 { 36 compatible = "arm,cortex-a53"; 37 device_type = "cpu"; 38 reg = <0x2>; 39 enable-method = "psci"; 40 }; 41 42 cpu3: cpu@3 { 43 compatible = "arm,cortex-a53"; 44 device_type = "cpu"; 45 reg = <0x3>; 46 enable-method = "psci"; 47 }; 48 }; 49 50 pmu { 51 compatible = "arm,cortex-a53-pmu"; 52 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 56 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 57 }; 58 59 psci { 60 compatible = "arm,psci-1.0"; 61 method = "smc"; 62 }; 63 64 dcxo24M: dcxo24M-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <24000000>; 67 clock-output-names = "dcxo24M"; 68 #clock-cells = <0>; 69 }; 70 71 iosc: internal-osc-clk { 72 compatible = "fixed-clock"; 73 clock-frequency = <16000000>; 74 clock-accuracy = <300000000>; 75 clock-output-names = "iosc"; 76 #clock-cells = <0>; 77 }; 78 79 osc32k: osc32k-clk { 80 compatible = "fixed-clock"; 81 clock-frequency = <32768>; 82 clock-output-names = "osc32k"; 83 #clock-cells = <0>; 84 }; 85 86 timer { 87 compatible = "arm,armv8-timer"; 88 interrupts = <GIC_PPI 13 89 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 90 <GIC_PPI 14 91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 92 <GIC_PPI 11 93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 10 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0 0 0x3fffffff>; 103 104 syscon: syscon@3000000 { 105 compatible = "allwinner,sun50i-a100-system-control", 106 "allwinner,sun50i-a64-system-control"; 107 reg = <0x03000000 0x1000>; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 sram_a1: sram@20000 { 113 compatible = "mmio-sram"; 114 reg = <0x00020000 0x4000>; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges = <0 0x00020000 0x4000>; 118 }; 119 120 sram_c: sram@24000 { 121 compatible = "mmio-sram"; 122 reg = <0x024000 0x21000>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0x024000 0x21000>; 126 }; 127 128 sram_a2: sram@100000 { 129 compatible = "mmio-sram"; 130 reg = <0x0100000 0x14000>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 ranges = <0 0x0100000 0x14000>; 134 }; 135 }; 136 137 ccu: clock@3001000 { 138 compatible = "allwinner,sun50i-a100-ccu"; 139 reg = <0x03001000 0x1000>; 140 clocks = <&dcxo24M>, <&osc32k>, <&iosc>; 141 clock-names = "hosc", "losc", "iosc"; 142 #clock-cells = <1>; 143 #reset-cells = <1>; 144 }; 145 146 dma: dma-controller@3002000 { 147 compatible = "allwinner,sun50i-a100-dma"; 148 reg = <0x03002000 0x1000>; 149 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 151 clock-names = "bus", "mbus"; 152 resets = <&ccu RST_BUS_DMA>; 153 dma-channels = <8>; 154 dma-requests = <52>; 155 #dma-cells = <1>; 156 }; 157 158 gic: interrupt-controller@3021000 { 159 compatible = "arm,gic-400"; 160 reg = <0x03021000 0x1000>, <0x03022000 0x2000>, 161 <0x03024000 0x2000>, <0x03026000 0x2000>; 162 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 163 IRQ_TYPE_LEVEL_HIGH)>; 164 interrupt-controller; 165 #interrupt-cells = <3>; 166 }; 167 168 efuse@3006000 { 169 compatible = "allwinner,sun50i-a100-sid", 170 "allwinner,sun50i-a64-sid"; 171 reg = <0x03006000 0x1000>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 175 ths_calibration: calib@14 { 176 reg = <0x14 8>; 177 }; 178 }; 179 180 watchdog@30090a0 { 181 compatible = "allwinner,sun50i-a100-wdt", 182 "allwinner,sun6i-a31-wdt"; 183 reg = <0x030090a0 0x20>; 184 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&dcxo24M>; 186 }; 187 188 pio: pinctrl@300b000 { 189 compatible = "allwinner,sun50i-a100-pinctrl"; 190 reg = <0x0300b000 0x400>; 191 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; 199 clock-names = "apb", "hosc", "losc"; 200 gpio-controller; 201 #gpio-cells = <3>; 202 interrupt-controller; 203 #interrupt-cells = <3>; 204 205 mmc0_pins: mmc0-pins { 206 pins = "PF0", "PF1", "PF2", "PF3", 207 "PF4", "PF5"; 208 function = "mmc0"; 209 drive-strength = <30>; 210 bias-pull-up; 211 }; 212 213 /omit-if-no-ref/ 214 mmc1_pins: mmc1-pins { 215 pins = "PG0", "PG1", "PG2", "PG3", 216 "PG4", "PG5"; 217 function = "mmc1"; 218 drive-strength = <30>; 219 bias-pull-up; 220 }; 221 222 mmc2_pins: mmc2-pins { 223 pins = "PC0", "PC1", "PC5", "PC6", 224 "PC8", "PC9", "PC10", "PC11", 225 "PC13", "PC14", "PC15", "PC16"; 226 function = "mmc2"; 227 drive-strength = <30>; 228 bias-pull-up; 229 }; 230 231 uart0_pb_pins: uart0-pb-pins { 232 pins = "PB9", "PB10"; 233 function = "uart0"; 234 }; 235 }; 236 237 mmc0: mmc@4020000 { 238 compatible = "allwinner,sun50i-a100-mmc"; 239 reg = <0x04020000 0x1000>; 240 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 241 clock-names = "ahb", "mmc"; 242 resets = <&ccu RST_BUS_MMC0>; 243 reset-names = "ahb"; 244 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&mmc0_pins>; 247 status = "disabled"; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 }; 251 252 mmc1: mmc@4021000 { 253 compatible = "allwinner,sun50i-a100-mmc"; 254 reg = <0x04021000 0x1000>; 255 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 256 clock-names = "ahb", "mmc"; 257 resets = <&ccu RST_BUS_MMC1>; 258 reset-names = "ahb"; 259 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&mmc1_pins>; 262 status = "disabled"; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 }; 266 267 mmc2: mmc@4022000 { 268 compatible = "allwinner,sun50i-a100-emmc"; 269 reg = <0x04022000 0x1000>; 270 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 271 clock-names = "ahb", "mmc"; 272 resets = <&ccu RST_BUS_MMC2>; 273 reset-names = "ahb"; 274 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&mmc2_pins>; 277 status = "disabled"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 }; 281 282 uart0: serial@5000000 { 283 compatible = "snps,dw-apb-uart"; 284 reg = <0x05000000 0x400>; 285 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 clocks = <&ccu CLK_BUS_UART0>; 289 resets = <&ccu RST_BUS_UART0>; 290 status = "disabled"; 291 }; 292 293 uart1: serial@5000400 { 294 compatible = "snps,dw-apb-uart"; 295 reg = <0x05000400 0x400>; 296 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 297 reg-shift = <2>; 298 reg-io-width = <4>; 299 clocks = <&ccu CLK_BUS_UART1>; 300 resets = <&ccu RST_BUS_UART1>; 301 status = "disabled"; 302 }; 303 304 uart2: serial@5000800 { 305 compatible = "snps,dw-apb-uart"; 306 reg = <0x05000800 0x400>; 307 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 308 reg-shift = <2>; 309 reg-io-width = <4>; 310 clocks = <&ccu CLK_BUS_UART2>; 311 resets = <&ccu RST_BUS_UART2>; 312 status = "disabled"; 313 }; 314 315 uart3: serial@5000c00 { 316 compatible = "snps,dw-apb-uart"; 317 reg = <0x05000c00 0x400>; 318 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 319 reg-shift = <2>; 320 reg-io-width = <4>; 321 clocks = <&ccu CLK_BUS_UART3>; 322 resets = <&ccu RST_BUS_UART3>; 323 status = "disabled"; 324 }; 325 326 uart4: serial@5001000 { 327 compatible = "snps,dw-apb-uart"; 328 reg = <0x05001000 0x400>; 329 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 330 reg-shift = <2>; 331 reg-io-width = <4>; 332 clocks = <&ccu CLK_BUS_UART4>; 333 resets = <&ccu RST_BUS_UART4>; 334 status = "disabled"; 335 }; 336 337 i2c0: i2c@5002000 { 338 compatible = "allwinner,sun50i-a100-i2c", 339 "allwinner,sun8i-v536-i2c", 340 "allwinner,sun6i-a31-i2c"; 341 reg = <0x05002000 0x400>; 342 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&ccu CLK_BUS_I2C0>; 344 resets = <&ccu RST_BUS_I2C0>; 345 dmas = <&dma 43>, <&dma 43>; 346 dma-names = "rx", "tx"; 347 status = "disabled"; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 }; 351 352 i2c1: i2c@5002400 { 353 compatible = "allwinner,sun50i-a100-i2c", 354 "allwinner,sun8i-v536-i2c", 355 "allwinner,sun6i-a31-i2c"; 356 reg = <0x05002400 0x400>; 357 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&ccu CLK_BUS_I2C1>; 359 resets = <&ccu RST_BUS_I2C1>; 360 dmas = <&dma 44>, <&dma 44>; 361 dma-names = "rx", "tx"; 362 status = "disabled"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 }; 366 367 i2c2: i2c@5002800 { 368 compatible = "allwinner,sun50i-a100-i2c", 369 "allwinner,sun8i-v536-i2c", 370 "allwinner,sun6i-a31-i2c"; 371 reg = <0x05002800 0x400>; 372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&ccu CLK_BUS_I2C2>; 374 resets = <&ccu RST_BUS_I2C2>; 375 dmas = <&dma 45>, <&dma 45>; 376 dma-names = "rx", "tx"; 377 status = "disabled"; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 }; 381 382 i2c3: i2c@5002c00 { 383 compatible = "allwinner,sun50i-a100-i2c", 384 "allwinner,sun8i-v536-i2c", 385 "allwinner,sun6i-a31-i2c"; 386 reg = <0x05002c00 0x400>; 387 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&ccu CLK_BUS_I2C3>; 389 resets = <&ccu RST_BUS_I2C3>; 390 dmas = <&dma 46>, <&dma 46>; 391 dma-names = "rx", "tx"; 392 status = "disabled"; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 }; 396 397 ths: thermal-sensor@5070400 { 398 compatible = "allwinner,sun50i-a100-ths"; 399 reg = <0x05070400 0x100>; 400 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&ccu CLK_BUS_THS>; 402 clock-names = "bus"; 403 resets = <&ccu RST_BUS_THS>; 404 nvmem-cells = <&ths_calibration>; 405 nvmem-cell-names = "calibration"; 406 #thermal-sensor-cells = <1>; 407 }; 408 409 usb_otg: usb@5100000 { 410 compatible = "allwinner,sun50i-a100-musb", 411 "allwinner,sun8i-a33-musb"; 412 reg = <0x05100000 0x0400>; 413 clocks = <&ccu CLK_BUS_OTG>; 414 resets = <&ccu RST_BUS_OTG>; 415 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "mc"; 417 phys = <&usbphy 0>; 418 phy-names = "usb"; 419 extcon = <&usbphy 0>; 420 status = "disabled"; 421 }; 422 423 usbphy: phy@5100400 { 424 compatible = "allwinner,sun50i-a100-usb-phy", 425 "allwinner,sun20i-d1-usb-phy"; 426 reg = <0x05100400 0x100>, 427 <0x05101800 0x100>, 428 <0x05200800 0x100>; 429 reg-names = "phy_ctrl", 430 "pmu0", 431 "pmu1"; 432 clocks = <&ccu CLK_USB_PHY0>, 433 <&ccu CLK_USB_PHY1>; 434 clock-names = "usb0_phy", 435 "usb1_phy"; 436 resets = <&ccu RST_USB_PHY0>, 437 <&ccu RST_USB_PHY1>; 438 reset-names = "usb0_reset", 439 "usb1_reset"; 440 status = "disabled"; 441 #phy-cells = <1>; 442 }; 443 444 ehci0: usb@5101000 { 445 compatible = "allwinner,sun50i-a100-ehci", 446 "generic-ehci"; 447 reg = <0x05101000 0x100>; 448 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&ccu CLK_BUS_OHCI0>, 450 <&ccu CLK_BUS_EHCI0>, 451 <&ccu CLK_USB_OHCI0>; 452 resets = <&ccu RST_BUS_OHCI0>, 453 <&ccu RST_BUS_EHCI0>; 454 phys = <&usbphy 0>; 455 phy-names = "usb"; 456 status = "disabled"; 457 }; 458 459 ohci0: usb@5101400 { 460 compatible = "allwinner,sun50i-a100-ohci", 461 "generic-ohci"; 462 reg = <0x05101400 0x100>; 463 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&ccu CLK_BUS_OHCI0>, 465 <&ccu CLK_USB_OHCI0>; 466 resets = <&ccu RST_BUS_OHCI0>; 467 phys = <&usbphy 0>; 468 phy-names = "usb"; 469 status = "disabled"; 470 }; 471 472 ehci1: usb@5200000 { 473 compatible = "allwinner,sun50i-a100-ehci", 474 "generic-ehci"; 475 reg = <0x05200000 0x100>; 476 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&ccu CLK_BUS_OHCI1>, 478 <&ccu CLK_BUS_EHCI1>, 479 <&ccu CLK_USB_OHCI1>; 480 resets = <&ccu RST_BUS_OHCI1>, 481 <&ccu RST_BUS_EHCI1>; 482 phys = <&usbphy 1>; 483 phy-names = "usb"; 484 status = "disabled"; 485 }; 486 487 ohci1: usb@5200400 { 488 compatible = "allwinner,sun50i-a100-ohci", 489 "generic-ohci"; 490 reg = <0x05200400 0x100>; 491 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_OHCI1>, 493 <&ccu CLK_USB_OHCI1>; 494 resets = <&ccu RST_BUS_OHCI1>; 495 phys = <&usbphy 1>; 496 phy-names = "usb"; 497 status = "disabled"; 498 }; 499 500 r_ccu: clock@7010000 { 501 compatible = "allwinner,sun50i-a100-r-ccu"; 502 reg = <0x07010000 0x300>; 503 clocks = <&dcxo24M>, <&osc32k>, <&iosc>, 504 <&ccu CLK_PLL_PERIPH0>; 505 clock-names = "hosc", "losc", "iosc", "pll-periph"; 506 #clock-cells = <1>; 507 #reset-cells = <1>; 508 }; 509 510 r_intc: interrupt-controller@7010320 { 511 compatible = "allwinner,sun50i-a100-nmi", 512 "allwinner,sun9i-a80-nmi"; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 reg = <0x07010320 0xc>; 516 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 517 }; 518 519 r_pio: pinctrl@7022000 { 520 compatible = "allwinner,sun50i-a100-r-pinctrl"; 521 reg = <0x07022000 0x400>; 522 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; 524 clock-names = "apb", "hosc", "losc"; 525 gpio-controller; 526 #gpio-cells = <3>; 527 interrupt-controller; 528 #interrupt-cells = <3>; 529 530 r_i2c0_pins: r-i2c0-pins { 531 pins = "PL0", "PL1"; 532 function = "s_i2c0"; 533 }; 534 535 r_i2c1_pins: r-i2c1-pins { 536 pins = "PL8", "PL9"; 537 function = "s_i2c1"; 538 }; 539 }; 540 541 r_uart: serial@7080000 { 542 compatible = "snps,dw-apb-uart"; 543 reg = <0x07080000 0x400>; 544 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 545 reg-shift = <2>; 546 reg-io-width = <4>; 547 clocks = <&r_ccu CLK_R_APB2_UART>; 548 resets = <&r_ccu RST_R_APB2_UART>; 549 status = "disabled"; 550 }; 551 552 r_i2c0: i2c@7081400 { 553 compatible = "allwinner,sun50i-a100-i2c", 554 "allwinner,sun8i-v536-i2c", 555 "allwinner,sun6i-a31-i2c"; 556 reg = <0x07081400 0x400>; 557 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&r_ccu CLK_R_APB2_I2C0>; 559 resets = <&r_ccu RST_R_APB2_I2C0>; 560 dmas = <&dma 50>, <&dma 50>; 561 dma-names = "rx", "tx"; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&r_i2c0_pins>; 564 status = "disabled"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 }; 568 569 r_i2c1: i2c@7081800 { 570 compatible = "allwinner,sun50i-a100-i2c", 571 "allwinner,sun8i-v536-i2c", 572 "allwinner,sun6i-a31-i2c"; 573 reg = <0x07081800 0x400>; 574 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&r_ccu CLK_R_APB2_I2C1>; 576 resets = <&r_ccu RST_R_APB2_I2C1>; 577 dmas = <&dma 51>, <&dma 51>; 578 dma-names = "rx", "tx"; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&r_i2c1_pins>; 581 status = "disabled"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 }; 585 }; 586 587 thermal-zones { 588 cpu-thermal { 589 polling-delay-passive = <0>; 590 polling-delay = <0>; 591 thermal-sensors = <&ths 0>; 592 }; 593 594 ddr-thermal { 595 polling-delay-passive = <0>; 596 polling-delay = <0>; 597 thermal-sensors = <&ths 2>; 598 }; 599 600 gpu-thermal { 601 polling-delay-passive = <0>; 602 polling-delay = <0>; 603 thermal-sensors = <&ths 1>; 604 }; 605 }; 606}; 607