1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <[email protected]> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 clock-frequency = <650000000>; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 psci { 34 compatible = "arm,psci-1.0"; 35 method = "smc"; 36 }; 37 38 intc: interrupt-controller@a0021000 { 39 compatible = "arm,cortex-a7-gic"; 40 #interrupt-cells = <3>; 41 interrupt-controller; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&intc>; 53 arm,no-tick-in-suspend; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&exti 61 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 134 interrupt-names = "rx", "tx"; 135 clocks = <&rcc IPCC>; 136 wakeup-source; 137 status = "disabled"; 138 }; 139 140 rcc: rcc@50000000 { 141 compatible = "st,stm32mp1-rcc", "syscon"; 142 reg = <0x50000000 0x1000>; 143 #clock-cells = <1>; 144 #reset-cells = <1>; 145 }; 146 147 pwr_regulators: pwr@50001000 { 148 compatible = "st,stm32mp1,pwr-reg"; 149 reg = <0x50001000 0x10>; 150 151 reg11: reg11 { 152 regulator-name = "reg11"; 153 regulator-min-microvolt = <1100000>; 154 regulator-max-microvolt = <1100000>; 155 }; 156 157 reg18: reg18 { 158 regulator-name = "reg18"; 159 regulator-min-microvolt = <1800000>; 160 regulator-max-microvolt = <1800000>; 161 }; 162 163 usb33: usb33 { 164 regulator-name = "usb33"; 165 regulator-min-microvolt = <3300000>; 166 regulator-max-microvolt = <3300000>; 167 }; 168 }; 169 170 pwr_mcu: pwr_mcu@50001014 { 171 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 172 reg = <0x50001014 0x4>; 173 }; 174 175 exti: interrupt-controller@5000d000 { 176 compatible = "st,stm32mp1-exti", "syscon"; 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 reg = <0x5000d000 0x400>; 180 interrupts-extended = 181 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 182 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 183 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 184 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 185 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 186 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 187 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 188 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 189 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 190 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 191 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 192 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 193 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 197 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 198 <0>, 199 <0>, 200 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 201 <0>, /* EXTI_20 */ 202 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 203 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 207 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 208 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 209 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 210 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 211 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 212 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 213 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 214 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 215 <0>, 216 <0>, 217 <0>, 218 <0>, 219 <0>, 220 <0>, 221 <0>, /* EXTI_40 */ 222 <0>, 223 <0>, 224 <0>, 225 <0>, 226 <0>, 227 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 228 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 229 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 230 <0>, 231 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 232 <0>, 233 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 234 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 235 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 236 <0>, 237 <0>, 238 <0>, 239 <0>, 240 <0>, 241 <0>, /* EXTI_60 */ 242 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 243 <0>, 244 <0>, 245 <0>, 246 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 247 <0>, 248 <0>, 249 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 250 <0>, 251 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 252 <0>, 253 <0>, 254 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 255 }; 256 257 syscfg: syscon@50020000 { 258 compatible = "st,stm32mp157-syscfg", "syscon"; 259 reg = <0x50020000 0x400>; 260 clocks = <&rcc SYSCFG>; 261 }; 262 263 dts: thermal@50028000 { 264 compatible = "st,stm32-thermal"; 265 reg = <0x50028000 0x100>; 266 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&rcc TMPSENS>; 268 clock-names = "pclk"; 269 #thermal-sensor-cells = <0>; 270 status = "disabled"; 271 }; 272 273 mdma1: dma-controller@58000000 { 274 compatible = "st,stm32h7-mdma"; 275 reg = <0x58000000 0x1000>; 276 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&rcc MDMA>; 278 resets = <&rcc MDMA_R>; 279 #dma-cells = <5>; 280 dma-channels = <32>; 281 dma-requests = <48>; 282 }; 283 284 sdmmc1: mmc@58005000 { 285 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 286 arm,primecell-periphid = <0x00253180>; 287 reg = <0x58005000 0x1000>; 288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&rcc SDMMC1_K>; 290 clock-names = "apb_pclk"; 291 resets = <&rcc SDMMC1_R>; 292 cap-sd-highspeed; 293 cap-mmc-highspeed; 294 max-frequency = <120000000>; 295 status = "disabled"; 296 }; 297 298 sdmmc2: mmc@58007000 { 299 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 300 arm,primecell-periphid = <0x00253180>; 301 reg = <0x58007000 0x1000>; 302 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&rcc SDMMC2_K>; 304 clock-names = "apb_pclk"; 305 resets = <&rcc SDMMC2_R>; 306 cap-sd-highspeed; 307 cap-mmc-highspeed; 308 max-frequency = <120000000>; 309 status = "disabled"; 310 }; 311 312 crc1: crc@58009000 { 313 compatible = "st,stm32f7-crc"; 314 reg = <0x58009000 0x400>; 315 clocks = <&rcc CRC1>; 316 status = "disabled"; 317 }; 318 319 usbh_ohci: usb@5800c000 { 320 compatible = "generic-ohci"; 321 reg = <0x5800c000 0x1000>; 322 clocks = <&usbphyc>, <&rcc USBH>; 323 resets = <&rcc USBH_R>; 324 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 325 phys = <&usbphyc_port0>; 326 phy-names = "usb"; 327 status = "disabled"; 328 }; 329 330 usbh_ehci: usb@5800d000 { 331 compatible = "generic-ehci"; 332 reg = <0x5800d000 0x1000>; 333 clocks = <&usbphyc>, <&rcc USBH>; 334 resets = <&rcc USBH_R>; 335 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 336 companion = <&usbh_ohci>; 337 phys = <&usbphyc_port0>; 338 phy-names = "usb"; 339 status = "disabled"; 340 }; 341 342 ltdc: display-controller@5a001000 { 343 compatible = "st,stm32-ltdc"; 344 reg = <0x5a001000 0x400>; 345 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&rcc LTDC_PX>; 348 clock-names = "lcd"; 349 resets = <&rcc LTDC_R>; 350 status = "disabled"; 351 }; 352 353 iwdg2: watchdog@5a002000 { 354 compatible = "st,stm32mp1-iwdg"; 355 reg = <0x5a002000 0x400>; 356 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 357 clock-names = "pclk", "lsi"; 358 interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>; 359 wakeup-source; 360 status = "disabled"; 361 }; 362 363 usbphyc: usbphyc@5a006000 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 #clock-cells = <0>; 367 compatible = "st,stm32mp1-usbphyc"; 368 reg = <0x5a006000 0x1000>; 369 clocks = <&rcc USBPHY_K>; 370 resets = <&rcc USBPHY_R>; 371 vdda1v1-supply = <®11>; 372 vdda1v8-supply = <®18>; 373 status = "disabled"; 374 375 usbphyc_port0: usb-phy@0 { 376 #phy-cells = <0>; 377 reg = <0>; 378 }; 379 380 usbphyc_port1: usb-phy@1 { 381 #phy-cells = <1>; 382 reg = <1>; 383 }; 384 }; 385 386 rtc: rtc@5c004000 { 387 compatible = "st,stm32mp1-rtc"; 388 reg = <0x5c004000 0x400>; 389 clocks = <&rcc RTCAPB>, <&rcc RTC>; 390 clock-names = "pclk", "rtc_ck"; 391 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 392 status = "disabled"; 393 }; 394 395 bsec: efuse@5c005000 { 396 compatible = "st,stm32mp15-bsec"; 397 reg = <0x5c005000 0x400>; 398 #address-cells = <1>; 399 #size-cells = <1>; 400 part_number_otp: part-number-otp@4 { 401 reg = <0x4 0x1>; 402 }; 403 vrefint: vrefin-cal@52 { 404 reg = <0x52 0x2>; 405 }; 406 ts_cal1: calib@5c { 407 reg = <0x5c 0x2>; 408 }; 409 ts_cal2: calib@5e { 410 reg = <0x5e 0x2>; 411 }; 412 }; 413 414 etzpc: bus@5c007000 { 415 compatible = "st,stm32-etzpc", "simple-bus"; 416 reg = <0x5c007000 0x400>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 #access-controller-cells = <1>; 420 ranges; 421 422 timers2: timer@40000000 { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 compatible = "st,stm32-timers"; 426 reg = <0x40000000 0x400>; 427 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "global"; 429 clocks = <&rcc TIM2_K>; 430 clock-names = "int"; 431 dmas = <&dmamux1 18 0x400 0x1>, 432 <&dmamux1 19 0x400 0x1>, 433 <&dmamux1 20 0x400 0x1>, 434 <&dmamux1 21 0x400 0x1>, 435 <&dmamux1 22 0x400 0x1>; 436 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 437 access-controllers = <&etzpc 16>; 438 status = "disabled"; 439 440 pwm { 441 compatible = "st,stm32-pwm"; 442 #pwm-cells = <3>; 443 status = "disabled"; 444 }; 445 446 timer@1 { 447 compatible = "st,stm32h7-timer-trigger"; 448 reg = <1>; 449 status = "disabled"; 450 }; 451 452 counter { 453 compatible = "st,stm32-timer-counter"; 454 status = "disabled"; 455 }; 456 }; 457 458 timers3: timer@40001000 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 compatible = "st,stm32-timers"; 462 reg = <0x40001000 0x400>; 463 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 464 interrupt-names = "global"; 465 clocks = <&rcc TIM3_K>; 466 clock-names = "int"; 467 dmas = <&dmamux1 23 0x400 0x1>, 468 <&dmamux1 24 0x400 0x1>, 469 <&dmamux1 25 0x400 0x1>, 470 <&dmamux1 26 0x400 0x1>, 471 <&dmamux1 27 0x400 0x1>, 472 <&dmamux1 28 0x400 0x1>; 473 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 474 access-controllers = <&etzpc 17>; 475 status = "disabled"; 476 477 pwm { 478 compatible = "st,stm32-pwm"; 479 #pwm-cells = <3>; 480 status = "disabled"; 481 }; 482 483 timer@2 { 484 compatible = "st,stm32h7-timer-trigger"; 485 reg = <2>; 486 status = "disabled"; 487 }; 488 489 counter { 490 compatible = "st,stm32-timer-counter"; 491 status = "disabled"; 492 }; 493 }; 494 495 timers4: timer@40002000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "st,stm32-timers"; 499 reg = <0x40002000 0x400>; 500 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-names = "global"; 502 clocks = <&rcc TIM4_K>; 503 clock-names = "int"; 504 dmas = <&dmamux1 29 0x400 0x1>, 505 <&dmamux1 30 0x400 0x1>, 506 <&dmamux1 31 0x400 0x1>, 507 <&dmamux1 32 0x400 0x1>; 508 dma-names = "ch1", "ch2", "ch3", "ch4"; 509 access-controllers = <&etzpc 18>; 510 status = "disabled"; 511 512 pwm { 513 compatible = "st,stm32-pwm"; 514 #pwm-cells = <3>; 515 status = "disabled"; 516 }; 517 518 timer@3 { 519 compatible = "st,stm32h7-timer-trigger"; 520 reg = <3>; 521 status = "disabled"; 522 }; 523 524 counter { 525 compatible = "st,stm32-timer-counter"; 526 status = "disabled"; 527 }; 528 }; 529 530 timers5: timer@40003000 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 compatible = "st,stm32-timers"; 534 reg = <0x40003000 0x400>; 535 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 536 interrupt-names = "global"; 537 clocks = <&rcc TIM5_K>; 538 clock-names = "int"; 539 dmas = <&dmamux1 55 0x400 0x1>, 540 <&dmamux1 56 0x400 0x1>, 541 <&dmamux1 57 0x400 0x1>, 542 <&dmamux1 58 0x400 0x1>, 543 <&dmamux1 59 0x400 0x1>, 544 <&dmamux1 60 0x400 0x1>; 545 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 546 access-controllers = <&etzpc 19>; 547 status = "disabled"; 548 549 pwm { 550 compatible = "st,stm32-pwm"; 551 #pwm-cells = <3>; 552 status = "disabled"; 553 }; 554 555 timer@4 { 556 compatible = "st,stm32h7-timer-trigger"; 557 reg = <4>; 558 status = "disabled"; 559 }; 560 561 counter { 562 compatible = "st,stm32-timer-counter"; 563 status = "disabled"; 564 }; 565 }; 566 567 timers6: timer@40004000 { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 compatible = "st,stm32-timers"; 571 reg = <0x40004000 0x400>; 572 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "global"; 574 clocks = <&rcc TIM6_K>; 575 clock-names = "int"; 576 dmas = <&dmamux1 69 0x400 0x1>; 577 dma-names = "up"; 578 access-controllers = <&etzpc 20>; 579 status = "disabled"; 580 581 counter { 582 compatible = "st,stm32-timer-counter"; 583 status = "disabled"; 584 }; 585 586 timer@5 { 587 compatible = "st,stm32h7-timer-trigger"; 588 reg = <5>; 589 status = "disabled"; 590 }; 591 }; 592 593 timers7: timer@40005000 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 compatible = "st,stm32-timers"; 597 reg = <0x40005000 0x400>; 598 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "global"; 600 clocks = <&rcc TIM7_K>; 601 clock-names = "int"; 602 dmas = <&dmamux1 70 0x400 0x1>; 603 dma-names = "up"; 604 access-controllers = <&etzpc 21>; 605 status = "disabled"; 606 607 counter { 608 compatible = "st,stm32-timer-counter"; 609 status = "disabled"; 610 }; 611 612 timer@6 { 613 compatible = "st,stm32h7-timer-trigger"; 614 reg = <6>; 615 status = "disabled"; 616 }; 617 }; 618 619 timers12: timer@40006000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 compatible = "st,stm32-timers"; 623 reg = <0x40006000 0x400>; 624 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 625 interrupt-names = "global"; 626 clocks = <&rcc TIM12_K>; 627 clock-names = "int"; 628 access-controllers = <&etzpc 22>; 629 status = "disabled"; 630 631 counter { 632 compatible = "st,stm32-timer-counter"; 633 status = "disabled"; 634 }; 635 636 pwm { 637 compatible = "st,stm32-pwm"; 638 #pwm-cells = <3>; 639 status = "disabled"; 640 }; 641 642 timer@11 { 643 compatible = "st,stm32h7-timer-trigger"; 644 reg = <11>; 645 status = "disabled"; 646 }; 647 }; 648 649 timers13: timer@40007000 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 compatible = "st,stm32-timers"; 653 reg = <0x40007000 0x400>; 654 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-names = "global"; 656 clocks = <&rcc TIM13_K>; 657 clock-names = "int"; 658 access-controllers = <&etzpc 23>; 659 status = "disabled"; 660 661 counter { 662 compatible = "st,stm32-timer-counter"; 663 status = "disabled"; 664 }; 665 666 pwm { 667 compatible = "st,stm32-pwm"; 668 #pwm-cells = <3>; 669 status = "disabled"; 670 }; 671 672 timer@12 { 673 compatible = "st,stm32h7-timer-trigger"; 674 reg = <12>; 675 status = "disabled"; 676 }; 677 }; 678 679 timers14: timer@40008000 { 680 #address-cells = <1>; 681 #size-cells = <0>; 682 compatible = "st,stm32-timers"; 683 reg = <0x40008000 0x400>; 684 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "global"; 686 clocks = <&rcc TIM14_K>; 687 clock-names = "int"; 688 access-controllers = <&etzpc 24>; 689 status = "disabled"; 690 691 counter { 692 compatible = "st,stm32-timer-counter"; 693 status = "disabled"; 694 }; 695 696 pwm { 697 compatible = "st,stm32-pwm"; 698 #pwm-cells = <3>; 699 status = "disabled"; 700 }; 701 702 timer@13 { 703 compatible = "st,stm32h7-timer-trigger"; 704 reg = <13>; 705 status = "disabled"; 706 }; 707 }; 708 709 lptimer1: timer@40009000 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 compatible = "st,stm32-lptimer"; 713 reg = <0x40009000 0x400>; 714 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&rcc LPTIM1_K>; 716 clock-names = "mux"; 717 wakeup-source; 718 access-controllers = <&etzpc 25>; 719 status = "disabled"; 720 721 pwm { 722 compatible = "st,stm32-pwm-lp"; 723 #pwm-cells = <3>; 724 status = "disabled"; 725 }; 726 727 trigger@0 { 728 compatible = "st,stm32-lptimer-trigger"; 729 reg = <0>; 730 status = "disabled"; 731 }; 732 733 counter { 734 compatible = "st,stm32-lptimer-counter"; 735 status = "disabled"; 736 }; 737 }; 738 739 i2s2: audio-controller@4000b000 { 740 compatible = "st,stm32h7-i2s"; 741 #sound-dai-cells = <0>; 742 reg = <0x4000b000 0x400>; 743 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 744 dmas = <&dmamux1 39 0x400 0x01>, 745 <&dmamux1 40 0x400 0x01>; 746 dma-names = "rx", "tx"; 747 access-controllers = <&etzpc 27>; 748 status = "disabled"; 749 }; 750 751 spi2: spi@4000b000 { 752 #address-cells = <1>; 753 #size-cells = <0>; 754 compatible = "st,stm32h7-spi"; 755 reg = <0x4000b000 0x400>; 756 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&rcc SPI2_K>; 758 resets = <&rcc SPI2_R>; 759 dmas = <&dmamux1 39 0x400 0x05>, 760 <&dmamux1 40 0x400 0x05>; 761 dma-names = "rx", "tx"; 762 access-controllers = <&etzpc 27>; 763 status = "disabled"; 764 }; 765 766 i2s3: audio-controller@4000c000 { 767 compatible = "st,stm32h7-i2s"; 768 #sound-dai-cells = <0>; 769 reg = <0x4000c000 0x400>; 770 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 771 dmas = <&dmamux1 61 0x400 0x01>, 772 <&dmamux1 62 0x400 0x01>; 773 dma-names = "rx", "tx"; 774 access-controllers = <&etzpc 28>; 775 status = "disabled"; 776 }; 777 778 spi3: spi@4000c000 { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 compatible = "st,stm32h7-spi"; 782 reg = <0x4000c000 0x400>; 783 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&rcc SPI3_K>; 785 resets = <&rcc SPI3_R>; 786 dmas = <&dmamux1 61 0x400 0x05>, 787 <&dmamux1 62 0x400 0x05>; 788 dma-names = "rx", "tx"; 789 access-controllers = <&etzpc 28>; 790 status = "disabled"; 791 }; 792 793 spdifrx: audio-controller@4000d000 { 794 compatible = "st,stm32h7-spdifrx"; 795 #sound-dai-cells = <0>; 796 reg = <0x4000d000 0x400>; 797 clocks = <&rcc SPDIF_K>; 798 clock-names = "kclk"; 799 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 800 dmas = <&dmamux1 93 0x400 0x01>, 801 <&dmamux1 94 0x400 0x01>; 802 dma-names = "rx", "rx-ctrl"; 803 access-controllers = <&etzpc 29>; 804 status = "disabled"; 805 }; 806 807 usart2: serial@4000e000 { 808 compatible = "st,stm32h7-uart"; 809 reg = <0x4000e000 0x400>; 810 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&rcc USART2_K>; 812 wakeup-source; 813 dmas = <&dmamux1 43 0x400 0x15>, 814 <&dmamux1 44 0x400 0x11>; 815 dma-names = "rx", "tx"; 816 access-controllers = <&etzpc 30>; 817 status = "disabled"; 818 }; 819 820 usart3: serial@4000f000 { 821 compatible = "st,stm32h7-uart"; 822 reg = <0x4000f000 0x400>; 823 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&rcc USART3_K>; 825 wakeup-source; 826 dmas = <&dmamux1 45 0x400 0x15>, 827 <&dmamux1 46 0x400 0x11>; 828 dma-names = "rx", "tx"; 829 access-controllers = <&etzpc 31>; 830 status = "disabled"; 831 }; 832 833 uart4: serial@40010000 { 834 compatible = "st,stm32h7-uart"; 835 reg = <0x40010000 0x400>; 836 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&rcc UART4_K>; 838 wakeup-source; 839 dmas = <&dmamux1 63 0x400 0x15>, 840 <&dmamux1 64 0x400 0x11>; 841 dma-names = "rx", "tx"; 842 access-controllers = <&etzpc 32>; 843 status = "disabled"; 844 }; 845 846 uart5: serial@40011000 { 847 compatible = "st,stm32h7-uart"; 848 reg = <0x40011000 0x400>; 849 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&rcc UART5_K>; 851 wakeup-source; 852 dmas = <&dmamux1 65 0x400 0x15>, 853 <&dmamux1 66 0x400 0x11>; 854 dma-names = "rx", "tx"; 855 access-controllers = <&etzpc 33>; 856 status = "disabled"; 857 }; 858 859 i2c1: i2c@40012000 { 860 compatible = "st,stm32mp15-i2c"; 861 reg = <0x40012000 0x400>; 862 interrupt-names = "event", "error"; 863 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&rcc I2C1_K>; 866 resets = <&rcc I2C1_R>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 st,syscfg-fmp = <&syscfg 0x4 0x1>; 870 wakeup-source; 871 i2c-analog-filter; 872 access-controllers = <&etzpc 34>; 873 status = "disabled"; 874 }; 875 876 i2c2: i2c@40013000 { 877 compatible = "st,stm32mp15-i2c"; 878 reg = <0x40013000 0x400>; 879 interrupt-names = "event", "error"; 880 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&rcc I2C2_K>; 883 resets = <&rcc I2C2_R>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 st,syscfg-fmp = <&syscfg 0x4 0x2>; 887 wakeup-source; 888 i2c-analog-filter; 889 access-controllers = <&etzpc 35>; 890 status = "disabled"; 891 }; 892 893 i2c3: i2c@40014000 { 894 compatible = "st,stm32mp15-i2c"; 895 reg = <0x40014000 0x400>; 896 interrupt-names = "event", "error"; 897 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&rcc I2C3_K>; 900 resets = <&rcc I2C3_R>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 st,syscfg-fmp = <&syscfg 0x4 0x4>; 904 wakeup-source; 905 i2c-analog-filter; 906 access-controllers = <&etzpc 36>; 907 status = "disabled"; 908 }; 909 910 i2c5: i2c@40015000 { 911 compatible = "st,stm32mp15-i2c"; 912 reg = <0x40015000 0x400>; 913 interrupt-names = "event", "error"; 914 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&rcc I2C5_K>; 917 resets = <&rcc I2C5_R>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 st,syscfg-fmp = <&syscfg 0x4 0x10>; 921 wakeup-source; 922 i2c-analog-filter; 923 access-controllers = <&etzpc 37>; 924 status = "disabled"; 925 }; 926 927 cec: cec@40016000 { 928 compatible = "st,stm32-cec"; 929 reg = <0x40016000 0x400>; 930 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&rcc CEC_K>, <&rcc CEC>; 932 clock-names = "cec", "hdmi-cec"; 933 access-controllers = <&etzpc 38>; 934 status = "disabled"; 935 }; 936 937 dac: dac@40017000 { 938 compatible = "st,stm32h7-dac-core"; 939 reg = <0x40017000 0x400>; 940 clocks = <&rcc DAC12>; 941 clock-names = "pclk"; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 access-controllers = <&etzpc 39>; 945 status = "disabled"; 946 947 dac1: dac@1 { 948 compatible = "st,stm32-dac"; 949 #io-channel-cells = <1>; 950 reg = <1>; 951 status = "disabled"; 952 }; 953 954 dac2: dac@2 { 955 compatible = "st,stm32-dac"; 956 #io-channel-cells = <1>; 957 reg = <2>; 958 status = "disabled"; 959 }; 960 }; 961 962 uart7: serial@40018000 { 963 compatible = "st,stm32h7-uart"; 964 reg = <0x40018000 0x400>; 965 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&rcc UART7_K>; 967 wakeup-source; 968 dmas = <&dmamux1 79 0x400 0x15>, 969 <&dmamux1 80 0x400 0x11>; 970 dma-names = "rx", "tx"; 971 access-controllers = <&etzpc 40>; 972 status = "disabled"; 973 }; 974 975 uart8: serial@40019000 { 976 compatible = "st,stm32h7-uart"; 977 reg = <0x40019000 0x400>; 978 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&rcc UART8_K>; 980 wakeup-source; 981 dmas = <&dmamux1 81 0x400 0x15>, 982 <&dmamux1 82 0x400 0x11>; 983 dma-names = "rx", "tx"; 984 access-controllers = <&etzpc 41>; 985 status = "disabled"; 986 }; 987 988 timers1: timer@44000000 { 989 #address-cells = <1>; 990 #size-cells = <0>; 991 compatible = "st,stm32-timers"; 992 reg = <0x44000000 0x400>; 993 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-names = "brk", "up", "trg-com", "cc"; 998 clocks = <&rcc TIM1_K>; 999 clock-names = "int"; 1000 dmas = <&dmamux1 11 0x400 0x1>, 1001 <&dmamux1 12 0x400 0x1>, 1002 <&dmamux1 13 0x400 0x1>, 1003 <&dmamux1 14 0x400 0x1>, 1004 <&dmamux1 15 0x400 0x1>, 1005 <&dmamux1 16 0x400 0x1>, 1006 <&dmamux1 17 0x400 0x1>; 1007 dma-names = "ch1", "ch2", "ch3", "ch4", 1008 "up", "trig", "com"; 1009 access-controllers = <&etzpc 48>; 1010 status = "disabled"; 1011 1012 pwm { 1013 compatible = "st,stm32-pwm"; 1014 #pwm-cells = <3>; 1015 status = "disabled"; 1016 }; 1017 1018 timer@0 { 1019 compatible = "st,stm32h7-timer-trigger"; 1020 reg = <0>; 1021 status = "disabled"; 1022 }; 1023 1024 counter { 1025 compatible = "st,stm32-timer-counter"; 1026 status = "disabled"; 1027 }; 1028 }; 1029 1030 timers8: timer@44001000 { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 compatible = "st,stm32-timers"; 1034 reg = <0x44001000 0x400>; 1035 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1039 interrupt-names = "brk", "up", "trg-com", "cc"; 1040 clocks = <&rcc TIM8_K>; 1041 clock-names = "int"; 1042 dmas = <&dmamux1 47 0x400 0x1>, 1043 <&dmamux1 48 0x400 0x1>, 1044 <&dmamux1 49 0x400 0x1>, 1045 <&dmamux1 50 0x400 0x1>, 1046 <&dmamux1 51 0x400 0x1>, 1047 <&dmamux1 52 0x400 0x1>, 1048 <&dmamux1 53 0x400 0x1>; 1049 dma-names = "ch1", "ch2", "ch3", "ch4", 1050 "up", "trig", "com"; 1051 access-controllers = <&etzpc 49>; 1052 status = "disabled"; 1053 1054 pwm { 1055 compatible = "st,stm32-pwm"; 1056 #pwm-cells = <3>; 1057 status = "disabled"; 1058 }; 1059 1060 timer@7 { 1061 compatible = "st,stm32h7-timer-trigger"; 1062 reg = <7>; 1063 status = "disabled"; 1064 }; 1065 1066 counter { 1067 compatible = "st,stm32-timer-counter"; 1068 status = "disabled"; 1069 }; 1070 }; 1071 1072 usart6: serial@44003000 { 1073 compatible = "st,stm32h7-uart"; 1074 reg = <0x44003000 0x400>; 1075 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&rcc USART6_K>; 1077 wakeup-source; 1078 dmas = <&dmamux1 71 0x400 0x15>, 1079 <&dmamux1 72 0x400 0x11>; 1080 dma-names = "rx", "tx"; 1081 access-controllers = <&etzpc 51>; 1082 status = "disabled"; 1083 }; 1084 1085 i2s1: audio-controller@44004000 { 1086 compatible = "st,stm32h7-i2s"; 1087 #sound-dai-cells = <0>; 1088 reg = <0x44004000 0x400>; 1089 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1090 dmas = <&dmamux1 37 0x400 0x01>, 1091 <&dmamux1 38 0x400 0x01>; 1092 dma-names = "rx", "tx"; 1093 access-controllers = <&etzpc 52>; 1094 status = "disabled"; 1095 }; 1096 1097 spi1: spi@44004000 { 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 compatible = "st,stm32h7-spi"; 1101 reg = <0x44004000 0x400>; 1102 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&rcc SPI1_K>; 1104 resets = <&rcc SPI1_R>; 1105 dmas = <&dmamux1 37 0x400 0x05>, 1106 <&dmamux1 38 0x400 0x05>; 1107 dma-names = "rx", "tx"; 1108 access-controllers = <&etzpc 52>; 1109 status = "disabled"; 1110 }; 1111 1112 spi4: spi@44005000 { 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 compatible = "st,stm32h7-spi"; 1116 reg = <0x44005000 0x400>; 1117 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&rcc SPI4_K>; 1119 resets = <&rcc SPI4_R>; 1120 dmas = <&dmamux1 83 0x400 0x05>, 1121 <&dmamux1 84 0x400 0x05>; 1122 dma-names = "rx", "tx"; 1123 access-controllers = <&etzpc 53>; 1124 status = "disabled"; 1125 }; 1126 1127 timers15: timer@44006000 { 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 compatible = "st,stm32-timers"; 1131 reg = <0x44006000 0x400>; 1132 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1133 interrupt-names = "global"; 1134 clocks = <&rcc TIM15_K>; 1135 clock-names = "int"; 1136 dmas = <&dmamux1 105 0x400 0x1>, 1137 <&dmamux1 106 0x400 0x1>, 1138 <&dmamux1 107 0x400 0x1>, 1139 <&dmamux1 108 0x400 0x1>; 1140 dma-names = "ch1", "up", "trig", "com"; 1141 access-controllers = <&etzpc 54>; 1142 status = "disabled"; 1143 1144 counter { 1145 compatible = "st,stm32-timer-counter"; 1146 status = "disabled"; 1147 }; 1148 1149 pwm { 1150 compatible = "st,stm32-pwm"; 1151 #pwm-cells = <3>; 1152 status = "disabled"; 1153 }; 1154 1155 timer@14 { 1156 compatible = "st,stm32h7-timer-trigger"; 1157 reg = <14>; 1158 status = "disabled"; 1159 }; 1160 }; 1161 1162 timers16: timer@44007000 { 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 compatible = "st,stm32-timers"; 1166 reg = <0x44007000 0x400>; 1167 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1168 interrupt-names = "global"; 1169 clocks = <&rcc TIM16_K>; 1170 clock-names = "int"; 1171 dmas = <&dmamux1 109 0x400 0x1>, 1172 <&dmamux1 110 0x400 0x1>; 1173 dma-names = "ch1", "up"; 1174 access-controllers = <&etzpc 55>; 1175 status = "disabled"; 1176 1177 counter { 1178 compatible = "st,stm32-timer-counter"; 1179 status = "disabled"; 1180 }; 1181 1182 pwm { 1183 compatible = "st,stm32-pwm"; 1184 #pwm-cells = <3>; 1185 status = "disabled"; 1186 }; 1187 1188 timer@15 { 1189 compatible = "st,stm32h7-timer-trigger"; 1190 reg = <15>; 1191 status = "disabled"; 1192 }; 1193 }; 1194 1195 timers17: timer@44008000 { 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 compatible = "st,stm32-timers"; 1199 reg = <0x44008000 0x400>; 1200 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1201 interrupt-names = "global"; 1202 clocks = <&rcc TIM17_K>; 1203 clock-names = "int"; 1204 dmas = <&dmamux1 111 0x400 0x1>, 1205 <&dmamux1 112 0x400 0x1>; 1206 dma-names = "ch1", "up"; 1207 access-controllers = <&etzpc 56>; 1208 status = "disabled"; 1209 1210 counter { 1211 compatible = "st,stm32-timer-counter"; 1212 status = "disabled"; 1213 }; 1214 1215 pwm { 1216 compatible = "st,stm32-pwm"; 1217 #pwm-cells = <3>; 1218 status = "disabled"; 1219 }; 1220 1221 timer@16 { 1222 compatible = "st,stm32h7-timer-trigger"; 1223 reg = <16>; 1224 status = "disabled"; 1225 }; 1226 }; 1227 1228 spi5: spi@44009000 { 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 compatible = "st,stm32h7-spi"; 1232 reg = <0x44009000 0x400>; 1233 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&rcc SPI5_K>; 1235 resets = <&rcc SPI5_R>; 1236 dmas = <&dmamux1 85 0x400 0x05>, 1237 <&dmamux1 86 0x400 0x05>; 1238 dma-names = "rx", "tx"; 1239 access-controllers = <&etzpc 57>; 1240 status = "disabled"; 1241 }; 1242 1243 sai1: sai@4400a000 { 1244 compatible = "st,stm32h7-sai"; 1245 #address-cells = <1>; 1246 #size-cells = <1>; 1247 ranges = <0 0x4400a000 0x400>; 1248 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1249 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1250 resets = <&rcc SAI1_R>; 1251 access-controllers = <&etzpc 58>; 1252 status = "disabled"; 1253 1254 sai1a: audio-controller@4400a004 { 1255 #sound-dai-cells = <0>; 1256 1257 compatible = "st,stm32-sai-sub-a"; 1258 reg = <0x4 0x20>; 1259 clocks = <&rcc SAI1_K>; 1260 clock-names = "sai_ck"; 1261 dmas = <&dmamux1 87 0x400 0x01>; 1262 status = "disabled"; 1263 }; 1264 1265 sai1b: audio-controller@4400a024 { 1266 #sound-dai-cells = <0>; 1267 compatible = "st,stm32-sai-sub-b"; 1268 reg = <0x24 0x20>; 1269 clocks = <&rcc SAI1_K>; 1270 clock-names = "sai_ck"; 1271 dmas = <&dmamux1 88 0x400 0x01>; 1272 status = "disabled"; 1273 }; 1274 }; 1275 1276 sai2: sai@4400b000 { 1277 compatible = "st,stm32h7-sai"; 1278 #address-cells = <1>; 1279 #size-cells = <1>; 1280 ranges = <0 0x4400b000 0x400>; 1281 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1282 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1283 resets = <&rcc SAI2_R>; 1284 access-controllers = <&etzpc 59>; 1285 status = "disabled"; 1286 1287 sai2a: audio-controller@4400b004 { 1288 #sound-dai-cells = <0>; 1289 compatible = "st,stm32-sai-sub-a"; 1290 reg = <0x4 0x20>; 1291 clocks = <&rcc SAI2_K>; 1292 clock-names = "sai_ck"; 1293 dmas = <&dmamux1 89 0x400 0x01>; 1294 status = "disabled"; 1295 }; 1296 1297 sai2b: audio-controller@4400b024 { 1298 #sound-dai-cells = <0>; 1299 compatible = "st,stm32-sai-sub-b"; 1300 reg = <0x24 0x20>; 1301 clocks = <&rcc SAI2_K>; 1302 clock-names = "sai_ck"; 1303 dmas = <&dmamux1 90 0x400 0x01>; 1304 status = "disabled"; 1305 }; 1306 }; 1307 1308 sai3: sai@4400c000 { 1309 compatible = "st,stm32h7-sai"; 1310 #address-cells = <1>; 1311 #size-cells = <1>; 1312 ranges = <0 0x4400c000 0x400>; 1313 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1314 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1315 resets = <&rcc SAI3_R>; 1316 access-controllers = <&etzpc 60>; 1317 status = "disabled"; 1318 1319 sai3a: audio-controller@4400c004 { 1320 #sound-dai-cells = <0>; 1321 compatible = "st,stm32-sai-sub-a"; 1322 reg = <0x04 0x20>; 1323 clocks = <&rcc SAI3_K>; 1324 clock-names = "sai_ck"; 1325 dmas = <&dmamux1 113 0x400 0x01>; 1326 status = "disabled"; 1327 }; 1328 1329 sai3b: audio-controller@4400c024 { 1330 #sound-dai-cells = <0>; 1331 compatible = "st,stm32-sai-sub-b"; 1332 reg = <0x24 0x20>; 1333 clocks = <&rcc SAI3_K>; 1334 clock-names = "sai_ck"; 1335 dmas = <&dmamux1 114 0x400 0x01>; 1336 status = "disabled"; 1337 }; 1338 }; 1339 1340 dfsdm: dfsdm@4400d000 { 1341 compatible = "st,stm32mp1-dfsdm"; 1342 reg = <0x4400d000 0x800>; 1343 clocks = <&rcc DFSDM_K>; 1344 clock-names = "dfsdm"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 access-controllers = <&etzpc 61>; 1348 status = "disabled"; 1349 1350 dfsdm0: filter@0 { 1351 compatible = "st,stm32-dfsdm-adc"; 1352 #io-channel-cells = <1>; 1353 reg = <0>; 1354 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1355 dmas = <&dmamux1 101 0x400 0x01>; 1356 dma-names = "rx"; 1357 status = "disabled"; 1358 }; 1359 1360 dfsdm1: filter@1 { 1361 compatible = "st,stm32-dfsdm-adc"; 1362 #io-channel-cells = <1>; 1363 reg = <1>; 1364 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1365 dmas = <&dmamux1 102 0x400 0x01>; 1366 dma-names = "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 dfsdm2: filter@2 { 1371 compatible = "st,stm32-dfsdm-adc"; 1372 #io-channel-cells = <1>; 1373 reg = <2>; 1374 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1375 dmas = <&dmamux1 103 0x400 0x01>; 1376 dma-names = "rx"; 1377 status = "disabled"; 1378 }; 1379 1380 dfsdm3: filter@3 { 1381 compatible = "st,stm32-dfsdm-adc"; 1382 #io-channel-cells = <1>; 1383 reg = <3>; 1384 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&dmamux1 104 0x400 0x01>; 1386 dma-names = "rx"; 1387 status = "disabled"; 1388 }; 1389 1390 dfsdm4: filter@4 { 1391 compatible = "st,stm32-dfsdm-adc"; 1392 #io-channel-cells = <1>; 1393 reg = <4>; 1394 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1395 dmas = <&dmamux1 91 0x400 0x01>; 1396 dma-names = "rx"; 1397 status = "disabled"; 1398 }; 1399 1400 dfsdm5: filter@5 { 1401 compatible = "st,stm32-dfsdm-adc"; 1402 #io-channel-cells = <1>; 1403 reg = <5>; 1404 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1405 dmas = <&dmamux1 92 0x400 0x01>; 1406 dma-names = "rx"; 1407 status = "disabled"; 1408 }; 1409 }; 1410 1411 dma1: dma-controller@48000000 { 1412 compatible = "st,stm32-dma"; 1413 reg = <0x48000000 0x400>; 1414 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1422 clocks = <&rcc DMA1>; 1423 resets = <&rcc DMA1_R>; 1424 #dma-cells = <4>; 1425 st,mem2mem; 1426 dma-requests = <8>; 1427 access-controllers = <&etzpc 88>; 1428 }; 1429 1430 dma2: dma-controller@48001000 { 1431 compatible = "st,stm32-dma"; 1432 reg = <0x48001000 0x400>; 1433 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1441 clocks = <&rcc DMA2>; 1442 resets = <&rcc DMA2_R>; 1443 #dma-cells = <4>; 1444 st,mem2mem; 1445 dma-requests = <8>; 1446 access-controllers = <&etzpc 89>; 1447 }; 1448 1449 dmamux1: dma-router@48002000 { 1450 compatible = "st,stm32h7-dmamux"; 1451 reg = <0x48002000 0x40>; 1452 #dma-cells = <3>; 1453 dma-requests = <128>; 1454 dma-masters = <&dma1 &dma2>; 1455 dma-channels = <16>; 1456 clocks = <&rcc DMAMUX>; 1457 resets = <&rcc DMAMUX_R>; 1458 access-controllers = <&etzpc 90>; 1459 }; 1460 1461 adc: adc@48003000 { 1462 compatible = "st,stm32mp1-adc-core"; 1463 reg = <0x48003000 0x400>; 1464 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1466 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1467 clock-names = "bus", "adc"; 1468 interrupt-controller; 1469 st,syscfg = <&syscfg>; 1470 #interrupt-cells = <1>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 access-controllers = <&etzpc 72>; 1474 status = "disabled"; 1475 1476 adc1: adc@0 { 1477 compatible = "st,stm32mp1-adc"; 1478 #io-channel-cells = <1>; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 reg = <0x0>; 1482 interrupt-parent = <&adc>; 1483 interrupts = <0>; 1484 dmas = <&dmamux1 9 0x400 0x01>; 1485 dma-names = "rx"; 1486 status = "disabled"; 1487 }; 1488 1489 adc2: adc@100 { 1490 compatible = "st,stm32mp1-adc"; 1491 #io-channel-cells = <1>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 reg = <0x100>; 1495 interrupt-parent = <&adc>; 1496 interrupts = <1>; 1497 dmas = <&dmamux1 10 0x400 0x01>; 1498 dma-names = "rx"; 1499 nvmem-cells = <&vrefint>; 1500 nvmem-cell-names = "vrefint"; 1501 status = "disabled"; 1502 channel@13 { 1503 reg = <13>; 1504 label = "vrefint"; 1505 }; 1506 channel@14 { 1507 reg = <14>; 1508 label = "vddcore"; 1509 }; 1510 }; 1511 }; 1512 1513 sdmmc3: mmc@48004000 { 1514 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1515 arm,primecell-periphid = <0x00253180>; 1516 reg = <0x48004000 0x400>; 1517 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&rcc SDMMC3_K>; 1519 clock-names = "apb_pclk"; 1520 resets = <&rcc SDMMC3_R>; 1521 cap-sd-highspeed; 1522 cap-mmc-highspeed; 1523 max-frequency = <120000000>; 1524 access-controllers = <&etzpc 86>; 1525 status = "disabled"; 1526 }; 1527 1528 usbotg_hs: usb-otg@49000000 { 1529 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1530 reg = <0x49000000 0x10000>; 1531 clocks = <&rcc USBO_K>, <&usbphyc>; 1532 clock-names = "otg", "utmi"; 1533 resets = <&rcc USBO_R>; 1534 reset-names = "dwc2"; 1535 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1536 g-rx-fifo-size = <512>; 1537 g-np-tx-fifo-size = <32>; 1538 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1539 dr_mode = "otg"; 1540 otg-rev = <0x200>; 1541 usb33d-supply = <&usb33>; 1542 access-controllers = <&etzpc 85>; 1543 status = "disabled"; 1544 }; 1545 1546 dcmi: dcmi@4c006000 { 1547 compatible = "st,stm32-dcmi"; 1548 reg = <0x4c006000 0x400>; 1549 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1550 resets = <&rcc CAMITF_R>; 1551 clocks = <&rcc DCMI>; 1552 clock-names = "mclk"; 1553 dmas = <&dmamux1 75 0x400 0x01>; 1554 dma-names = "tx"; 1555 access-controllers = <&etzpc 70>; 1556 status = "disabled"; 1557 }; 1558 1559 lptimer2: timer@50021000 { 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 compatible = "st,stm32-lptimer"; 1563 reg = <0x50021000 0x400>; 1564 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&rcc LPTIM2_K>; 1566 clock-names = "mux"; 1567 wakeup-source; 1568 access-controllers = <&etzpc 64>; 1569 status = "disabled"; 1570 1571 pwm { 1572 compatible = "st,stm32-pwm-lp"; 1573 #pwm-cells = <3>; 1574 status = "disabled"; 1575 }; 1576 1577 trigger@1 { 1578 compatible = "st,stm32-lptimer-trigger"; 1579 reg = <1>; 1580 status = "disabled"; 1581 }; 1582 1583 counter { 1584 compatible = "st,stm32-lptimer-counter"; 1585 status = "disabled"; 1586 }; 1587 }; 1588 1589 lptimer3: timer@50022000 { 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 compatible = "st,stm32-lptimer"; 1593 reg = <0x50022000 0x400>; 1594 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&rcc LPTIM3_K>; 1596 clock-names = "mux"; 1597 wakeup-source; 1598 access-controllers = <&etzpc 65>; 1599 status = "disabled"; 1600 1601 pwm { 1602 compatible = "st,stm32-pwm-lp"; 1603 #pwm-cells = <3>; 1604 status = "disabled"; 1605 }; 1606 1607 trigger@2 { 1608 compatible = "st,stm32-lptimer-trigger"; 1609 reg = <2>; 1610 status = "disabled"; 1611 }; 1612 }; 1613 1614 lptimer4: timer@50023000 { 1615 compatible = "st,stm32-lptimer"; 1616 reg = <0x50023000 0x400>; 1617 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&rcc LPTIM4_K>; 1619 clock-names = "mux"; 1620 wakeup-source; 1621 access-controllers = <&etzpc 66>; 1622 status = "disabled"; 1623 1624 pwm { 1625 compatible = "st,stm32-pwm-lp"; 1626 #pwm-cells = <3>; 1627 status = "disabled"; 1628 }; 1629 }; 1630 1631 lptimer5: timer@50024000 { 1632 compatible = "st,stm32-lptimer"; 1633 reg = <0x50024000 0x400>; 1634 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&rcc LPTIM5_K>; 1636 clock-names = "mux"; 1637 wakeup-source; 1638 access-controllers = <&etzpc 67>; 1639 status = "disabled"; 1640 1641 pwm { 1642 compatible = "st,stm32-pwm-lp"; 1643 #pwm-cells = <3>; 1644 status = "disabled"; 1645 }; 1646 }; 1647 1648 vrefbuf: vrefbuf@50025000 { 1649 compatible = "st,stm32-vrefbuf"; 1650 reg = <0x50025000 0x8>; 1651 regulator-min-microvolt = <1500000>; 1652 regulator-max-microvolt = <2500000>; 1653 clocks = <&rcc VREF>; 1654 access-controllers = <&etzpc 69>; 1655 status = "disabled"; 1656 }; 1657 1658 sai4: sai@50027000 { 1659 compatible = "st,stm32h7-sai"; 1660 #address-cells = <1>; 1661 #size-cells = <1>; 1662 ranges = <0 0x50027000 0x400>; 1663 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1664 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1665 resets = <&rcc SAI4_R>; 1666 access-controllers = <&etzpc 68>; 1667 status = "disabled"; 1668 1669 sai4a: audio-controller@50027004 { 1670 #sound-dai-cells = <0>; 1671 compatible = "st,stm32-sai-sub-a"; 1672 reg = <0x04 0x20>; 1673 clocks = <&rcc SAI4_K>; 1674 clock-names = "sai_ck"; 1675 dmas = <&dmamux1 99 0x400 0x01>; 1676 status = "disabled"; 1677 }; 1678 1679 sai4b: audio-controller@50027024 { 1680 #sound-dai-cells = <0>; 1681 compatible = "st,stm32-sai-sub-b"; 1682 reg = <0x24 0x20>; 1683 clocks = <&rcc SAI4_K>; 1684 clock-names = "sai_ck"; 1685 dmas = <&dmamux1 100 0x400 0x01>; 1686 status = "disabled"; 1687 }; 1688 }; 1689 1690 hash1: hash@54002000 { 1691 compatible = "st,stm32f756-hash"; 1692 reg = <0x54002000 0x400>; 1693 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&rcc HASH1>; 1695 resets = <&rcc HASH1_R>; 1696 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1697 dma-names = "in"; 1698 dma-maxburst = <2>; 1699 access-controllers = <&etzpc 8>; 1700 status = "disabled"; 1701 }; 1702 1703 rng1: rng@54003000 { 1704 compatible = "st,stm32-rng"; 1705 reg = <0x54003000 0x400>; 1706 clocks = <&rcc RNG1_K>; 1707 resets = <&rcc RNG1_R>; 1708 access-controllers = <&etzpc 7>; 1709 status = "disabled"; 1710 }; 1711 1712 fmc: memory-controller@58002000 { 1713 #address-cells = <2>; 1714 #size-cells = <1>; 1715 compatible = "st,stm32mp1-fmc2-ebi"; 1716 reg = <0x58002000 0x1000>; 1717 clocks = <&rcc FMC_K>; 1718 resets = <&rcc FMC_R>; 1719 access-controllers = <&etzpc 91>; 1720 status = "disabled"; 1721 1722 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1723 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1724 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1725 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1726 <4 0 0x80000000 0x10000000>; /* NAND */ 1727 1728 nand-controller@4,0 { 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 compatible = "st,stm32mp1-fmc2-nfc"; 1732 reg = <4 0x00000000 0x1000>, 1733 <4 0x08010000 0x1000>, 1734 <4 0x08020000 0x1000>, 1735 <4 0x01000000 0x1000>, 1736 <4 0x09010000 0x1000>, 1737 <4 0x09020000 0x1000>; 1738 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1739 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1740 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1741 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1742 dma-names = "tx", "rx", "ecc"; 1743 status = "disabled"; 1744 }; 1745 }; 1746 1747 qspi: spi@58003000 { 1748 compatible = "st,stm32f469-qspi"; 1749 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1750 reg-names = "qspi", "qspi_mm"; 1751 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1752 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1753 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1754 dma-names = "tx", "rx"; 1755 clocks = <&rcc QSPI_K>; 1756 resets = <&rcc QSPI_R>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 access-controllers = <&etzpc 92>; 1760 status = "disabled"; 1761 }; 1762 1763 ethernet0: ethernet@5800a000 { 1764 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1765 reg = <0x5800a000 0x2000>; 1766 reg-names = "stmmaceth"; 1767 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1768 interrupt-names = "macirq"; 1769 clock-names = "stmmaceth", 1770 "mac-clk-tx", 1771 "mac-clk-rx", 1772 "eth-ck", 1773 "ptp_ref", 1774 "ethstp"; 1775 clocks = <&rcc ETHMAC>, 1776 <&rcc ETHTX>, 1777 <&rcc ETHRX>, 1778 <&rcc ETHCK_K>, 1779 <&rcc ETHPTP_K>, 1780 <&rcc ETHSTP>; 1781 st,syscon = <&syscfg 0x4>; 1782 snps,mixed-burst; 1783 snps,pbl = <2>; 1784 snps,en-tx-lpi-clockgating; 1785 snps,axi-config = <&stmmac_axi_config_0>; 1786 snps,tso; 1787 access-controllers = <&etzpc 94>; 1788 status = "disabled"; 1789 1790 stmmac_axi_config_0: stmmac-axi-config { 1791 snps,wr_osr_lmt = <0x7>; 1792 snps,rd_osr_lmt = <0x7>; 1793 snps,blen = <0 0 0 0 16 8 4>; 1794 }; 1795 }; 1796 1797 usart1: serial@5c000000 { 1798 compatible = "st,stm32h7-uart"; 1799 reg = <0x5c000000 0x400>; 1800 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&rcc USART1_K>; 1802 wakeup-source; 1803 access-controllers = <&etzpc 3>; 1804 status = "disabled"; 1805 }; 1806 1807 spi6: spi@5c001000 { 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 compatible = "st,stm32h7-spi"; 1811 reg = <0x5c001000 0x400>; 1812 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1813 clocks = <&rcc SPI6_K>; 1814 resets = <&rcc SPI6_R>; 1815 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1816 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1817 access-controllers = <&etzpc 4>; 1818 dma-names = "rx", "tx"; 1819 status = "disabled"; 1820 }; 1821 1822 i2c4: i2c@5c002000 { 1823 compatible = "st,stm32mp15-i2c"; 1824 reg = <0x5c002000 0x400>; 1825 interrupt-names = "event", "error"; 1826 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1828 clocks = <&rcc I2C4_K>; 1829 resets = <&rcc I2C4_R>; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1833 wakeup-source; 1834 i2c-analog-filter; 1835 access-controllers = <&etzpc 5>; 1836 status = "disabled"; 1837 }; 1838 1839 i2c6: i2c@5c009000 { 1840 compatible = "st,stm32mp15-i2c"; 1841 reg = <0x5c009000 0x400>; 1842 interrupt-names = "event", "error"; 1843 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1845 clocks = <&rcc I2C6_K>; 1846 resets = <&rcc I2C6_R>; 1847 #address-cells = <1>; 1848 #size-cells = <0>; 1849 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1850 wakeup-source; 1851 i2c-analog-filter; 1852 access-controllers = <&etzpc 12>; 1853 status = "disabled"; 1854 }; 1855 }; 1856 1857 tamp: tamp@5c00a000 { 1858 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 1859 reg = <0x5c00a000 0x400>; 1860 }; 1861 1862 /* 1863 * Break node order to solve dependency probe issue between 1864 * pinctrl and exti. 1865 */ 1866 pinctrl: pinctrl@50002000 { 1867 #address-cells = <1>; 1868 #size-cells = <1>; 1869 compatible = "st,stm32mp157-pinctrl"; 1870 ranges = <0 0x50002000 0xa400>; 1871 interrupt-parent = <&exti>; 1872 st,syscfg = <&exti 0x60 0xff>; 1873 1874 gpioa: gpio@50002000 { 1875 gpio-controller; 1876 #gpio-cells = <2>; 1877 interrupt-controller; 1878 #interrupt-cells = <2>; 1879 reg = <0x0 0x400>; 1880 clocks = <&rcc GPIOA>; 1881 st,bank-name = "GPIOA"; 1882 status = "disabled"; 1883 }; 1884 1885 gpiob: gpio@50003000 { 1886 gpio-controller; 1887 #gpio-cells = <2>; 1888 interrupt-controller; 1889 #interrupt-cells = <2>; 1890 reg = <0x1000 0x400>; 1891 clocks = <&rcc GPIOB>; 1892 st,bank-name = "GPIOB"; 1893 status = "disabled"; 1894 }; 1895 1896 gpioc: gpio@50004000 { 1897 gpio-controller; 1898 #gpio-cells = <2>; 1899 interrupt-controller; 1900 #interrupt-cells = <2>; 1901 reg = <0x2000 0x400>; 1902 clocks = <&rcc GPIOC>; 1903 st,bank-name = "GPIOC"; 1904 status = "disabled"; 1905 }; 1906 1907 gpiod: gpio@50005000 { 1908 gpio-controller; 1909 #gpio-cells = <2>; 1910 interrupt-controller; 1911 #interrupt-cells = <2>; 1912 reg = <0x3000 0x400>; 1913 clocks = <&rcc GPIOD>; 1914 st,bank-name = "GPIOD"; 1915 status = "disabled"; 1916 }; 1917 1918 gpioe: gpio@50006000 { 1919 gpio-controller; 1920 #gpio-cells = <2>; 1921 interrupt-controller; 1922 #interrupt-cells = <2>; 1923 reg = <0x4000 0x400>; 1924 clocks = <&rcc GPIOE>; 1925 st,bank-name = "GPIOE"; 1926 status = "disabled"; 1927 }; 1928 1929 gpiof: gpio@50007000 { 1930 gpio-controller; 1931 #gpio-cells = <2>; 1932 interrupt-controller; 1933 #interrupt-cells = <2>; 1934 reg = <0x5000 0x400>; 1935 clocks = <&rcc GPIOF>; 1936 st,bank-name = "GPIOF"; 1937 status = "disabled"; 1938 }; 1939 1940 gpiog: gpio@50008000 { 1941 gpio-controller; 1942 #gpio-cells = <2>; 1943 interrupt-controller; 1944 #interrupt-cells = <2>; 1945 reg = <0x6000 0x400>; 1946 clocks = <&rcc GPIOG>; 1947 st,bank-name = "GPIOG"; 1948 status = "disabled"; 1949 }; 1950 1951 gpioh: gpio@50009000 { 1952 gpio-controller; 1953 #gpio-cells = <2>; 1954 interrupt-controller; 1955 #interrupt-cells = <2>; 1956 reg = <0x7000 0x400>; 1957 clocks = <&rcc GPIOH>; 1958 st,bank-name = "GPIOH"; 1959 status = "disabled"; 1960 }; 1961 1962 gpioi: gpio@5000a000 { 1963 gpio-controller; 1964 #gpio-cells = <2>; 1965 interrupt-controller; 1966 #interrupt-cells = <2>; 1967 reg = <0x8000 0x400>; 1968 clocks = <&rcc GPIOI>; 1969 st,bank-name = "GPIOI"; 1970 status = "disabled"; 1971 }; 1972 1973 gpioj: gpio@5000b000 { 1974 gpio-controller; 1975 #gpio-cells = <2>; 1976 interrupt-controller; 1977 #interrupt-cells = <2>; 1978 reg = <0x9000 0x400>; 1979 clocks = <&rcc GPIOJ>; 1980 st,bank-name = "GPIOJ"; 1981 status = "disabled"; 1982 }; 1983 1984 gpiok: gpio@5000c000 { 1985 gpio-controller; 1986 #gpio-cells = <2>; 1987 interrupt-controller; 1988 #interrupt-cells = <2>; 1989 reg = <0xa000 0x400>; 1990 clocks = <&rcc GPIOK>; 1991 st,bank-name = "GPIOK"; 1992 status = "disabled"; 1993 }; 1994 }; 1995 1996 pinctrl_z: pinctrl@54004000 { 1997 #address-cells = <1>; 1998 #size-cells = <1>; 1999 compatible = "st,stm32mp157-z-pinctrl"; 2000 ranges = <0 0x54004000 0x400>; 2001 interrupt-parent = <&exti>; 2002 st,syscfg = <&exti 0x60 0xff>; 2003 2004 gpioz: gpio@54004000 { 2005 gpio-controller; 2006 #gpio-cells = <2>; 2007 interrupt-controller; 2008 #interrupt-cells = <2>; 2009 reg = <0 0x400>; 2010 clocks = <&rcc GPIOZ>; 2011 st,bank-name = "GPIOZ"; 2012 st,bank-ioport = <11>; 2013 status = "disabled"; 2014 }; 2015 }; 2016 }; 2017 2018 mlahb: ahb { 2019 compatible = "st,mlahb", "simple-bus"; 2020 #address-cells = <1>; 2021 #size-cells = <1>; 2022 ranges; 2023 dma-ranges = <0x00000000 0x38000000 0x10000>, 2024 <0x10000000 0x10000000 0x60000>, 2025 <0x30000000 0x30000000 0x60000>; 2026 2027 m4_rproc: m4@10000000 { 2028 compatible = "st,stm32mp1-m4"; 2029 reg = <0x10000000 0x40000>, 2030 <0x30000000 0x40000>, 2031 <0x38000000 0x10000>; 2032 resets = <&rcc MCU_R>; 2033 reset-names = "mcu_rst"; 2034 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 2035 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 2036 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 2037 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 2038 status = "disabled"; 2039 }; 2040 }; 2041}; 2042