1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r7s72100 SoC 4 * 5 * Copyright (C) 2013-14 Renesas Solutions Corp. 6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <[email protected]> 7 */ 8 9#include <dt-bindings/clock/r7s72100-clock.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12 13/ { 14 compatible = "renesas,r7s72100"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 spi0 = &spi0; 24 spi1 = &spi1; 25 spi2 = &spi2; 26 spi3 = &spi3; 27 spi4 = &spi4; 28 }; 29 30 /* Fixed factor clocks */ 31 b_clk: b { 32 #clock-cells = <0>; 33 compatible = "fixed-factor-clock"; 34 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 35 clock-mult = <1>; 36 clock-div = <3>; 37 }; 38 39 bsc: bus { 40 compatible = "simple-bus"; 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0 0 0x18000000>; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a9"; 53 reg = <0>; 54 clock-frequency = <400000000>; 55 clocks = <&cpg_clocks R7S72100_CLK_I>; 56 next-level-cache = <&L2>; 57 }; 58 }; 59 60 /* External clocks */ 61 extal_clk: extal { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 /* If clk present, value must be set by board */ 65 clock-frequency = <0>; 66 }; 67 68 p0_clk: p0 { 69 #clock-cells = <0>; 70 compatible = "fixed-factor-clock"; 71 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 72 clock-mult = <1>; 73 clock-div = <12>; 74 }; 75 76 p1_clk: p1 { 77 #clock-cells = <0>; 78 compatible = "fixed-factor-clock"; 79 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 80 clock-mult = <1>; 81 clock-div = <6>; 82 }; 83 84 pmu { 85 compatible = "arm,cortex-a9-pmu"; 86 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; 87 }; 88 89 rtc_x1_clk: rtc_x1 { 90 #clock-cells = <0>; 91 compatible = "fixed-clock"; 92 /* If clk present, value must be set by board to 32678 */ 93 clock-frequency = <0>; 94 }; 95 96 rtc_x3_clk: rtc_x3 { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 /* If clk present, value must be set by board to 4000000 */ 100 clock-frequency = <0>; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 interrupt-parent = <&gic>; 106 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 L2: cache-controller@3ffff000 { 112 compatible = "arm,pl310-cache"; 113 reg = <0x3ffff000 0x1000>; 114 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 115 arm,early-bresp-disable; 116 arm,full-line-zero-disable; 117 cache-unified; 118 cache-level = <2>; 119 }; 120 121 scif0: serial@e8007000 { 122 compatible = "renesas,scif-r7s72100", "renesas,scif"; 123 reg = <0xe8007000 64>; 124 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 128 interrupt-names = "eri", "rxi", "txi", "bri"; 129 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; 130 clock-names = "fck"; 131 power-domains = <&cpg_clocks>; 132 status = "disabled"; 133 }; 134 135 scif1: serial@e8007800 { 136 compatible = "renesas,scif-r7s72100", "renesas,scif"; 137 reg = <0xe8007800 64>; 138 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "eri", "rxi", "txi", "bri"; 143 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; 144 clock-names = "fck"; 145 power-domains = <&cpg_clocks>; 146 status = "disabled"; 147 }; 148 149 scif2: serial@e8008000 { 150 compatible = "renesas,scif-r7s72100", "renesas,scif"; 151 reg = <0xe8008000 64>; 152 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "eri", "rxi", "txi", "bri"; 157 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; 158 clock-names = "fck"; 159 power-domains = <&cpg_clocks>; 160 status = "disabled"; 161 }; 162 163 scif3: serial@e8008800 { 164 compatible = "renesas,scif-r7s72100", "renesas,scif"; 165 reg = <0xe8008800 64>; 166 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-names = "eri", "rxi", "txi", "bri"; 171 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; 172 clock-names = "fck"; 173 power-domains = <&cpg_clocks>; 174 status = "disabled"; 175 }; 176 177 scif4: serial@e8009000 { 178 compatible = "renesas,scif-r7s72100", "renesas,scif"; 179 reg = <0xe8009000 64>; 180 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "eri", "rxi", "txi", "bri"; 185 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; 186 clock-names = "fck"; 187 power-domains = <&cpg_clocks>; 188 status = "disabled"; 189 }; 190 191 scif5: serial@e8009800 { 192 compatible = "renesas,scif-r7s72100", "renesas,scif"; 193 reg = <0xe8009800 64>; 194 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "eri", "rxi", "txi", "bri"; 199 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; 200 clock-names = "fck"; 201 power-domains = <&cpg_clocks>; 202 status = "disabled"; 203 }; 204 205 scif6: serial@e800a000 { 206 compatible = "renesas,scif-r7s72100", "renesas,scif"; 207 reg = <0xe800a000 64>; 208 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "eri", "rxi", "txi", "bri"; 213 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; 214 clock-names = "fck"; 215 power-domains = <&cpg_clocks>; 216 status = "disabled"; 217 }; 218 219 scif7: serial@e800a800 { 220 compatible = "renesas,scif-r7s72100", "renesas,scif"; 221 reg = <0xe800a800 64>; 222 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "eri", "rxi", "txi", "bri"; 227 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; 228 clock-names = "fck"; 229 power-domains = <&cpg_clocks>; 230 status = "disabled"; 231 }; 232 233 spi0: spi@e800c800 { 234 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 235 reg = <0xe800c800 0x24>; 236 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 239 interrupt-names = "error", "rx", "tx"; 240 clocks = <&mstp10_clks R7S72100_CLK_SPI0>; 241 dmas = <&dmac 0x2d21>, <&dmac 0x2d22>; 242 dma-names = "tx", "rx"; 243 power-domains = <&cpg_clocks>; 244 num-cs = <1>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 status = "disabled"; 248 }; 249 250 spi1: spi@e800d000 { 251 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 252 reg = <0xe800d000 0x24>; 253 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-names = "error", "rx", "tx"; 257 clocks = <&mstp10_clks R7S72100_CLK_SPI1>; 258 dmas = <&dmac 0x2d25>, <&dmac 0x2d26>; 259 dma-names = "tx", "rx"; 260 power-domains = <&cpg_clocks>; 261 num-cs = <1>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 status = "disabled"; 265 }; 266 267 spi2: spi@e800d800 { 268 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 269 reg = <0xe800d800 0x24>; 270 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "error", "rx", "tx"; 274 clocks = <&mstp10_clks R7S72100_CLK_SPI2>; 275 dmas = <&dmac 0x2d29>, <&dmac 0x2d2a>; 276 dma-names = "tx", "rx"; 277 power-domains = <&cpg_clocks>; 278 num-cs = <1>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 status = "disabled"; 282 }; 283 284 spi3: spi@e800e000 { 285 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 286 reg = <0xe800e000 0x24>; 287 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "error", "rx", "tx"; 291 clocks = <&mstp10_clks R7S72100_CLK_SPI3>; 292 dmas = <&dmac 0x2d2d>, <&dmac 0x2d2e>; 293 dma-names = "tx", "rx"; 294 power-domains = <&cpg_clocks>; 295 num-cs = <1>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 301 spi4: spi@e800e800 { 302 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 303 reg = <0xe800e800 0x24>; 304 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-names = "error", "rx", "tx"; 308 clocks = <&mstp10_clks R7S72100_CLK_SPI4>; 309 dmas = <&dmac 0x2d31>, <&dmac 0x2d32>; 310 dma-names = "tx", "rx"; 311 power-domains = <&cpg_clocks>; 312 num-cs = <1>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 318 usbhs0: usb@e8010000 { 319 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 320 reg = <0xe8010000 0x1a0>; 321 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&mstp7_clks R7S72100_CLK_USB0>; 323 renesas,buswait = <4>; 324 power-domains = <&cpg_clocks>; 325 status = "disabled"; 326 }; 327 328 usbhs1: usb@e8207000 { 329 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 330 reg = <0xe8207000 0x1a0>; 331 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&mstp7_clks R7S72100_CLK_USB1>; 333 renesas,buswait = <4>; 334 power-domains = <&cpg_clocks>; 335 status = "disabled"; 336 }; 337 338 mmcif: mmc@e804c800 { 339 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; 340 reg = <0xe804c800 0x80>; 341 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; 345 dmas = <&dmac 0x2cc9>, <&dmac 0x2cca>; 346 dma-names = "tx", "rx"; 347 power-domains = <&cpg_clocks>; 348 status = "disabled"; 349 }; 350 351 sdhi0: mmc@e804e000 { 352 compatible = "renesas,sdhi-r7s72100"; 353 reg = <0xe804e000 0x100>; 354 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 357 358 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, 359 <&mstp12_clks R7S72100_CLK_SDHI01>; 360 clock-names = "core", "cd"; 361 power-domains = <&cpg_clocks>; 362 cap-sd-highspeed; 363 cap-sdio-irq; 364 status = "disabled"; 365 }; 366 367 sdhi1: mmc@e804e800 { 368 compatible = "renesas,sdhi-r7s72100"; 369 reg = <0xe804e800 0x100>; 370 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 373 374 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, 375 <&mstp12_clks R7S72100_CLK_SDHI11>; 376 clock-names = "core", "cd"; 377 power-domains = <&cpg_clocks>; 378 cap-sd-highspeed; 379 cap-sdio-irq; 380 status = "disabled"; 381 }; 382 383 dmac: dma-controller@e8200000 { 384 compatible = "renesas,r7s72100-dmac", 385 "renesas,rz-dmac"; 386 reg = <0xe8200000 0x1000>, 387 <0xfcfe1000 0x20>; 388 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 393 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>, 394 <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>, 395 <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>, 396 <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>, 397 <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>, 398 <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>, 399 <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 400 <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, 401 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 402 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, 403 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 405 interrupt-names = "error", 406 "ch0", "ch1", "ch2", "ch3", 407 "ch4", "ch5", "ch6", "ch7", 408 "ch8", "ch9", "ch10", "ch11", 409 "ch12", "ch13", "ch14", "ch15"; 410 #dma-cells = <1>; 411 dma-channels = <16>; 412 }; 413 414 gic: interrupt-controller@e8201000 { 415 compatible = "arm,pl390"; 416 #interrupt-cells = <3>; 417 #address-cells = <0>; 418 interrupt-controller; 419 reg = <0xe8201000 0x1000>, 420 <0xe8202000 0x1000>; 421 }; 422 423 ether: ethernet@e8203000 { 424 compatible = "renesas,ether-r7s72100"; 425 reg = <0xe8203000 0x800>, 426 <0xe8204800 0x200>; 427 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&mstp7_clks R7S72100_CLK_ETHER>; 429 power-domains = <&cpg_clocks>; 430 phy-mode = "mii"; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 status = "disabled"; 434 }; 435 436 ceu: camera@e8210000 { 437 reg = <0xe8210000 0x3000>; 438 compatible = "renesas,r7s72100-ceu"; 439 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&mstp6_clks R7S72100_CLK_CEU>; 441 power-domains = <&cpg_clocks>; 442 status = "disabled"; 443 }; 444 445 wdt: watchdog@fcfe0000 { 446 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; 447 reg = <0xfcfe0000 0x6>; 448 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&p0_clk>; 450 }; 451 452 /* Special CPG clocks */ 453 cpg_clocks: cpg_clocks@fcfe0000 { 454 #clock-cells = <1>; 455 compatible = "renesas,r7s72100-cpg-clocks", 456 "renesas,rz-cpg-clocks"; 457 reg = <0xfcfe0000 0x18>; 458 clocks = <&extal_clk>, <&usb_x1_clk>; 459 clock-output-names = "pll", "i", "g"; 460 #power-domain-cells = <0>; 461 }; 462 463 /* MSTP clocks */ 464 mstp3_clks: mstp3_clks@fcfe0420 { 465 #clock-cells = <1>; 466 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 467 reg = <0xfcfe0420 4>; 468 clocks = <&p0_clk>; 469 clock-indices = <R7S72100_CLK_MTU2>; 470 clock-output-names = "mtu2"; 471 }; 472 473 mstp4_clks: mstp4_clks@fcfe0424 { 474 #clock-cells = <1>; 475 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 476 reg = <0xfcfe0424 4>; 477 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 478 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 479 clock-indices = < 480 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 481 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 482 >; 483 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; 484 }; 485 486 mstp5_clks: mstp5_clks@fcfe0428 { 487 #clock-cells = <1>; 488 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 489 reg = <0xfcfe0428 4>; 490 clocks = <&p0_clk>, <&p0_clk>; 491 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; 492 clock-output-names = "ostm0", "ostm1"; 493 }; 494 495 mstp6_clks: mstp6_clks@fcfe042c { 496 #clock-cells = <1>; 497 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 498 reg = <0xfcfe042c 4>; 499 clocks = <&b_clk>, <&p0_clk>; 500 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>; 501 clock-output-names = "ceu", "rtc"; 502 }; 503 504 mstp7_clks: mstp7_clks@fcfe0430 { 505 #clock-cells = <1>; 506 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 507 reg = <0xfcfe0430 4>; 508 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; 509 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>; 510 clock-output-names = "ether", "usb0", "usb1"; 511 }; 512 513 mstp8_clks: mstp8_clks@fcfe0434 { 514 #clock-cells = <1>; 515 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 516 reg = <0xfcfe0434 4>; 517 clocks = <&p1_clk>; 518 clock-indices = <R7S72100_CLK_MMCIF>; 519 clock-output-names = "mmcif"; 520 }; 521 522 mstp9_clks: mstp9_clks@fcfe0438 { 523 #clock-cells = <1>; 524 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 525 reg = <0xfcfe0438 4>; 526 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; 527 clock-indices = < 528 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 529 R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 530 >; 531 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; 532 }; 533 534 mstp10_clks: mstp10_clks@fcfe043c { 535 #clock-cells = <1>; 536 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 537 reg = <0xfcfe043c 4>; 538 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 539 <&p1_clk>; 540 clock-indices = < 541 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 542 R7S72100_CLK_SPI4 543 >; 544 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; 545 }; 546 mstp12_clks: mstp12_clks@fcfe0444 { 547 #clock-cells = <1>; 548 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 549 reg = <0xfcfe0444 4>; 550 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 551 clock-indices = < 552 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 553 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 554 >; 555 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; 556 }; 557 558 pinctrl: pinctrl@fcfe3000 { 559 compatible = "renesas,r7s72100-ports"; 560 561 reg = <0xfcfe3000 0x4230>; 562 563 port0: gpio-0 { 564 gpio-controller; 565 #gpio-cells = <2>; 566 gpio-ranges = <&pinctrl 0 0 6>; 567 }; 568 569 port1: gpio-1 { 570 gpio-controller; 571 #gpio-cells = <2>; 572 gpio-ranges = <&pinctrl 0 16 16>; 573 }; 574 575 port2: gpio-2 { 576 gpio-controller; 577 #gpio-cells = <2>; 578 gpio-ranges = <&pinctrl 0 32 16>; 579 }; 580 581 port3: gpio-3 { 582 gpio-controller; 583 #gpio-cells = <2>; 584 gpio-ranges = <&pinctrl 0 48 16>; 585 }; 586 587 port4: gpio-4 { 588 gpio-controller; 589 #gpio-cells = <2>; 590 gpio-ranges = <&pinctrl 0 64 16>; 591 }; 592 593 port5: gpio-5 { 594 gpio-controller; 595 #gpio-cells = <2>; 596 gpio-ranges = <&pinctrl 0 80 11>; 597 }; 598 599 port6: gpio-6 { 600 gpio-controller; 601 #gpio-cells = <2>; 602 gpio-ranges = <&pinctrl 0 96 16>; 603 }; 604 605 port7: gpio-7 { 606 gpio-controller; 607 #gpio-cells = <2>; 608 gpio-ranges = <&pinctrl 0 112 16>; 609 }; 610 611 port8: gpio-8 { 612 gpio-controller; 613 #gpio-cells = <2>; 614 gpio-ranges = <&pinctrl 0 128 16>; 615 }; 616 617 port9: gpio-9 { 618 gpio-controller; 619 #gpio-cells = <2>; 620 gpio-ranges = <&pinctrl 0 144 8>; 621 }; 622 623 port10: gpio-10 { 624 gpio-controller; 625 #gpio-cells = <2>; 626 gpio-ranges = <&pinctrl 0 160 16>; 627 }; 628 629 port11: gpio-11 { 630 gpio-controller; 631 #gpio-cells = <2>; 632 gpio-ranges = <&pinctrl 0 176 16>; 633 }; 634 }; 635 636 ostm0: timer@fcfec000 { 637 compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 638 reg = <0xfcfec000 0x30>; 639 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; 640 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; 641 power-domains = <&cpg_clocks>; 642 status = "disabled"; 643 }; 644 645 ostm1: timer@fcfec400 { 646 compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 647 reg = <0xfcfec400 0x30>; 648 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; 649 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; 650 power-domains = <&cpg_clocks>; 651 status = "disabled"; 652 }; 653 654 i2c0: i2c@fcfee000 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 658 reg = <0xfcfee000 0x44>; 659 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 661 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, 662 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "tei", "ri", "ti", "spi", "sti", 668 "naki", "ali", "tmoi"; 669 clocks = <&mstp9_clks R7S72100_CLK_I2C0>; 670 clock-frequency = <100000>; 671 power-domains = <&cpg_clocks>; 672 status = "disabled"; 673 }; 674 675 i2c1: i2c@fcfee400 { 676 #address-cells = <1>; 677 #size-cells = <0>; 678 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 679 reg = <0xfcfee400 0x44>; 680 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, 682 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, 683 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-names = "tei", "ri", "ti", "spi", "sti", 689 "naki", "ali", "tmoi"; 690 clocks = <&mstp9_clks R7S72100_CLK_I2C1>; 691 clock-frequency = <100000>; 692 power-domains = <&cpg_clocks>; 693 status = "disabled"; 694 }; 695 696 i2c2: i2c@fcfee800 { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 700 reg = <0xfcfee800 0x44>; 701 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, 703 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, 704 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 709 interrupt-names = "tei", "ri", "ti", "spi", "sti", 710 "naki", "ali", "tmoi"; 711 clocks = <&mstp9_clks R7S72100_CLK_I2C2>; 712 clock-frequency = <100000>; 713 power-domains = <&cpg_clocks>; 714 status = "disabled"; 715 }; 716 717 i2c3: i2c@fcfeec00 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 721 reg = <0xfcfeec00 0x44>; 722 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, 724 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, 725 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 730 interrupt-names = "tei", "ri", "ti", "spi", "sti", 731 "naki", "ali", "tmoi"; 732 clocks = <&mstp9_clks R7S72100_CLK_I2C3>; 733 clock-frequency = <100000>; 734 power-domains = <&cpg_clocks>; 735 status = "disabled"; 736 }; 737 738 irqc: interrupt-controller@fcfef800 { 739 compatible = "renesas,r7s72100-irqc", 740 "renesas,rza1-irqc"; 741 #interrupt-cells = <2>; 742 #address-cells = <0>; 743 interrupt-controller; 744 reg = <0xfcfef800 0x6>; 745 interrupt-map = 746 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 747 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 748 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 749 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 750 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 751 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 752 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 753 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-map-mask = <7 0>; 755 }; 756 757 mtu2: timer@fcff0000 { 758 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; 759 reg = <0xfcff0000 0x400>; 760 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "tgi0a"; 762 clocks = <&mstp3_clks R7S72100_CLK_MTU2>; 763 clock-names = "fck"; 764 power-domains = <&cpg_clocks>; 765 status = "disabled"; 766 }; 767 768 rtc: rtc@fcff1000 { 769 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; 770 reg = <0xfcff1000 0x2e>; 771 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 774 interrupt-names = "alarm", "period", "carry"; 775 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, 776 <&rtc_x3_clk>, <&extal_clk>; 777 clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; 778 power-domains = <&cpg_clocks>; 779 status = "disabled"; 780 }; 781 }; 782 783 usb_x1_clk: usb_x1 { 784 #clock-cells = <0>; 785 compatible = "fixed-clock"; 786 /* If clk present, value must be set by board */ 787 clock-frequency = <0>; 788 }; 789}; 790