1// SPDX-License-Identifier: (GPL-2.0+ OR X11) 2/* 3 * Copyright 2018 Icenowy Zheng <[email protected]> 4 * Copyright 2018 Mesih Kilinc <[email protected]> 5 */ 6 7#include <dt-bindings/clock/suniv-ccu-f1c100s.h> 8#include <dt-bindings/reset/suniv-ccu-f1c100s.h> 9#include <dt-bindings/dma/sun4i-a10.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 interrupt-parent = <&intc>; 15 16 clocks { 17 osc24M: clk-24M { 18 #clock-cells = <0>; 19 compatible = "fixed-clock"; 20 clock-frequency = <24000000>; 21 clock-output-names = "osc24M"; 22 }; 23 24 osc32k: clk-32k { 25 #clock-cells = <0>; 26 compatible = "fixed-clock"; 27 clock-frequency = <32768>; 28 clock-output-names = "osc32k"; 29 }; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 compatible = "arm,arm926ej-s"; 38 device_type = "cpu"; 39 reg = <0x0>; 40 }; 41 }; 42 43 soc { 44 compatible = "simple-bus"; 45 #address-cells = <1>; 46 #size-cells = <1>; 47 ranges; 48 49 sram-controller@1c00000 { 50 compatible = "allwinner,suniv-f1c100s-system-control", 51 "allwinner,sun4i-a10-system-control"; 52 reg = <0x01c00000 0x30>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 57 sram_d: sram@10000 { 58 compatible = "mmio-sram"; 59 reg = <0x00010000 0x1000>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges = <0 0x00010000 0x1000>; 63 64 otg_sram: sram-section@0 { 65 compatible = "allwinner,suniv-f1c100s-sram-d", 66 "allwinner,sun4i-a10-sram-d"; 67 reg = <0x0000 0x1000>; 68 status = "disabled"; 69 }; 70 }; 71 }; 72 73 spi0: spi@1c05000 { 74 compatible = "allwinner,suniv-f1c100s-spi", 75 "allwinner,sun8i-h3-spi"; 76 reg = <0x01c05000 0x1000>; 77 interrupts = <10>; 78 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; 79 clock-names = "ahb", "mod"; 80 resets = <&ccu RST_BUS_SPI0>; 81 status = "disabled"; 82 num-cs = <1>; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 }; 86 87 spi1: spi@1c06000 { 88 compatible = "allwinner,suniv-f1c100s-spi", 89 "allwinner,sun8i-h3-spi"; 90 reg = <0x01c06000 0x1000>; 91 interrupts = <11>; 92 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; 93 clock-names = "ahb", "mod"; 94 resets = <&ccu RST_BUS_SPI1>; 95 status = "disabled"; 96 num-cs = <1>; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 }; 100 101 mmc0: mmc@1c0f000 { 102 compatible = "allwinner,suniv-f1c100s-mmc", 103 "allwinner,sun7i-a20-mmc"; 104 reg = <0x01c0f000 0x1000>; 105 clocks = <&ccu CLK_BUS_MMC0>, 106 <&ccu CLK_MMC0>, 107 <&ccu CLK_MMC0_OUTPUT>, 108 <&ccu CLK_MMC0_SAMPLE>; 109 clock-names = "ahb", "mmc", "output", "sample"; 110 resets = <&ccu RST_BUS_MMC0>; 111 reset-names = "ahb"; 112 interrupts = <23>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&mmc0_pins>; 115 status = "disabled"; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 }; 119 120 mmc1: mmc@1c10000 { 121 compatible = "allwinner,suniv-f1c100s-mmc", 122 "allwinner,sun7i-a20-mmc"; 123 reg = <0x01c10000 0x1000>; 124 clocks = <&ccu CLK_BUS_MMC1>, 125 <&ccu CLK_MMC1>, 126 <&ccu CLK_MMC1_OUTPUT>, 127 <&ccu CLK_MMC1_SAMPLE>; 128 clock-names = "ahb", "mmc", "output", "sample"; 129 resets = <&ccu RST_BUS_MMC1>; 130 reset-names = "ahb"; 131 interrupts = <24>; 132 status = "disabled"; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 }; 136 137 usb_otg: usb@1c13000 { 138 compatible = "allwinner,suniv-f1c100s-musb"; 139 reg = <0x01c13000 0x0400>; 140 clocks = <&ccu CLK_BUS_OTG>; 141 resets = <&ccu RST_BUS_OTG>; 142 interrupts = <26>; 143 interrupt-names = "mc"; 144 phys = <&usbphy 0>; 145 phy-names = "usb"; 146 extcon = <&usbphy 0>; 147 allwinner,sram = <&otg_sram 1>; 148 status = "disabled"; 149 }; 150 151 usbphy: phy@1c13400 { 152 compatible = "allwinner,suniv-f1c100s-usb-phy"; 153 reg = <0x01c13400 0x10>; 154 reg-names = "phy_ctrl"; 155 clocks = <&ccu CLK_USB_PHY0>; 156 clock-names = "usb0_phy"; 157 resets = <&ccu RST_USB_PHY0>; 158 reset-names = "usb0_reset"; 159 #phy-cells = <1>; 160 status = "disabled"; 161 }; 162 163 dma: dma-controller@1c02000 { 164 compatible = "allwinner,suniv-f1c100s-dma"; 165 reg = <0x01c02000 0x1000>; 166 interrupts = <18>; 167 clocks = <&ccu CLK_BUS_DMA>; 168 resets = <&ccu RST_BUS_DMA>; 169 #dma-cells = <2>; 170 }; 171 172 ccu: clock@1c20000 { 173 compatible = "allwinner,suniv-f1c100s-ccu"; 174 reg = <0x01c20000 0x400>; 175 clocks = <&osc24M>, <&osc32k>; 176 clock-names = "hosc", "losc"; 177 #clock-cells = <1>; 178 #reset-cells = <1>; 179 }; 180 181 intc: interrupt-controller@1c20400 { 182 compatible = "allwinner,suniv-f1c100s-ic"; 183 reg = <0x01c20400 0x400>; 184 interrupt-controller; 185 #interrupt-cells = <1>; 186 }; 187 188 pio: pinctrl@1c20800 { 189 compatible = "allwinner,suniv-f1c100s-pinctrl"; 190 reg = <0x01c20800 0x400>; 191 interrupts = <38>, <39>, <40>; 192 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 193 clock-names = "apb", "hosc", "losc"; 194 gpio-controller; 195 interrupt-controller; 196 #interrupt-cells = <3>; 197 #gpio-cells = <3>; 198 199 mmc0_pins: mmc0-pins { 200 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 201 function = "mmc0"; 202 drive-strength = <30>; 203 }; 204 205 /omit-if-no-ref/ 206 i2c0_pd_pins: i2c0-pd-pins { 207 pins = "PD0", "PD12"; 208 function = "i2c0"; 209 }; 210 211 spi0_pc_pins: spi0-pc-pins { 212 pins = "PC0", "PC1", "PC2", "PC3"; 213 function = "spi0"; 214 }; 215 216 uart0_pe_pins: uart0-pe-pins { 217 pins = "PE0", "PE1"; 218 function = "uart0"; 219 }; 220 221 /omit-if-no-ref/ 222 uart1_pa_pins: uart1-pa-pins { 223 pins = "PA2", "PA3"; 224 function = "uart1"; 225 }; 226 }; 227 228 i2c0: i2c@1c27000 { 229 compatible = "allwinner,suniv-f1c100s-i2c", 230 "allwinner,sun6i-a31-i2c"; 231 reg = <0x01c27000 0x400>; 232 interrupts = <7>; 233 clocks = <&ccu CLK_BUS_I2C0>; 234 resets = <&ccu RST_BUS_I2C0>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 status = "disabled"; 238 }; 239 240 i2c1: i2c@1c27400 { 241 compatible = "allwinner,suniv-f1c100s-i2c", 242 "allwinner,sun6i-a31-i2c"; 243 reg = <0x01c27400 0x400>; 244 interrupts = <8>; 245 clocks = <&ccu CLK_BUS_I2C1>; 246 resets = <&ccu RST_BUS_I2C1>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 status = "disabled"; 250 }; 251 252 i2c2: i2c@1c27800 { 253 compatible = "allwinner,suniv-f1c100s-i2c", 254 "allwinner,sun6i-a31-i2c"; 255 reg = <0x01c27800 0x400>; 256 interrupts = <9>; 257 clocks = <&ccu CLK_BUS_I2C2>; 258 resets = <&ccu RST_BUS_I2C2>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 status = "disabled"; 262 }; 263 264 timer@1c20c00 { 265 compatible = "allwinner,suniv-f1c100s-timer"; 266 reg = <0x01c20c00 0x90>; 267 interrupts = <13>, <14>, <15>; 268 clocks = <&osc24M>; 269 }; 270 271 wdt: watchdog@1c20ca0 { 272 compatible = "allwinner,suniv-f1c100s-wdt", 273 "allwinner,sun6i-a31-wdt"; 274 reg = <0x01c20ca0 0x20>; 275 interrupts = <16>; 276 clocks = <&osc32k>; 277 }; 278 279 pwm: pwm@1c21000 { 280 compatible = "allwinner,suniv-f1c100s-pwm", 281 "allwinner,sun7i-a20-pwm"; 282 reg = <0x01c21000 0x400>; 283 clocks = <&osc24M>; 284 #pwm-cells = <3>; 285 status = "disabled"; 286 }; 287 288 ir: ir@1c22c00 { 289 compatible = "allwinner,suniv-f1c100s-ir", 290 "allwinner,sun6i-a31-ir"; 291 reg = <0x01c22c00 0x400>; 292 clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; 293 clock-names = "apb", "ir"; 294 resets = <&ccu RST_BUS_IR>; 295 interrupts = <6>; 296 status = "disabled"; 297 }; 298 299 lradc: lradc@1c23400 { 300 compatible = "allwinner,suniv-f1c100s-lradc", 301 "allwinner,sun8i-a83t-r-lradc"; 302 reg = <0x01c23400 0x400>; 303 interrupts = <22>; 304 status = "disabled"; 305 }; 306 307 uart0: serial@1c25000 { 308 compatible = "snps,dw-apb-uart"; 309 reg = <0x01c25000 0x400>; 310 interrupts = <1>; 311 reg-shift = <2>; 312 reg-io-width = <4>; 313 clocks = <&ccu CLK_BUS_UART0>; 314 resets = <&ccu RST_BUS_UART0>; 315 status = "disabled"; 316 }; 317 318 uart1: serial@1c25400 { 319 compatible = "snps,dw-apb-uart"; 320 reg = <0x01c25400 0x400>; 321 interrupts = <2>; 322 reg-shift = <2>; 323 reg-io-width = <4>; 324 clocks = <&ccu CLK_BUS_UART1>; 325 resets = <&ccu RST_BUS_UART1>; 326 status = "disabled"; 327 }; 328 329 uart2: serial@1c25800 { 330 compatible = "snps,dw-apb-uart"; 331 reg = <0x01c25800 0x400>; 332 interrupts = <3>; 333 reg-shift = <2>; 334 reg-io-width = <4>; 335 clocks = <&ccu CLK_BUS_UART2>; 336 resets = <&ccu RST_BUS_UART2>; 337 status = "disabled"; 338 }; 339 340 codec: codec@1c23c00 { 341 #sound-dai-cells = <0>; 342 compatible = "allwinner,suniv-f1c100s-codec"; 343 reg = <0x01c23c00 0x400>; 344 interrupts = <21>; 345 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>; 346 clock-names = "apb", "codec"; 347 dmas = <&dma SUN4I_DMA_NORMAL 12>, 348 <&dma SUN4I_DMA_NORMAL 12>; 349 dma-names = "rx", "tx"; 350 resets = <&ccu RST_BUS_CODEC>; 351 status = "disabled"; 352 }; 353 }; 354}; 355