1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Header file for UHS-II packets, Host Controller registers and I/O 4 * accessors. 5 * 6 * Copyright (C) 2014 Intel Corp, All Rights Reserved. 7 */ 8 #ifndef LINUX_MMC_UHS2_H 9 #define LINUX_MMC_UHS2_H 10 11 /* LINK Layer definition */ 12 /* 13 * UHS2 Header: 14 * Refer to UHS-II Addendum Version 1.02 Figure 5-2, the format of CCMD Header is described below: 15 * bit [3:0] : DID(Destination ID = Node ID of UHS2 card) 16 * bit [6:4] : TYP(Packet Type) 17 * 000b: CCMD(Control command packet) 18 * 001b: DCMD(Data command packet) 19 * 010b: RES(Response packet) 20 * 011b: DATA(Data payload packet) 21 * 111b: MSG(Message packet) 22 * Others: Reserved 23 * bit [7] : NP(Native Packet) 24 * bit [10:8] : TID(Transaction ID) 25 * bit [11] : Reserved 26 * bit [15:12]: SID(Source ID 0: Node ID of Host) 27 * 28 * Broadcast CCMD issued by Host is represented as DID=SID=0. 29 */ 30 /* 31 * UHS2 Argument: 32 * Refer to UHS-II Addendum Version 1.02 Figure 6-5, the format of CCMD Argument is described below: 33 * bit [3:0] : MSB of IOADR 34 * bit [5:4] : PLEN(Payload Length) 35 * 00b: 0 byte 36 * 01b: 4 bytes 37 * 10b: 8 bytes 38 * 11b: 16 bytes 39 * bit [6] : Reserved 40 * bit [7] : R/W(Read/Write) 41 * 0: Control read command 42 * 1: Control write command 43 * bit [15:8] : LSB of IOADR 44 * 45 * I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD. 46 * The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last. 47 */ 48 #define UHS2_NATIVE_PACKET_POS 7 49 #define UHS2_NATIVE_PACKET (1 << UHS2_NATIVE_PACKET_POS) 50 51 #define UHS2_PACKET_TYPE_POS 4 52 #define UHS2_PACKET_TYPE_CCMD (0 << UHS2_PACKET_TYPE_POS) 53 #define UHS2_PACKET_TYPE_DCMD (1 << UHS2_PACKET_TYPE_POS) 54 #define UHS2_PACKET_TYPE_RES (2 << UHS2_PACKET_TYPE_POS) 55 #define UHS2_PACKET_TYPE_DATA (3 << UHS2_PACKET_TYPE_POS) 56 #define UHS2_PACKET_TYPE_MSG (7 << UHS2_PACKET_TYPE_POS) 57 58 #define UHS2_DEST_ID_MASK 0x0F 59 #define UHS2_DEST_ID 0x1 60 61 #define UHS2_SRC_ID_POS 12 62 #define UHS2_SRC_ID_MASK 0xF000 63 64 #define UHS2_TRANS_ID_POS 8 65 #define UHS2_TRANS_ID_MASK 0x0700 66 67 /* UHS2 MSG */ 68 #define UHS2_MSG_CTG_POS 5 69 #define UHS2_MSG_CTG_LMSG 0x00 70 #define UHS2_MSG_CTG_INT 0x60 71 #define UHS2_MSG_CTG_AMSG 0x80 72 73 #define UHS2_MSG_CTG_FCREQ 0x00 74 #define UHS2_MSG_CTG_FCRDY 0x01 75 #define UHS2_MSG_CTG_STAT 0x02 76 77 #define UHS2_MSG_CODE_POS 8 78 #define UHS2_MSG_CODE_FC_UNRECOVER_ERR 0x8 79 #define UHS2_MSG_CODE_STAT_UNRECOVER_ERR 0x8 80 #define UHS2_MSG_CODE_STAT_RECOVER_ERR 0x1 81 82 /* TRANS Layer definition */ 83 84 /* Native packets*/ 85 #define UHS2_NATIVE_CMD_RW_POS 7 86 #define UHS2_NATIVE_CMD_WRITE (1 << UHS2_NATIVE_CMD_RW_POS) 87 #define UHS2_NATIVE_CMD_READ (0 << UHS2_NATIVE_CMD_RW_POS) 88 89 #define UHS2_NATIVE_CMD_PLEN_POS 4 90 #define UHS2_NATIVE_CMD_PLEN_4B (1 << UHS2_NATIVE_CMD_PLEN_POS) 91 #define UHS2_NATIVE_CMD_PLEN_8B (2 << UHS2_NATIVE_CMD_PLEN_POS) 92 #define UHS2_NATIVE_CMD_PLEN_16B (3 << UHS2_NATIVE_CMD_PLEN_POS) 93 94 #define UHS2_NATIVE_CCMD_GET_MIOADR_MASK 0xF00 95 #define UHS2_NATIVE_CCMD_MIOADR_MASK 0x0F 96 97 #define UHS2_NATIVE_CCMD_LIOADR_POS 8 98 #define UHS2_NATIVE_CCMD_GET_LIOADR_MASK 0x0FF 99 100 #define UHS2_CCMD_DEV_INIT_COMPLETE_FLAG BIT(11) 101 #define UHS2_DEV_INIT_PAYLOAD_LEN 1 102 #define UHS2_DEV_INIT_RESP_LEN 6 103 #define UHS2_DEV_ENUM_PAYLOAD_LEN 1 104 #define UHS2_DEV_ENUM_RESP_LEN 8 105 #define UHS2_CFG_WRITE_PAYLOAD_LEN 2 106 #define UHS2_CFG_WRITE_PHY_SET_RESP_LEN 4 107 #define UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN 5 108 #define UHS2_GO_DORMANT_PAYLOAD_LEN 1 109 110 /* 111 * UHS2 Argument: 112 * Refer to UHS-II Addendum Version 1.02 Figure 6-8, the format of DCMD Argument is described below: 113 * bit [3:0] : Reserved 114 * bit [6:3] : TMODE(Transfer Mode) 115 * bit 3: DAM(Data Access Mode) 116 * bit 4: TLUM(TLEN Unit Mode) 117 * bit 5: LM(Length Mode) 118 * bit 6: DM(Duplex Mode) 119 * bit [7] : R/W(Read/Write) 120 * 0: Control read command 121 * 1: Control write command 122 * bit [15:8] : Reserved 123 * 124 * I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD. 125 * The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last. 126 */ 127 #define UHS2_DCMD_DM_POS 6 128 #define UHS2_DCMD_2L_HD_MODE (1 << UHS2_DCMD_DM_POS) 129 #define UHS2_DCMD_LM_POS 5 130 #define UHS2_DCMD_LM_TLEN_EXIST (1 << UHS2_DCMD_LM_POS) 131 #define UHS2_DCMD_TLUM_POS 4 132 #define UHS2_DCMD_TLUM_BYTE_MODE (1 << UHS2_DCMD_TLUM_POS) 133 #define UHS2_NATIVE_DCMD_DAM_POS 3 134 #define UHS2_NATIVE_DCMD_DAM_IO (1 << UHS2_NATIVE_DCMD_DAM_POS) 135 136 #define UHS2_RES_NACK_POS 7 137 #define UHS2_RES_NACK_MASK (0x1 << UHS2_RES_NACK_POS) 138 139 #define UHS2_RES_ECODE_POS 4 140 #define UHS2_RES_ECODE_MASK 0x7 141 #define UHS2_RES_ECODE_COND 1 142 #define UHS2_RES_ECODE_ARG 2 143 #define UHS2_RES_ECODE_GEN 3 144 145 /* IOADR of device registers */ 146 #define UHS2_IOADR_GENERIC_CAPS 0x00 147 #define UHS2_IOADR_PHY_CAPS 0x02 148 #define UHS2_IOADR_LINK_CAPS 0x04 149 #define UHS2_IOADR_RSV_CAPS 0x06 150 #define UHS2_IOADR_GENERIC_SETTINGS 0x08 151 #define UHS2_IOADR_PHY_SETTINGS 0x0A 152 #define UHS2_IOADR_LINK_SETTINGS 0x0C 153 #define UHS2_IOADR_PRESET 0x40 154 155 /* SD application packets */ 156 #define UHS2_SD_CMD_INDEX_POS 8 157 158 #define UHS2_SD_CMD_APP_POS 14 159 #define UHS2_SD_CMD_APP (1 << UHS2_SD_CMD_APP_POS) 160 161 /* UHS-II Device Registers */ 162 #define UHS2_DEV_CONFIG_REG 0x000 163 164 /* General Caps and Settings registers */ 165 #define UHS2_DEV_CONFIG_GEN_CAPS (UHS2_DEV_CONFIG_REG + 0x000) 166 #define UHS2_DEV_CONFIG_N_LANES_POS 8 167 #define UHS2_DEV_CONFIG_N_LANES_MASK 0x3F 168 #define UHS2_DEV_CONFIG_2L_HD_FD 0x1 169 #define UHS2_DEV_CONFIG_2D1U_FD 0x2 170 #define UHS2_DEV_CONFIG_1D2U_FD 0x4 171 #define UHS2_DEV_CONFIG_2D2U_FD 0x8 172 #define UHS2_DEV_CONFIG_DADR_POS 14 173 #define UHS2_DEV_CONFIG_DADR_MASK 0x1 174 #define UHS2_DEV_CONFIG_APP_POS 16 175 #define UHS2_DEV_CONFIG_APP_MASK 0xFF 176 #define UHS2_DEV_CONFIG_APP_SD_MEM 0x1 177 178 #define UHS2_DEV_CONFIG_GEN_SET (UHS2_DEV_CONFIG_REG + 0x008) 179 #define UHS2_DEV_CONFIG_GEN_SET_N_LANES_POS 8 180 #define UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD 0x0 181 #define UHS2_DEV_CONFIG_GEN_SET_2D1U_FD 0x2 182 #define UHS2_DEV_CONFIG_GEN_SET_1D2U_FD 0x3 183 #define UHS2_DEV_CONFIG_GEN_SET_2D2U_FD 0x4 184 #define UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE BIT(31) 185 186 /* PHY Caps and Settings registers */ 187 #define UHS2_DEV_CONFIG_PHY_CAPS (UHS2_DEV_CONFIG_REG + 0x002) 188 #define UHS2_DEV_CONFIG_PHY_MINOR_MASK 0xF 189 #define UHS2_DEV_CONFIG_PHY_MAJOR_POS 4 190 #define UHS2_DEV_CONFIG_PHY_MAJOR_MASK 0x3 191 #define UHS2_DEV_CONFIG_CAN_HIBER_POS 15 192 #define UHS2_DEV_CONFIG_CAN_HIBER_MASK 0x1 193 #define UHS2_DEV_CONFIG_PHY_CAPS1 (UHS2_DEV_CONFIG_REG + 0x003) 194 #define UHS2_DEV_CONFIG_N_LSS_SYN_MASK 0xF 195 #define UHS2_DEV_CONFIG_N_LSS_DIR_POS 4 196 #define UHS2_DEV_CONFIG_N_LSS_DIR_MASK 0xF 197 198 #define UHS2_DEV_CONFIG_PHY_SET (UHS2_DEV_CONFIG_REG + 0x00A) 199 #define UHS2_DEV_CONFIG_PHY_SET_SPEED_POS 6 200 #define UHS2_DEV_CONFIG_PHY_SET_SPEED_A 0x0 201 #define UHS2_DEV_CONFIG_PHY_SET_SPEED_B 0x1 202 203 /* LINK-TRAN Caps and Settings registers */ 204 #define UHS2_DEV_CONFIG_LINK_TRAN_CAPS (UHS2_DEV_CONFIG_REG + 0x004) 205 #define UHS2_DEV_CONFIG_LT_MINOR_MASK 0xF 206 #define UHS2_DEV_CONFIG_LT_MAJOR_POS 4 207 #define UHS2_DEV_CONFIG_LT_MAJOR_MASK 0x3 208 #define UHS2_DEV_CONFIG_N_FCU_POS 8 209 #define UHS2_DEV_CONFIG_N_FCU_MASK 0xFF 210 #define UHS2_DEV_CONFIG_DEV_TYPE_POS 16 211 #define UHS2_DEV_CONFIG_DEV_TYPE_MASK 0x7 212 #define UHS2_DEV_CONFIG_MAX_BLK_LEN_POS 20 213 #define UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK 0xFFF 214 #define UHS2_DEV_CONFIG_LINK_TRAN_CAPS1 (UHS2_DEV_CONFIG_REG + 0x005) 215 #define UHS2_DEV_CONFIG_N_DATA_GAP_MASK 0xFF 216 217 #define UHS2_DEV_CONFIG_LINK_TRAN_SET (UHS2_DEV_CONFIG_REG + 0x00C) 218 #define UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN 0x200 219 #define UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_POS 16 220 221 /* Preset register */ 222 #define UHS2_DEV_CONFIG_PRESET (UHS2_DEV_CONFIG_REG + 0x040) 223 224 #define UHS2_DEV_INT_REG 0x100 225 226 #define UHS2_DEV_STATUS_REG 0x180 227 228 #define UHS2_DEV_CMD_REG 0x200 229 #define UHS2_DEV_CMD_FULL_RESET (UHS2_DEV_CMD_REG + 0x000) 230 #define UHS2_DEV_CMD_GO_DORMANT_STATE (UHS2_DEV_CMD_REG + 0x001) 231 #define UHS2_DEV_CMD_DORMANT_HIBER BIT(7) 232 #define UHS2_DEV_CMD_DEVICE_INIT (UHS2_DEV_CMD_REG + 0x002) 233 #define UHS2_DEV_INIT_COMPLETE_FLAG BIT(11) 234 #define UHS2_DEV_CMD_ENUMERATE (UHS2_DEV_CMD_REG + 0x003) 235 #define UHS2_DEV_CMD_TRANS_ABORT (UHS2_DEV_CMD_REG + 0x004) 236 237 #define UHS2_RCLK_MAX 52000000 238 #define UHS2_RCLK_MIN 26000000 239 240 #endif /* LINUX_MMC_UHS2_H */ 241