1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Oleksij Rempel <[email protected]> 4 * 5 * Driver for Alcor Micro AU6601 and AU6621 controllers 6 */ 7 8 #ifndef __ALCOR_PCI_H 9 #define __ALCOR_PCI_H 10 11 #define ALCOR_SD_CARD 0 12 #define ALCOR_MS_CARD 1 13 14 #define DRV_NAME_ALCOR_PCI "alcor_pci" 15 #define DRV_NAME_ALCOR_PCI_SDMMC "alcor_sdmmc" 16 #define DRV_NAME_ALCOR_PCI_MS "alcor_ms" 17 18 #define PCI_ID_ALCOR_MICRO 0x1AEA 19 #define PCI_ID_AU6601 0x6601 20 #define PCI_ID_AU6621 0x6621 21 #define PCI_ID_AU6625 0x6625 22 23 #define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000) 24 25 #define AU6601_BASE_CLOCK 31000000 26 #define AU6601_MIN_CLOCK 150000 27 #define AU6601_MAX_CLOCK 208000000 28 #define AU6601_MAX_DMA_SEGMENTS 64 29 #define AU6601_MAX_PIO_SEGMENTS 1 30 #define AU6601_MAX_DMA_BLOCK_SIZE 0x1000 31 #define AU6601_MAX_PIO_BLOCK_SIZE 0x200 32 #define AU6601_MAX_DMA_BLOCKS 1 33 #define AU6601_DMA_LOCAL_SEGMENTS 1 34 35 /* registers spotter by reverse engineering but still 36 * with unknown functionality: 37 * 0x10 - ADMA phy address. AU6621 only? 38 * 0x51 - LED ctrl? 39 * 0x52 - unknown 40 * 0x61 - LED related? Always toggled BIT0 41 * 0x63 - Same as 0x61? 42 * 0x77 - unknown 43 */ 44 45 /* SDMA phy address. Higher then 0x0800.0000? 46 * The au6601 and au6621 have different DMA engines with different issues. One 47 * For example au6621 engine is triggered by addr change. No other interaction 48 * is needed. This means, if we get two buffers with same address, then engine 49 * will stall. 50 */ 51 #define AU6601_REG_SDMA_ADDR 0x00 52 #define AU6601_SDMA_MASK 0xffffffff 53 54 #define AU6601_DMA_BOUNDARY 0x05 55 #define AU6621_DMA_PAGE_CNT 0x05 56 /* PIO */ 57 #define AU6601_REG_BUFFER 0x08 58 /* ADMA ctrl? AU6621 only. */ 59 #define AU6621_DMA_CTRL 0x0c 60 #define AU6621_DMA_ENABLE BIT(0) 61 /* CMD index */ 62 #define AU6601_REG_CMD_OPCODE 0x23 63 /* CMD parametr */ 64 #define AU6601_REG_CMD_ARG 0x24 65 /* CMD response 4x4 Bytes */ 66 #define AU6601_REG_CMD_RSP0 0x30 67 #define AU6601_REG_CMD_RSP1 0x34 68 #define AU6601_REG_CMD_RSP2 0x38 69 #define AU6601_REG_CMD_RSP3 0x3C 70 /* default timeout set to 125: 125 * 40ms = 5 sec 71 * how exactly it is calculated? 72 */ 73 #define AU6601_TIME_OUT_CTRL 0x69 74 /* Block size for SDMA or PIO */ 75 #define AU6601_REG_BLOCK_SIZE 0x6c 76 /* Some power related reg, used together with AU6601_OUTPUT_ENABLE */ 77 #define AU6601_POWER_CONTROL 0x70 78 79 /* PLL ctrl */ 80 #define AU6601_CLK_SELECT 0x72 81 #define AU6601_CLK_OVER_CLK 0x80 82 #define AU6601_CLK_384_MHZ 0x30 83 #define AU6601_CLK_125_MHZ 0x20 84 #define AU6601_CLK_48_MHZ 0x10 85 #define AU6601_CLK_EXT_PLL 0x04 86 #define AU6601_CLK_X2_MODE 0x02 87 #define AU6601_CLK_ENABLE 0x01 88 #define AU6601_CLK_31_25_MHZ 0x00 89 90 #define AU6601_CLK_DIVIDER 0x73 91 92 #define AU6601_INTERFACE_MODE_CTRL 0x74 93 #define AU6601_DLINK_MODE 0x80 94 #define AU6601_INTERRUPT_DELAY_TIME 0x40 95 #define AU6601_SIGNAL_REQ_CTRL 0x30 96 #define AU6601_MS_CARD_WP BIT(3) 97 #define AU6601_SD_CARD_WP BIT(0) 98 99 /* same register values are used for: 100 * - AU6601_OUTPUT_ENABLE 101 * - AU6601_POWER_CONTROL 102 */ 103 #define AU6601_ACTIVE_CTRL 0x75 104 #define AU6601_XD_CARD BIT(4) 105 /* AU6601_MS_CARD_ACTIVE - will cativate MS card section? */ 106 #define AU6601_MS_CARD BIT(3) 107 #define AU6601_SD_CARD BIT(0) 108 109 /* card slot state. It should automatically detect type of 110 * the card 111 */ 112 #define AU6601_DETECT_STATUS 0x76 113 #define AU6601_DETECT_EN BIT(7) 114 #define AU6601_MS_DETECTED BIT(3) 115 #define AU6601_SD_DETECTED BIT(0) 116 #define AU6601_DETECT_STATUS_M 0xf 117 118 #define AU6601_REG_SW_RESET 0x79 119 #define AU6601_BUF_CTRL_RESET BIT(7) 120 #define AU6601_RESET_DATA BIT(3) 121 #define AU6601_RESET_CMD BIT(0) 122 123 #define AU6601_OUTPUT_ENABLE 0x7a 124 125 #define AU6601_PAD_DRIVE0 0x7b 126 #define AU6601_PAD_DRIVE1 0x7c 127 #define AU6601_PAD_DRIVE2 0x7d 128 /* read EEPROM? */ 129 #define AU6601_FUNCTION 0x7f 130 131 #define AU6601_CMD_XFER_CTRL 0x81 132 #define AU6601_CMD_17_BYTE_CRC 0xc0 133 #define AU6601_CMD_6_BYTE_WO_CRC 0x80 134 #define AU6601_CMD_6_BYTE_CRC 0x40 135 #define AU6601_CMD_START_XFER 0x20 136 #define AU6601_CMD_STOP_WAIT_RDY 0x10 137 #define AU6601_CMD_NO_RESP 0x00 138 139 #define AU6601_REG_BUS_CTRL 0x82 140 #define AU6601_BUS_WIDTH_4BIT 0x20 141 #define AU6601_BUS_WIDTH_8BIT 0x10 142 #define AU6601_BUS_WIDTH_1BIT 0x00 143 144 #define AU6601_DATA_XFER_CTRL 0x83 145 #define AU6601_DATA_WRITE BIT(7) 146 #define AU6601_DATA_DMA_MODE BIT(6) 147 #define AU6601_DATA_START_XFER BIT(0) 148 149 #define AU6601_DATA_PIN_STATE 0x84 150 #define AU6601_BUS_STAT_CMD BIT(15) 151 /* BIT(4) - BIT(7) are permanently 1. 152 * May be reserved or not attached DAT4-DAT7 153 */ 154 #define AU6601_BUS_STAT_DAT3 BIT(3) 155 #define AU6601_BUS_STAT_DAT2 BIT(2) 156 #define AU6601_BUS_STAT_DAT1 BIT(1) 157 #define AU6601_BUS_STAT_DAT0 BIT(0) 158 #define AU6601_BUS_STAT_DAT_MASK 0xf 159 160 #define AU6601_OPT 0x85 161 #define AU6601_OPT_CMD_LINE_LEVEL 0x80 162 #define AU6601_OPT_NCRC_16_CLK BIT(4) 163 #define AU6601_OPT_CMD_NWT BIT(3) 164 #define AU6601_OPT_STOP_CLK BIT(2) 165 #define AU6601_OPT_DDR_MODE BIT(1) 166 #define AU6601_OPT_SD_18V BIT(0) 167 168 #define AU6601_CLK_DELAY 0x86 169 #define AU6601_CLK_DATA_POSITIVE_EDGE 0x80 170 #define AU6601_CLK_CMD_POSITIVE_EDGE 0x40 171 #define AU6601_CLK_POSITIVE_EDGE_ALL (AU6601_CLK_CMD_POSITIVE_EDGE \ 172 | AU6601_CLK_DATA_POSITIVE_EDGE) 173 174 175 #define AU6601_REG_INT_STATUS 0x90 176 #define AU6601_REG_INT_ENABLE 0x94 177 #define AU6601_INT_DATA_END_BIT_ERR BIT(22) 178 #define AU6601_INT_DATA_CRC_ERR BIT(21) 179 #define AU6601_INT_DATA_TIMEOUT_ERR BIT(20) 180 #define AU6601_INT_CMD_INDEX_ERR BIT(19) 181 #define AU6601_INT_CMD_END_BIT_ERR BIT(18) 182 #define AU6601_INT_CMD_CRC_ERR BIT(17) 183 #define AU6601_INT_CMD_TIMEOUT_ERR BIT(16) 184 #define AU6601_INT_ERROR BIT(15) 185 #define AU6601_INT_OVER_CURRENT_ERR BIT(8) 186 #define AU6601_INT_CARD_INSERT BIT(7) 187 #define AU6601_INT_CARD_REMOVE BIT(6) 188 #define AU6601_INT_READ_BUF_RDY BIT(5) 189 #define AU6601_INT_WRITE_BUF_RDY BIT(4) 190 #define AU6601_INT_DMA_END BIT(3) 191 #define AU6601_INT_DATA_END BIT(1) 192 #define AU6601_INT_CMD_END BIT(0) 193 194 #define AU6601_INT_NORMAL_MASK 0x00007FFF 195 #define AU6601_INT_ERROR_MASK 0xFFFF8000 196 197 #define AU6601_INT_CMD_MASK (AU6601_INT_CMD_END | \ 198 AU6601_INT_CMD_TIMEOUT_ERR | AU6601_INT_CMD_CRC_ERR | \ 199 AU6601_INT_CMD_END_BIT_ERR | AU6601_INT_CMD_INDEX_ERR) 200 #define AU6601_INT_DATA_MASK (AU6601_INT_DATA_END | AU6601_INT_DMA_END | \ 201 AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY | \ 202 AU6601_INT_DATA_TIMEOUT_ERR | AU6601_INT_DATA_CRC_ERR | \ 203 AU6601_INT_DATA_END_BIT_ERR) 204 #define AU6601_INT_ALL_MASK ((u32)-1) 205 206 /* MS_CARD mode registers */ 207 208 #define AU6601_MS_STATUS 0xa0 209 210 #define AU6601_MS_BUS_MODE_CTRL 0xa1 211 #define AU6601_MS_BUS_8BIT_MODE 0x03 212 #define AU6601_MS_BUS_4BIT_MODE 0x01 213 #define AU6601_MS_BUS_1BIT_MODE 0x00 214 215 #define AU6601_MS_TPC_CMD 0xa2 216 #define AU6601_MS_TPC_READ_PAGE_DATA 0x02 217 #define AU6601_MS_TPC_READ_REG 0x04 218 #define AU6601_MS_TPC_GET_INT 0x07 219 #define AU6601_MS_TPC_WRITE_PAGE_DATA 0x0D 220 #define AU6601_MS_TPC_WRITE_REG 0x0B 221 #define AU6601_MS_TPC_SET_RW_REG_ADRS 0x08 222 #define AU6601_MS_TPC_SET_CMD 0x0E 223 #define AU6601_MS_TPC_EX_SET_CMD 0x09 224 #define AU6601_MS_TPC_READ_SHORT_DATA 0x03 225 #define AU6601_MS_TPC_WRITE_SHORT_DATA 0x0C 226 227 #define AU6601_MS_TRANSFER_MODE 0xa3 228 #define AU6601_MS_XFER_INT_TIMEOUT_CHK BIT(2) 229 #define AU6601_MS_XFER_DMA_ENABLE BIT(1) 230 #define AU6601_MS_XFER_START BIT(0) 231 232 #define AU6601_MS_DATA_PIN_STATE 0xa4 233 234 #define AU6601_MS_INT_STATUS 0xb0 235 #define AU6601_MS_INT_ENABLE 0xb4 236 #define AU6601_MS_INT_OVER_CURRENT_ERROR BIT(23) 237 #define AU6601_MS_INT_DATA_CRC_ERROR BIT(21) 238 #define AU6601_MS_INT_INT_TIMEOUT BIT(20) 239 #define AU6601_MS_INT_INT_RESP_ERROR BIT(19) 240 #define AU6601_MS_INT_CED_ERROR BIT(18) 241 #define AU6601_MS_INT_TPC_TIMEOUT BIT(16) 242 #define AU6601_MS_INT_ERROR BIT(15) 243 #define AU6601_MS_INT_CARD_INSERT BIT(7) 244 #define AU6601_MS_INT_CARD_REMOVE BIT(6) 245 #define AU6601_MS_INT_BUF_READ_RDY BIT(5) 246 #define AU6601_MS_INT_BUF_WRITE_RDY BIT(4) 247 #define AU6601_MS_INT_DMA_END BIT(3) 248 #define AU6601_MS_INT_TPC_END BIT(1) 249 250 #define AU6601_MS_INT_DATA_MASK 0x00000038 251 #define AU6601_MS_INT_TPC_MASK 0x003d8002 252 #define AU6601_MS_INT_TPC_ERROR 0x003d0000 253 254 #define ALCOR_PCIE_LINK_CTRL_OFFSET 0x10 255 #define ALCOR_PCIE_LINK_CAP_OFFSET 0x0c 256 #define ALCOR_CAP_START_OFFSET 0x34 257 258 struct alcor_dev_cfg { 259 u8 dma; 260 }; 261 262 struct alcor_pci_priv { 263 struct pci_dev *pdev; 264 struct pci_dev *parent_pdev; 265 struct device *dev; 266 void __iomem *iobase; 267 unsigned int irq; 268 269 unsigned long id; /* idr id */ 270 271 struct alcor_dev_cfg *cfg; 272 }; 273 274 void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr); 275 void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr); 276 void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr); 277 void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr); 278 u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr); 279 u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr); 280 u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr); 281 #endif 282