1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Type definitions for the Microsoft hypervisor. 4 */ 5 #ifndef _HV_HVGDK_MINI_H 6 #define _HV_HVGDK_MINI_H 7 8 #include <linux/types.h> 9 #include <linux/bits.h> 10 11 struct hv_u128 { 12 u64 low_part; 13 u64 high_part; 14 } __packed; 15 16 /* NOTE: when adding below, update hv_status_to_string() */ 17 #define HV_STATUS_SUCCESS 0x0 18 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2 19 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3 20 #define HV_STATUS_INVALID_ALIGNMENT 0x4 21 #define HV_STATUS_INVALID_PARAMETER 0x5 22 #define HV_STATUS_ACCESS_DENIED 0x6 23 #define HV_STATUS_INVALID_PARTITION_STATE 0x7 24 #define HV_STATUS_OPERATION_DENIED 0x8 25 #define HV_STATUS_UNKNOWN_PROPERTY 0x9 26 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA 27 #define HV_STATUS_INSUFFICIENT_MEMORY 0xB 28 #define HV_STATUS_INVALID_PARTITION_ID 0xD 29 #define HV_STATUS_INVALID_VP_INDEX 0xE 30 #define HV_STATUS_NOT_FOUND 0x10 31 #define HV_STATUS_INVALID_PORT_ID 0x11 32 #define HV_STATUS_INVALID_CONNECTION_ID 0x12 33 #define HV_STATUS_INSUFFICIENT_BUFFERS 0x13 34 #define HV_STATUS_NOT_ACKNOWLEDGED 0x14 35 #define HV_STATUS_INVALID_VP_STATE 0x15 36 #define HV_STATUS_NO_RESOURCES 0x1D 37 #define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20 38 #define HV_STATUS_INVALID_LP_INDEX 0x41 39 #define HV_STATUS_INVALID_REGISTER_VALUE 0x50 40 #define HV_STATUS_OPERATION_FAILED 0x71 41 #define HV_STATUS_TIME_OUT 0x78 42 #define HV_STATUS_CALL_PENDING 0x79 43 #define HV_STATUS_VTL_ALREADY_ENABLED 0x86 44 45 /* 46 * The Hyper-V TimeRefCount register and the TSC 47 * page provide a guest VM clock with 100ns tick rate 48 */ 49 #define HV_CLOCK_HZ (NSEC_PER_SEC / 100) 50 51 #define HV_HYP_PAGE_SHIFT 12 52 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) 53 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 54 55 #define HV_PARTITION_ID_INVALID ((u64)0) 56 #define HV_PARTITION_ID_SELF ((u64)-1) 57 58 /* Hyper-V specific model specific registers (MSRs) */ 59 60 #if defined(CONFIG_X86) 61 /* HV_X64_SYNTHETIC_MSR */ 62 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 63 #define HV_X64_MSR_HYPERCALL 0x40000001 64 #define HV_X64_MSR_VP_INDEX 0x40000002 65 #define HV_X64_MSR_RESET 0x40000003 66 #define HV_X64_MSR_VP_RUNTIME 0x40000010 67 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 68 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 69 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 70 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 71 72 /* Define the virtual APIC registers */ 73 #define HV_X64_MSR_EOI 0x40000070 74 #define HV_X64_MSR_ICR 0x40000071 75 #define HV_X64_MSR_TPR 0x40000072 76 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 77 78 /* Define synthetic interrupt controller model specific registers. */ 79 #define HV_X64_MSR_SCONTROL 0x40000080 80 #define HV_X64_MSR_SVERSION 0x40000081 81 #define HV_X64_MSR_SIEFP 0x40000082 82 #define HV_X64_MSR_SIMP 0x40000083 83 #define HV_X64_MSR_EOM 0x40000084 84 #define HV_X64_MSR_SIRBP 0x40000085 85 #define HV_X64_MSR_SINT0 0x40000090 86 #define HV_X64_MSR_SINT1 0x40000091 87 #define HV_X64_MSR_SINT2 0x40000092 88 #define HV_X64_MSR_SINT3 0x40000093 89 #define HV_X64_MSR_SINT4 0x40000094 90 #define HV_X64_MSR_SINT5 0x40000095 91 #define HV_X64_MSR_SINT6 0x40000096 92 #define HV_X64_MSR_SINT7 0x40000097 93 #define HV_X64_MSR_SINT8 0x40000098 94 #define HV_X64_MSR_SINT9 0x40000099 95 #define HV_X64_MSR_SINT10 0x4000009A 96 #define HV_X64_MSR_SINT11 0x4000009B 97 #define HV_X64_MSR_SINT12 0x4000009C 98 #define HV_X64_MSR_SINT13 0x4000009D 99 #define HV_X64_MSR_SINT14 0x4000009E 100 #define HV_X64_MSR_SINT15 0x4000009F 101 102 /* Define synthetic interrupt controller model specific registers for nested hypervisor */ 103 #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 104 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 105 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 106 #define HV_X64_MSR_NESTED_SIMP 0x40001083 107 #define HV_X64_MSR_NESTED_EOM 0x40001084 108 #define HV_X64_MSR_NESTED_SINT0 0x40001090 109 110 /* 111 * Synthetic Timer MSRs. Four timers per vcpu. 112 */ 113 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 114 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 115 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 116 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 117 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 118 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 119 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 120 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 121 122 /* Hyper-V guest idle MSR */ 123 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 124 125 /* Hyper-V guest crash notification MSR's */ 126 #define HV_X64_MSR_CRASH_P0 0x40000100 127 #define HV_X64_MSR_CRASH_P1 0x40000101 128 #define HV_X64_MSR_CRASH_P2 0x40000102 129 #define HV_X64_MSR_CRASH_P3 0x40000103 130 #define HV_X64_MSR_CRASH_P4 0x40000104 131 #define HV_X64_MSR_CRASH_CTL 0x40000105 132 133 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 134 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 135 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 136 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 137 138 #define HV_X64_MSR_CRASH_PARAMS \ 139 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 140 141 #define HV_IPI_LOW_VECTOR 0x10 142 #define HV_IPI_HIGH_VECTOR 0xff 143 144 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 145 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 146 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 147 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 148 149 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 150 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 151 152 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 153 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 154 155 /* Number of XMM registers used in hypercall input/output */ 156 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 157 158 struct hv_reenlightenment_control { 159 u64 vector : 8; 160 u64 reserved1 : 8; 161 u64 enabled : 1; 162 u64 reserved2 : 15; 163 u64 target_vp : 32; 164 } __packed; 165 166 struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */ 167 u64 inprogress : 1; 168 u64 reserved : 63; 169 } __packed; 170 171 struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */ 172 u64 enabled : 1; 173 u64 reserved : 63; 174 } __packed; 175 176 /* TSC emulation after migration */ 177 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 178 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 179 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 180 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 181 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) 182 183 #endif /* CONFIG_X86 */ 184 185 struct hv_get_partition_id { /* HV_OUTPUT_GET_PARTITION_ID */ 186 u64 partition_id; 187 } __packed; 188 189 /* HV_CRASH_CTL_REG_CONTENTS */ 190 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 191 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 192 193 union hv_reference_tsc_msr { 194 u64 as_uint64; 195 struct { 196 u64 enable : 1; 197 u64 reserved : 11; 198 u64 pfn : 52; 199 } __packed; 200 }; 201 202 /* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */ 203 #define HV_MAX_SPARSE_VCPU_BANKS (64) 204 /* The number of vCPUs in one sparse bank */ 205 #define HV_VCPUS_PER_SPARSE_BANK (64) 206 207 /* Some of Hyper-V structs do not use hv_vpset where linux uses them */ 208 struct hv_vpset { /* HV_VP_SET */ 209 u64 format; 210 u64 valid_bank_mask; 211 u64 bank_contents[]; 212 } __packed; 213 214 /* 215 * Version info reported by hypervisor 216 * Changed to a union for convenience 217 */ 218 union hv_hypervisor_version_info { 219 struct { 220 u32 build_number; 221 222 u32 minor_version : 16; 223 u32 major_version : 16; 224 225 u32 service_pack; 226 227 u32 service_number : 24; 228 u32 service_branch : 8; 229 }; 230 struct { 231 u32 eax; 232 u32 ebx; 233 u32 ecx; 234 u32 edx; 235 }; 236 }; 237 238 /* HV_CPUID_FUNCTION */ 239 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 240 #define HYPERV_CPUID_INTERFACE 0x40000001 241 #define HYPERV_CPUID_VERSION 0x40000002 242 #define HYPERV_CPUID_FEATURES 0x40000003 243 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 244 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 245 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 246 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 247 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 248 249 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 250 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 251 252 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 253 /* Support for the extended IOAPIC RTE format */ 254 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 255 256 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 257 #define HYPERV_CPUID_MIN 0x40000005 258 #define HYPERV_CPUID_MAX 0x4000ffff 259 260 /* 261 * HV_X64_HYPERVISOR_FEATURES (EAX), or 262 * HV_PARTITION_PRIVILEGE_MASK [31-0] 263 */ 264 #define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0) 265 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) 266 #define HV_MSR_SYNIC_AVAILABLE BIT(2) 267 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) 268 #define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4) 269 #define HV_MSR_HYPERCALL_AVAILABLE BIT(5) 270 #define HV_MSR_VP_INDEX_AVAILABLE BIT(6) 271 #define HV_MSR_RESET_AVAILABLE BIT(7) 272 #define HV_MSR_STAT_PAGES_AVAILABLE BIT(8) 273 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) 274 #define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10) 275 #define HV_ACCESS_FREQUENCY_MSRS BIT(11) 276 #define HV_ACCESS_REENLIGHTENMENT BIT(13) 277 #define HV_ACCESS_TSC_INVARIANT BIT(15) 278 279 /* 280 * HV_X64_HYPERVISOR_FEATURES (EBX), or 281 * HV_PARTITION_PRIVILEGE_MASK [63-32] 282 */ 283 #define HV_CREATE_PARTITIONS BIT(0) 284 #define HV_ACCESS_PARTITION_ID BIT(1) 285 #define HV_ACCESS_MEMORY_POOL BIT(2) 286 #define HV_ADJUST_MESSAGE_BUFFERS BIT(3) 287 #define HV_POST_MESSAGES BIT(4) 288 #define HV_SIGNAL_EVENTS BIT(5) 289 #define HV_CREATE_PORT BIT(6) 290 #define HV_CONNECT_PORT BIT(7) 291 #define HV_ACCESS_STATS BIT(8) 292 #define HV_DEBUGGING BIT(11) 293 #define HV_CPU_MANAGEMENT BIT(12) 294 #define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20) 295 #define HV_ISOLATION BIT(22) 296 297 #if defined(CONFIG_X86) 298 /* HV_X64_HYPERVISOR_FEATURES (EDX) */ 299 #define HV_X64_MWAIT_AVAILABLE BIT(0) 300 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 301 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 302 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 303 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 304 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 305 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 306 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 307 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 308 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 309 /* 310 * Support for returning hypercall output block via XMM 311 * registers is available 312 */ 313 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 314 /* stimer Direct Mode is available */ 315 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 316 317 /* 318 * Implementation recommendations. Indicates which behaviors the hypervisor 319 * recommends the OS implement for optimal performance. 320 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 321 */ 322 /* HV_X64_ENLIGHTENMENT_INFORMATION */ 323 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 324 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 325 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 326 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 327 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 328 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 329 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 330 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 331 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 332 #define HV_X64_HYPERV_NESTED BIT(12) 333 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 334 #define HV_X64_USE_MMIO_HYPERCALLS BIT(21) 335 336 /* 337 * CPU management features identification. 338 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 339 */ 340 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 341 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 342 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 343 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 344 345 /* 346 * Virtual processor will never share a physical core with another virtual 347 * processor, except for virtual processors that are reported as sibling SMT 348 * threads. 349 */ 350 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 351 352 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 353 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 354 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 355 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 356 357 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 358 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 359 360 /* 361 * This is specific to AMD and specifies that enlightened TLB flush is 362 * supported. If guest opts in to this feature, ASID invalidations only 363 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 364 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 365 * or HvFlushGuestPhysicalAddressList). 366 */ 367 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 368 369 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 370 #define HV_PARAVISOR_PRESENT BIT(0) 371 372 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 373 #define HV_ISOLATION_TYPE GENMASK(3, 0) 374 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 375 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 376 377 enum hv_isolation_type { 378 HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */ 379 HV_ISOLATION_TYPE_VBS = 1, 380 HV_ISOLATION_TYPE_SNP = 2, 381 HV_ISOLATION_TYPE_TDX = 3 382 }; 383 384 union hv_x64_msr_hypercall_contents { 385 u64 as_uint64; 386 struct { 387 u64 enable : 1; 388 u64 reserved : 11; 389 u64 guest_physical_address : 52; 390 } __packed; 391 }; 392 #endif /* CONFIG_X86 */ 393 394 #if defined(CONFIG_ARM64) 395 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8) 396 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13) 397 #endif /* CONFIG_ARM64 */ 398 399 #if defined(CONFIG_X86) 400 #define HV_MAXIMUM_PROCESSORS 2048 401 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 402 #define HV_MAXIMUM_PROCESSORS 320 403 #endif /* CONFIG_ARM64 */ 404 405 #define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1) 406 #define HV_VP_INDEX_SELF ((u32)-2) 407 #define HV_ANY_VP ((u32)-1) 408 409 union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */ 410 u64 as_uint64; 411 struct { 412 u64 enable : 1; 413 u64 reserved : 11; 414 u64 pfn : 52; 415 } __packed; 416 }; 417 418 /* Declare the various hypercall operations. */ 419 /* HV_CALL_CODE */ 420 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 421 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 422 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 423 #define HVCALL_SEND_IPI 0x000b 424 #define HVCALL_ENABLE_VP_VTL 0x000f 425 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 426 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 427 #define HVCALL_SEND_IPI_EX 0x0015 428 #define HVCALL_CREATE_PARTITION 0x0040 429 #define HVCALL_INITIALIZE_PARTITION 0x0041 430 #define HVCALL_FINALIZE_PARTITION 0x0042 431 #define HVCALL_DELETE_PARTITION 0x0043 432 #define HVCALL_GET_PARTITION_PROPERTY 0x0044 433 #define HVCALL_SET_PARTITION_PROPERTY 0x0045 434 #define HVCALL_GET_PARTITION_ID 0x0046 435 #define HVCALL_DEPOSIT_MEMORY 0x0048 436 #define HVCALL_WITHDRAW_MEMORY 0x0049 437 #define HVCALL_MAP_GPA_PAGES 0x004b 438 #define HVCALL_UNMAP_GPA_PAGES 0x004c 439 #define HVCALL_CREATE_VP 0x004e 440 #define HVCALL_DELETE_VP 0x004f 441 #define HVCALL_GET_VP_REGISTERS 0x0050 442 #define HVCALL_SET_VP_REGISTERS 0x0051 443 #define HVCALL_DELETE_PORT 0x0058 444 #define HVCALL_DISCONNECT_PORT 0x005b 445 #define HVCALL_POST_MESSAGE 0x005c 446 #define HVCALL_SIGNAL_EVENT 0x005d 447 #define HVCALL_POST_DEBUG_DATA 0x0069 448 #define HVCALL_RETRIEVE_DEBUG_DATA 0x006a 449 #define HVCALL_RESET_DEBUG_SESSION 0x006b 450 #define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076 451 #define HVCALL_GET_SYSTEM_PROPERTY 0x007b 452 #define HVCALL_MAP_DEVICE_INTERRUPT 0x007c 453 #define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d 454 #define HVCALL_RETARGET_INTERRUPT 0x007e 455 #define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b 456 #define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094 457 #define HVCALL_CREATE_PORT 0x0095 458 #define HVCALL_CONNECT_PORT 0x0096 459 #define HVCALL_START_VP 0x0099 460 #define HVCALL_GET_VP_ID_FROM_APIC_ID 0x009a 461 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 462 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 463 #define HVCALL_DISPATCH_VP 0x00c2 464 #define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db 465 #define HVCALL_MAP_VP_STATE_PAGE 0x00e1 466 #define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2 467 #define HVCALL_GET_VP_STATE 0x00e3 468 #define HVCALL_SET_VP_STATE 0x00e4 469 #define HVCALL_MMIO_READ 0x0106 470 #define HVCALL_MMIO_WRITE 0x0107 471 472 /* HV_HYPERCALL_INPUT */ 473 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 474 #define HV_HYPERCALL_FAST_BIT BIT(16) 475 #define HV_HYPERCALL_VARHEAD_OFFSET 17 476 #define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17) 477 #define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27) 478 #define HV_HYPERCALL_NESTED BIT_ULL(31) 479 #define HV_HYPERCALL_REP_COMP_OFFSET 32 480 #define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32) 481 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 482 #define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44) 483 #define HV_HYPERCALL_REP_START_OFFSET 48 484 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 485 #define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60) 486 #define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \ 487 HV_HYPERCALL_RSVD1_MASK | \ 488 HV_HYPERCALL_RSVD2_MASK) 489 490 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 491 struct hv_guest_mapping_flush { 492 u64 address_space; 493 u64 flags; 494 } __packed; 495 496 /* 497 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 498 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 499 */ 500 #define HV_MAX_FLUSH_PAGES (2048) 501 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0 502 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1 503 504 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 505 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 506 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 507 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 508 509 /* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */ 510 union hv_gpa_page_range { 511 u64 address_space; 512 struct { 513 u64 additional_pages : 11; 514 u64 largepage : 1; 515 u64 basepfn : 52; 516 } page; 517 struct { 518 u64 reserved : 12; 519 u64 page_size : 1; 520 u64 reserved1 : 8; 521 u64 base_large_pfn : 43; 522 }; 523 }; 524 525 /* 526 * All input flush parameters should be in single page. The max flush 527 * count is equal with how many entries of union hv_gpa_page_range can 528 * be populated into the input parameter page. 529 */ 530 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 531 sizeof(union hv_gpa_page_range)) 532 533 struct hv_guest_mapping_flush_list { 534 u64 address_space; 535 u64 flags; 536 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 537 }; 538 539 struct hv_tlb_flush { /* HV_INPUT_FLUSH_VIRTUAL_ADDRESS_LIST */ 540 u64 address_space; 541 u64 flags; 542 u64 processor_mask; 543 u64 gva_list[]; 544 } __packed; 545 546 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 547 struct hv_tlb_flush_ex { 548 u64 address_space; 549 u64 flags; 550 struct hv_vpset hv_vp_set; 551 u64 gva_list[]; 552 } __packed; 553 554 struct ms_hyperv_tsc_page { /* HV_REFERENCE_TSC_PAGE */ 555 volatile u32 tsc_sequence; 556 u32 reserved1; 557 volatile u64 tsc_scale; 558 volatile s64 tsc_offset; 559 } __packed; 560 561 /* Define the number of synthetic interrupt sources. */ 562 #define HV_SYNIC_SINT_COUNT (16) 563 564 /* Define the expected SynIC version. */ 565 #define HV_SYNIC_VERSION_1 (0x1) 566 /* Valid SynIC vectors are 16-255. */ 567 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 568 569 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 570 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 571 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 572 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 573 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 574 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 575 576 # 577 578 /* Hyper-V defined statically assigned SINTs */ 579 #define HV_SYNIC_INTERCEPTION_SINT_INDEX 0x00000000 580 #define HV_SYNIC_IOMMU_FAULT_SINT_INDEX 0x00000001 581 #define HV_SYNIC_VMBUS_SINT_INDEX 0x00000002 582 #define HV_SYNIC_FIRST_UNUSED_SINT_INDEX 0x00000005 583 584 /* mshv assigned SINT for doorbell */ 585 #define HV_SYNIC_DOORBELL_SINT_INDEX HV_SYNIC_FIRST_UNUSED_SINT_INDEX 586 587 enum hv_interrupt_type { 588 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 589 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 590 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 591 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 592 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 593 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 594 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 595 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 596 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 597 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 598 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 599 }; 600 601 /* Define synthetic interrupt source. */ 602 union hv_synic_sint { 603 u64 as_uint64; 604 struct { 605 u64 vector : 8; 606 u64 reserved1 : 8; 607 u64 masked : 1; 608 u64 auto_eoi : 1; 609 u64 polling : 1; 610 u64 as_intercept : 1; 611 u64 proxy : 1; 612 u64 reserved2 : 43; 613 } __packed; 614 }; 615 616 union hv_x64_xsave_xfem_register { 617 u64 as_uint64; 618 struct { 619 u32 low_uint32; 620 u32 high_uint32; 621 } __packed; 622 struct { 623 u64 legacy_x87 : 1; 624 u64 legacy_sse : 1; 625 u64 avx : 1; 626 u64 mpx_bndreg : 1; 627 u64 mpx_bndcsr : 1; 628 u64 avx_512_op_mask : 1; 629 u64 avx_512_zmmhi : 1; 630 u64 avx_512_zmm16_31 : 1; 631 u64 rsvd8_9 : 2; 632 u64 pasid : 1; 633 u64 cet_u : 1; 634 u64 cet_s : 1; 635 u64 rsvd13_16 : 4; 636 u64 xtile_cfg : 1; 637 u64 xtile_data : 1; 638 u64 rsvd19_63 : 45; 639 } __packed; 640 }; 641 642 /* Synthetic timer configuration */ 643 union hv_stimer_config { /* HV_X64_MSR_STIMER_CONFIG_CONTENTS */ 644 u64 as_uint64; 645 struct { 646 u64 enable : 1; 647 u64 periodic : 1; 648 u64 lazy : 1; 649 u64 auto_enable : 1; 650 u64 apic_vector : 8; 651 u64 direct_mode : 1; 652 u64 reserved_z0 : 3; 653 u64 sintx : 4; 654 u64 reserved_z1 : 44; 655 } __packed; 656 }; 657 658 /* Define the number of synthetic timers */ 659 #define HV_SYNIC_STIMER_COUNT (4) 660 661 /* Define port identifier type. */ 662 union hv_port_id { 663 u32 asu32; 664 struct { 665 u32 id : 24; 666 u32 reserved : 8; 667 } __packed u; 668 }; 669 670 #define HV_MESSAGE_SIZE (256) 671 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 672 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 673 674 /* Define hypervisor message types. */ 675 enum hv_message_type { 676 HVMSG_NONE = 0x00000000, 677 678 /* Memory access messages. */ 679 HVMSG_UNMAPPED_GPA = 0x80000000, 680 HVMSG_GPA_INTERCEPT = 0x80000001, 681 682 /* Timer notification messages. */ 683 HVMSG_TIMER_EXPIRED = 0x80000010, 684 685 /* Error messages. */ 686 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 687 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 688 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 689 690 /* 691 * Opaque intercept message. The original intercept message is only 692 * accessible from the mapped intercept message page. 693 */ 694 HVMSG_OPAQUE_INTERCEPT = 0x8000003F, 695 696 /* Trace buffer complete messages. */ 697 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 698 699 /* Hypercall intercept */ 700 HVMSG_HYPERCALL_INTERCEPT = 0x80000050, 701 702 /* SynIC intercepts */ 703 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060, 704 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061, 705 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062, 706 707 /* Async call completion intercept */ 708 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070, 709 710 /* Root scheduler messages */ 711 HVMSG_SCHEDULER_VP_SIGNAL_BITSET = 0x80000100, 712 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101, 713 714 /* Platform-specific processor intercept messages. */ 715 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000, 716 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 717 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 718 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 719 HVMSG_X64_APIC_EOI = 0x80010004, 720 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005, 721 HVMSG_X64_IOMMU_PRQ = 0x80010006, 722 HVMSG_X64_HALT = 0x80010007, 723 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008, 724 HVMSG_X64_SIPI_INTERCEPT = 0x80010009, 725 }; 726 727 /* Define the format of the SIMP register */ 728 union hv_synic_simp { 729 u64 as_uint64; 730 struct { 731 u64 simp_enabled : 1; 732 u64 preserved : 11; 733 u64 base_simp_gpa : 52; 734 } __packed; 735 }; 736 737 union hv_message_flags { 738 u8 asu8; 739 struct { 740 u8 msg_pending : 1; 741 u8 reserved : 7; 742 } __packed; 743 }; 744 745 struct hv_message_header { 746 u32 message_type; 747 u8 payload_size; 748 union hv_message_flags message_flags; 749 u8 reserved[2]; 750 union { 751 u64 sender; 752 union hv_port_id port; 753 }; 754 } __packed; 755 756 /* 757 * Message format for notifications delivered via 758 * intercept message(as_intercept=1) 759 */ 760 struct hv_notification_message_payload { 761 u32 sint_index; 762 } __packed; 763 764 struct hv_message { 765 struct hv_message_header header; 766 union { 767 u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 768 } u; 769 } __packed; 770 771 /* Define the synthetic interrupt message page layout. */ 772 struct hv_message_page { 773 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 774 } __packed; 775 776 /* Define timer message payload structure. */ 777 struct hv_timer_message_payload { 778 __u32 timer_index; 779 __u32 reserved; 780 __u64 expiration_time; /* When the timer expired */ 781 __u64 delivery_time; /* When the message was delivered */ 782 } __packed; 783 784 struct hv_x64_segment_register { 785 u64 base; 786 u32 limit; 787 u16 selector; 788 union { 789 struct { 790 u16 segment_type : 4; 791 u16 non_system_segment : 1; 792 u16 descriptor_privilege_level : 2; 793 u16 present : 1; 794 u16 reserved : 4; 795 u16 available : 1; 796 u16 _long : 1; 797 u16 _default : 1; 798 u16 granularity : 1; 799 } __packed; 800 u16 attributes; 801 }; 802 } __packed; 803 804 struct hv_x64_table_register { 805 u16 pad[3]; 806 u16 limit; 807 u64 base; 808 } __packed; 809 810 union hv_input_vtl { 811 u8 as_uint8; 812 struct { 813 u8 target_vtl : 4; 814 u8 use_target_vtl : 1; 815 u8 reserved_z : 3; 816 }; 817 } __packed; 818 819 struct hv_init_vp_context { 820 u64 rip; 821 u64 rsp; 822 u64 rflags; 823 824 struct hv_x64_segment_register cs; 825 struct hv_x64_segment_register ds; 826 struct hv_x64_segment_register es; 827 struct hv_x64_segment_register fs; 828 struct hv_x64_segment_register gs; 829 struct hv_x64_segment_register ss; 830 struct hv_x64_segment_register tr; 831 struct hv_x64_segment_register ldtr; 832 833 struct hv_x64_table_register idtr; 834 struct hv_x64_table_register gdtr; 835 836 u64 efer; 837 u64 cr0; 838 u64 cr3; 839 u64 cr4; 840 u64 msr_cr_pat; 841 } __packed; 842 843 struct hv_enable_vp_vtl { 844 u64 partition_id; 845 u32 vp_index; 846 union hv_input_vtl target_vtl; 847 u8 mbz0; 848 u16 mbz1; 849 struct hv_init_vp_context vp_context; 850 } __packed; 851 852 struct hv_get_vp_from_apic_id_in { 853 u64 partition_id; 854 union hv_input_vtl target_vtl; 855 u8 res[7]; 856 u32 apic_ids[]; 857 } __packed; 858 859 struct hv_nested_enlightenments_control { 860 struct { 861 u32 directhypercall : 1; 862 u32 reserved : 31; 863 } __packed features; 864 struct { 865 u32 inter_partition_comm : 1; 866 u32 reserved : 31; 867 } __packed hypercall_controls; 868 } __packed; 869 870 /* Define virtual processor assist page structure. */ 871 struct hv_vp_assist_page { 872 u32 apic_assist; 873 u32 reserved1; 874 u32 vtl_entry_reason; 875 u32 vtl_reserved; 876 u64 vtl_ret_x64rax; 877 u64 vtl_ret_x64rcx; 878 struct hv_nested_enlightenments_control nested_control; 879 u8 enlighten_vmentry; 880 u8 reserved2[7]; 881 u64 current_nested_vmcs; 882 u8 synthetic_time_unhalted_timer_expired; 883 u8 reserved3[7]; 884 u8 virtualization_fault_information[40]; 885 u8 reserved4[8]; 886 u8 intercept_message[256]; 887 u8 vtl_ret_actions[256]; 888 } __packed; 889 890 enum hv_register_name { 891 /* Suspend Registers */ 892 HV_REGISTER_EXPLICIT_SUSPEND = 0x00000000, 893 HV_REGISTER_INTERCEPT_SUSPEND = 0x00000001, 894 HV_REGISTER_DISPATCH_SUSPEND = 0x00000003, 895 896 /* Version - 128-bit result same as CPUID 0x40000002 */ 897 HV_REGISTER_HYPERVISOR_VERSION = 0x00000100, 898 899 /* Feature Access (registers are 128 bits) - same as CPUID 0x40000003 - 0x4000000B */ 900 HV_REGISTER_PRIVILEGES_AND_FEATURES_INFO = 0x00000200, 901 HV_REGISTER_FEATURES_INFO = 0x00000201, 902 HV_REGISTER_IMPLEMENTATION_LIMITS_INFO = 0x00000202, 903 HV_REGISTER_HARDWARE_FEATURES_INFO = 0x00000203, 904 HV_REGISTER_CPU_MANAGEMENT_FEATURES_INFO = 0x00000204, 905 HV_REGISTER_SVM_FEATURES_INFO = 0x00000205, 906 HV_REGISTER_SKIP_LEVEL_FEATURES_INFO = 0x00000206, 907 HV_REGISTER_NESTED_VIRT_FEATURES_INFO = 0x00000207, 908 HV_REGISTER_IPT_FEATURES_INFO = 0x00000208, 909 910 /* Guest Crash Registers */ 911 HV_REGISTER_GUEST_CRASH_P0 = 0x00000210, 912 HV_REGISTER_GUEST_CRASH_P1 = 0x00000211, 913 HV_REGISTER_GUEST_CRASH_P2 = 0x00000212, 914 HV_REGISTER_GUEST_CRASH_P3 = 0x00000213, 915 HV_REGISTER_GUEST_CRASH_P4 = 0x00000214, 916 HV_REGISTER_GUEST_CRASH_CTL = 0x00000215, 917 918 /* Misc */ 919 HV_REGISTER_VP_RUNTIME = 0x00090000, 920 HV_REGISTER_GUEST_OS_ID = 0x00090002, 921 HV_REGISTER_VP_INDEX = 0x00090003, 922 HV_REGISTER_TIME_REF_COUNT = 0x00090004, 923 HV_REGISTER_CPU_MANAGEMENT_VERSION = 0x00090007, 924 HV_REGISTER_VP_ASSIST_PAGE = 0x00090013, 925 HV_REGISTER_VP_ROOT_SIGNAL_COUNT = 0x00090014, 926 HV_REGISTER_REFERENCE_TSC = 0x00090017, 927 928 /* Hypervisor-defined Registers (Synic) */ 929 HV_REGISTER_SINT0 = 0x000A0000, 930 HV_REGISTER_SINT1 = 0x000A0001, 931 HV_REGISTER_SINT2 = 0x000A0002, 932 HV_REGISTER_SINT3 = 0x000A0003, 933 HV_REGISTER_SINT4 = 0x000A0004, 934 HV_REGISTER_SINT5 = 0x000A0005, 935 HV_REGISTER_SINT6 = 0x000A0006, 936 HV_REGISTER_SINT7 = 0x000A0007, 937 HV_REGISTER_SINT8 = 0x000A0008, 938 HV_REGISTER_SINT9 = 0x000A0009, 939 HV_REGISTER_SINT10 = 0x000A000A, 940 HV_REGISTER_SINT11 = 0x000A000B, 941 HV_REGISTER_SINT12 = 0x000A000C, 942 HV_REGISTER_SINT13 = 0x000A000D, 943 HV_REGISTER_SINT14 = 0x000A000E, 944 HV_REGISTER_SINT15 = 0x000A000F, 945 HV_REGISTER_SCONTROL = 0x000A0010, 946 HV_REGISTER_SVERSION = 0x000A0011, 947 HV_REGISTER_SIEFP = 0x000A0012, 948 HV_REGISTER_SIMP = 0x000A0013, 949 HV_REGISTER_EOM = 0x000A0014, 950 HV_REGISTER_SIRBP = 0x000A0015, 951 952 HV_REGISTER_NESTED_SINT0 = 0x000A1000, 953 HV_REGISTER_NESTED_SINT1 = 0x000A1001, 954 HV_REGISTER_NESTED_SINT2 = 0x000A1002, 955 HV_REGISTER_NESTED_SINT3 = 0x000A1003, 956 HV_REGISTER_NESTED_SINT4 = 0x000A1004, 957 HV_REGISTER_NESTED_SINT5 = 0x000A1005, 958 HV_REGISTER_NESTED_SINT6 = 0x000A1006, 959 HV_REGISTER_NESTED_SINT7 = 0x000A1007, 960 HV_REGISTER_NESTED_SINT8 = 0x000A1008, 961 HV_REGISTER_NESTED_SINT9 = 0x000A1009, 962 HV_REGISTER_NESTED_SINT10 = 0x000A100A, 963 HV_REGISTER_NESTED_SINT11 = 0x000A100B, 964 HV_REGISTER_NESTED_SINT12 = 0x000A100C, 965 HV_REGISTER_NESTED_SINT13 = 0x000A100D, 966 HV_REGISTER_NESTED_SINT14 = 0x000A100E, 967 HV_REGISTER_NESTED_SINT15 = 0x000A100F, 968 HV_REGISTER_NESTED_SCONTROL = 0x000A1010, 969 HV_REGISTER_NESTED_SVERSION = 0x000A1011, 970 HV_REGISTER_NESTED_SIFP = 0x000A1012, 971 HV_REGISTER_NESTED_SIPP = 0x000A1013, 972 HV_REGISTER_NESTED_EOM = 0x000A1014, 973 HV_REGISTER_NESTED_SIRBP = 0x000a1015, 974 975 /* Hypervisor-defined Registers (Synthetic Timers) */ 976 HV_REGISTER_STIMER0_CONFIG = 0x000B0000, 977 HV_REGISTER_STIMER0_COUNT = 0x000B0001, 978 979 /* VSM */ 980 HV_REGISTER_VSM_VP_STATUS = 0x000D0003, 981 }; 982 983 /* 984 * Arch compatibility regs for use with hv_set/get_register 985 */ 986 #if defined(CONFIG_X86) 987 988 /* 989 * To support arch-generic code calling hv_set/get_register: 990 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrl/wrmsrl 991 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall 992 */ 993 #define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0) 994 #define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1) 995 #define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2) 996 #define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3) 997 #define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4) 998 #define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL) 999 1000 #define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX) 1001 #define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT) 1002 #define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC) 1003 1004 #define HV_MSR_SINT0 (HV_X64_MSR_SINT0) 1005 #define HV_MSR_SVERSION (HV_X64_MSR_SVERSION) 1006 #define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL) 1007 #define HV_MSR_SIEFP (HV_X64_MSR_SIEFP) 1008 #define HV_MSR_SIMP (HV_X64_MSR_SIMP) 1009 #define HV_MSR_EOM (HV_X64_MSR_EOM) 1010 #define HV_MSR_SIRBP (HV_X64_MSR_SIRBP) 1011 1012 #define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL) 1013 #define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION) 1014 #define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP) 1015 #define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP) 1016 #define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM) 1017 #define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0) 1018 1019 #define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG) 1020 #define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT) 1021 1022 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1023 1024 #define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0) 1025 #define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1) 1026 #define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2) 1027 #define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3) 1028 #define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4) 1029 #define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL) 1030 1031 #define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX) 1032 #define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT) 1033 #define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC) 1034 1035 #define HV_MSR_SINT0 (HV_REGISTER_SINT0) 1036 #define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL) 1037 #define HV_MSR_SIEFP (HV_REGISTER_SIEFP) 1038 #define HV_MSR_SIMP (HV_REGISTER_SIMP) 1039 #define HV_MSR_EOM (HV_REGISTER_EOM) 1040 #define HV_MSR_SIRBP (HV_REGISTER_SIRBP) 1041 1042 #define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) 1043 #define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) 1044 1045 #endif /* CONFIG_ARM64 */ 1046 1047 union hv_explicit_suspend_register { 1048 u64 as_uint64; 1049 struct { 1050 u64 suspended : 1; 1051 u64 reserved : 63; 1052 } __packed; 1053 }; 1054 1055 union hv_intercept_suspend_register { 1056 u64 as_uint64; 1057 struct { 1058 u64 suspended : 1; 1059 u64 reserved : 63; 1060 } __packed; 1061 }; 1062 1063 union hv_dispatch_suspend_register { 1064 u64 as_uint64; 1065 struct { 1066 u64 suspended : 1; 1067 u64 reserved : 63; 1068 } __packed; 1069 }; 1070 1071 union hv_arm64_pending_interruption_register { 1072 u64 as_uint64; 1073 struct { 1074 u64 interruption_pending : 1; 1075 u64 interruption_type: 1; 1076 u64 reserved : 30; 1077 u64 error_code : 32; 1078 } __packed; 1079 }; 1080 1081 union hv_arm64_interrupt_state_register { 1082 u64 as_uint64; 1083 struct { 1084 u64 interrupt_shadow : 1; 1085 u64 reserved : 63; 1086 } __packed; 1087 }; 1088 1089 union hv_arm64_pending_synthetic_exception_event { 1090 u64 as_uint64[2]; 1091 struct { 1092 u8 event_pending : 1; 1093 u8 event_type : 3; 1094 u8 reserved : 4; 1095 u8 rsvd[3]; 1096 u32 exception_type; 1097 u64 context; 1098 } __packed; 1099 }; 1100 1101 union hv_x64_interrupt_state_register { 1102 u64 as_uint64; 1103 struct { 1104 u64 interrupt_shadow : 1; 1105 u64 nmi_masked : 1; 1106 u64 reserved : 62; 1107 } __packed; 1108 }; 1109 1110 union hv_x64_pending_interruption_register { 1111 u64 as_uint64; 1112 struct { 1113 u32 interruption_pending : 1; 1114 u32 interruption_type : 3; 1115 u32 deliver_error_code : 1; 1116 u32 instruction_length : 4; 1117 u32 nested_event : 1; 1118 u32 reserved : 6; 1119 u32 interruption_vector : 16; 1120 u32 error_code; 1121 } __packed; 1122 }; 1123 1124 union hv_register_value { 1125 struct hv_u128 reg128; 1126 u64 reg64; 1127 u32 reg32; 1128 u16 reg16; 1129 u8 reg8; 1130 1131 struct hv_x64_segment_register segment; 1132 struct hv_x64_table_register table; 1133 union hv_explicit_suspend_register explicit_suspend; 1134 union hv_intercept_suspend_register intercept_suspend; 1135 union hv_dispatch_suspend_register dispatch_suspend; 1136 #ifdef CONFIG_ARM64 1137 union hv_arm64_interrupt_state_register interrupt_state; 1138 union hv_arm64_pending_interruption_register pending_interruption; 1139 #endif 1140 #ifdef CONFIG_X86 1141 union hv_x64_interrupt_state_register interrupt_state; 1142 union hv_x64_pending_interruption_register pending_interruption; 1143 #endif 1144 union hv_arm64_pending_synthetic_exception_event pending_synthetic_exception_event; 1145 }; 1146 1147 /* NOTE: Linux helper struct - NOT from Hyper-V code. */ 1148 struct hv_output_get_vp_registers { 1149 DECLARE_FLEX_ARRAY(union hv_register_value, values); 1150 }; 1151 1152 #if defined(CONFIG_ARM64) 1153 /* HvGetVpRegisters returns an array of these output elements */ 1154 struct hv_get_vp_registers_output { 1155 union { 1156 struct { 1157 u32 a; 1158 u32 b; 1159 u32 c; 1160 u32 d; 1161 } as32 __packed; 1162 struct { 1163 u64 low; 1164 u64 high; 1165 } as64 __packed; 1166 }; 1167 }; 1168 1169 #endif /* CONFIG_ARM64 */ 1170 1171 struct hv_register_assoc { 1172 u32 name; /* enum hv_register_name */ 1173 u32 reserved1; 1174 u64 reserved2; 1175 union hv_register_value value; 1176 } __packed; 1177 1178 struct hv_input_get_vp_registers { 1179 u64 partition_id; 1180 u32 vp_index; 1181 union hv_input_vtl input_vtl; 1182 u8 rsvd_z8; 1183 u16 rsvd_z16; 1184 u32 names[]; 1185 } __packed; 1186 1187 struct hv_input_set_vp_registers { 1188 u64 partition_id; 1189 u32 vp_index; 1190 union hv_input_vtl input_vtl; 1191 u8 rsvd_z8; 1192 u16 rsvd_z16; 1193 struct hv_register_assoc elements[]; 1194 } __packed; 1195 1196 #define HV_UNMAP_GPA_LARGE_PAGE 0x2 1197 1198 /* HvCallSendSyntheticClusterIpi hypercall */ 1199 struct hv_send_ipi { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI */ 1200 u32 vector; 1201 u32 reserved; 1202 u64 cpu_mask; 1203 } __packed; 1204 1205 #define HV_X64_VTL_MASK GENMASK(3, 0) 1206 1207 /* Hyper-V memory host visibility */ 1208 enum hv_mem_host_visibility { 1209 VMBUS_PAGE_NOT_VISIBLE = 0, 1210 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 1211 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 1212 }; 1213 1214 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 1215 #define HV_MAX_MODIFY_GPA_REP_COUNT ((HV_HYP_PAGE_SIZE / sizeof(u64)) - 2) 1216 struct hv_gpa_range_for_visibility { 1217 u64 partition_id; 1218 u32 host_visibility : 2; 1219 u32 reserved0 : 30; 1220 u32 reserved1; 1221 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 1222 } __packed; 1223 1224 #if defined(CONFIG_X86) 1225 union hv_msi_address_register { /* HV_MSI_ADDRESS */ 1226 u32 as_uint32; 1227 struct { 1228 u32 reserved1 : 2; 1229 u32 destination_mode : 1; 1230 u32 redirection_hint : 1; 1231 u32 reserved2 : 8; 1232 u32 destination_id : 8; 1233 u32 msi_base : 12; 1234 }; 1235 } __packed; 1236 1237 union hv_msi_data_register { /* HV_MSI_ENTRY.Data */ 1238 u32 as_uint32; 1239 struct { 1240 u32 vector : 8; 1241 u32 delivery_mode : 3; 1242 u32 reserved1 : 3; 1243 u32 level_assert : 1; 1244 u32 trigger_mode : 1; 1245 u32 reserved2 : 16; 1246 }; 1247 } __packed; 1248 1249 union hv_msi_entry { /* HV_MSI_ENTRY */ 1250 1251 u64 as_uint64; 1252 struct { 1253 union hv_msi_address_register address; 1254 union hv_msi_data_register data; 1255 } __packed; 1256 }; 1257 1258 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1259 1260 union hv_msi_entry { 1261 u64 as_uint64[2]; 1262 struct { 1263 u64 address; 1264 u32 data; 1265 u32 reserved; 1266 } __packed; 1267 }; 1268 #endif /* CONFIG_ARM64 */ 1269 1270 union hv_ioapic_rte { 1271 u64 as_uint64; 1272 1273 struct { 1274 u32 vector : 8; 1275 u32 delivery_mode : 3; 1276 u32 destination_mode : 1; 1277 u32 delivery_status : 1; 1278 u32 interrupt_polarity : 1; 1279 u32 remote_irr : 1; 1280 u32 trigger_mode : 1; 1281 u32 interrupt_mask : 1; 1282 u32 reserved1 : 15; 1283 1284 u32 reserved2 : 24; 1285 u32 destination_id : 8; 1286 }; 1287 1288 struct { 1289 u32 low_uint32; 1290 u32 high_uint32; 1291 }; 1292 } __packed; 1293 1294 enum hv_interrupt_source { /* HV_INTERRUPT_SOURCE */ 1295 HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */ 1296 HV_INTERRUPT_SOURCE_IOAPIC, 1297 }; 1298 1299 struct hv_interrupt_entry { /* HV_INTERRUPT_ENTRY */ 1300 u32 source; 1301 u32 reserved1; 1302 union { 1303 union hv_msi_entry msi_entry; 1304 union hv_ioapic_rte ioapic_rte; 1305 }; 1306 } __packed; 1307 1308 #define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1 1309 #define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2 1310 1311 struct hv_device_interrupt_target { /* HV_DEVICE_INTERRUPT_TARGET */ 1312 u32 vector; 1313 u32 flags; /* HV_DEVICE_INTERRUPT_TARGET_* above */ 1314 union { 1315 u64 vp_mask; 1316 struct hv_vpset vp_set; 1317 }; 1318 } __packed; 1319 1320 struct hv_retarget_device_interrupt { /* HV_INPUT_RETARGET_DEVICE_INTERRUPT */ 1321 u64 partition_id; /* use "self" */ 1322 u64 device_id; 1323 struct hv_interrupt_entry int_entry; 1324 u64 reserved2; 1325 struct hv_device_interrupt_target int_target; 1326 } __packed __aligned(8); 1327 1328 /* Data structures for HVCALL_MMIO_READ and HVCALL_MMIO_WRITE */ 1329 #define HV_HYPERCALL_MMIO_MAX_DATA_LENGTH 64 1330 1331 struct hv_mmio_read_input { /* HV_INPUT_MEMORY_MAPPED_IO_READ */ 1332 u64 gpa; 1333 u32 size; 1334 u32 reserved; 1335 } __packed; 1336 1337 struct hv_mmio_read_output { 1338 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1339 } __packed; 1340 1341 struct hv_mmio_write_input { 1342 u64 gpa; 1343 u32 size; 1344 u32 reserved; 1345 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1346 } __packed; 1347 1348 #endif /* _HV_HVGDK_MINI_H */ 1349