1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Balsam CHIHI <[email protected]>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
10 #include <linux/debugfs.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/thermal.h>
20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21
22 #include "../thermal_hwmon.h"
23
24 #define LVTS_MONCTL0(__base) (__base + 0x0000)
25 #define LVTS_MONCTL1(__base) (__base + 0x0004)
26 #define LVTS_MONCTL2(__base) (__base + 0x0008)
27 #define LVTS_MONINT(__base) (__base + 0x000C)
28 #define LVTS_MONINTSTS(__base) (__base + 0x0010)
29 #define LVTS_MONIDET0(__base) (__base + 0x0014)
30 #define LVTS_MONIDET1(__base) (__base + 0x0018)
31 #define LVTS_MONIDET2(__base) (__base + 0x001C)
32 #define LVTS_MONIDET3(__base) (__base + 0x0020)
33 #define LVTS_H2NTHRE(__base) (__base + 0x0024)
34 #define LVTS_HTHRE(__base) (__base + 0x0028)
35 #define LVTS_OFFSETH(__base) (__base + 0x0030)
36 #define LVTS_OFFSETL(__base) (__base + 0x0034)
37 #define LVTS_MSRCTL0(__base) (__base + 0x0038)
38 #define LVTS_MSRCTL1(__base) (__base + 0x003C)
39 #define LVTS_TSSEL(__base) (__base + 0x0040)
40 #define LVTS_CALSCALE(__base) (__base + 0x0048)
41 #define LVTS_ID(__base) (__base + 0x004C)
42 #define LVTS_CONFIG(__base) (__base + 0x0050)
43 #define LVTS_EDATA00(__base) (__base + 0x0054)
44 #define LVTS_EDATA01(__base) (__base + 0x0058)
45 #define LVTS_EDATA02(__base) (__base + 0x005C)
46 #define LVTS_EDATA03(__base) (__base + 0x0060)
47 #define LVTS_MSR0(__base) (__base + 0x0090)
48 #define LVTS_MSR1(__base) (__base + 0x0094)
49 #define LVTS_MSR2(__base) (__base + 0x0098)
50 #define LVTS_MSR3(__base) (__base + 0x009C)
51 #define LVTS_IMMD0(__base) (__base + 0x00A0)
52 #define LVTS_IMMD1(__base) (__base + 0x00A4)
53 #define LVTS_IMMD2(__base) (__base + 0x00A8)
54 #define LVTS_IMMD3(__base) (__base + 0x00AC)
55 #define LVTS_PROTCTL(__base) (__base + 0x00C0)
56 #define LVTS_PROTTA(__base) (__base + 0x00C4)
57 #define LVTS_PROTTB(__base) (__base + 0x00C8)
58 #define LVTS_PROTTC(__base) (__base + 0x00CC)
59 #define LVTS_CLKEN(__base) (__base + 0x00E4)
60
61 #define LVTS_PERIOD_UNIT 0
62 #define LVTS_GROUP_INTERVAL 0
63 #define LVTS_FILTER_INTERVAL 0
64 #define LVTS_SENSOR_INTERVAL 0
65 #define LVTS_HW_FILTER 0x0
66 #define LVTS_TSSEL_CONF 0x13121110
67 #define LVTS_CALSCALE_CONF 0x300
68 #define LVTS_MONINT_CONF 0x0300318C
69
70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC
71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180
72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000
73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000
74
75 #define LVTS_INT_SENSOR0 0x0009001F
76 #define LVTS_INT_SENSOR1 0x001203E0
77 #define LVTS_INT_SENSOR2 0x00247C00
78 #define LVTS_INT_SENSOR3 0x1FC00000
79
80 #define LVTS_SENSOR_MAX 4
81 #define LVTS_GOLDEN_TEMP_MAX 62
82 #define LVTS_GOLDEN_TEMP_DEFAULT 50
83 #define LVTS_COEFF_A_MT8195 -250460
84 #define LVTS_COEFF_B_MT8195 250460
85 #define LVTS_COEFF_A_MT7988 -204650
86 #define LVTS_COEFF_B_MT7988 204650
87
88 #define LVTS_MSR_IMMEDIATE_MODE 0
89 #define LVTS_MSR_FILTERED_MODE 1
90
91 #define LVTS_MSR_READ_TIMEOUT_US 400
92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
93
94 #define LVTS_MINIMUM_THRESHOLD 20000
95
96 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
97 static int golden_temp_offset;
98
99 struct lvts_sensor_data {
100 int dt_id;
101 u8 cal_offsets[3];
102 };
103
104 struct lvts_ctrl_data {
105 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
106 u8 valid_sensor_mask;
107 int offset;
108 int mode;
109 };
110
111 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \
112 .valid_sensor_mask = (((s0) ? BIT(0) : 0) | \
113 ((s1) ? BIT(1) : 0) | \
114 ((s2) ? BIT(2) : 0) | \
115 ((s3) ? BIT(3) : 0))
116
117 #define lvts_for_each_valid_sensor(i, lvts_ctrl) \
118 for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \
119 if (!((lvts_ctrl)->valid_sensor_mask & BIT(i))) \
120 continue; \
121 else
122
123 struct lvts_data {
124 const struct lvts_ctrl_data *lvts_ctrl;
125 int num_lvts_ctrl;
126 int temp_factor;
127 int temp_offset;
128 int gt_calib_bit_offset;
129 unsigned int def_calibration;
130 };
131
132 struct lvts_sensor {
133 struct thermal_zone_device *tz;
134 void __iomem *msr;
135 void __iomem *base;
136 int id;
137 int dt_id;
138 int low_thresh;
139 int high_thresh;
140 };
141
142 struct lvts_ctrl {
143 struct lvts_sensor sensors[LVTS_SENSOR_MAX];
144 const struct lvts_data *lvts_data;
145 u32 calibration[LVTS_SENSOR_MAX];
146 u8 valid_sensor_mask;
147 int mode;
148 void __iomem *base;
149 int low_thresh;
150 int high_thresh;
151 };
152
153 struct lvts_domain {
154 struct lvts_ctrl *lvts_ctrl;
155 struct reset_control *reset;
156 struct clk *clk;
157 int num_lvts_ctrl;
158 void __iomem *base;
159 size_t calib_len;
160 u8 *calib;
161 #ifdef CONFIG_DEBUG_FS
162 struct dentry *dom_dentry;
163 #endif
164 };
165
166 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
167
168 #define LVTS_DEBUG_FS_REGS(__reg) \
169 { \
170 .name = __stringify(__reg), \
171 .offset = __reg(0), \
172 }
173
174 static const struct debugfs_reg32 lvts_regs[] = {
175 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
176 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
177 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
178 LVTS_DEBUG_FS_REGS(LVTS_MONINT),
179 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
180 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
181 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
182 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
183 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
184 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
185 LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
186 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
187 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
188 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
189 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
190 LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
191 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
192 LVTS_DEBUG_FS_REGS(LVTS_ID),
193 LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
194 LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
195 LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
196 LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
197 LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
198 LVTS_DEBUG_FS_REGS(LVTS_MSR0),
199 LVTS_DEBUG_FS_REGS(LVTS_MSR1),
200 LVTS_DEBUG_FS_REGS(LVTS_MSR2),
201 LVTS_DEBUG_FS_REGS(LVTS_MSR3),
202 LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
203 LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
204 LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
205 LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
206 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
207 LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
208 LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
209 LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
210 LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
211 };
212
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)213 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
214 {
215 struct debugfs_regset32 *regset;
216 struct lvts_ctrl *lvts_ctrl;
217 struct dentry *dentry;
218 char name[64];
219 int i;
220
221 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
222 if (IS_ERR(lvts_td->dom_dentry))
223 return 0;
224
225 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
226
227 lvts_ctrl = &lvts_td->lvts_ctrl[i];
228
229 sprintf(name, "controller%d", i);
230 dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
231 if (IS_ERR(dentry))
232 continue;
233
234 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
235 if (!regset)
236 continue;
237
238 regset->base = lvts_ctrl->base;
239 regset->regs = lvts_regs;
240 regset->nregs = ARRAY_SIZE(lvts_regs);
241
242 debugfs_create_regset32("registers", 0400, dentry, regset);
243 }
244
245 return 0;
246 }
247
lvts_debugfs_exit(struct lvts_domain * lvts_td)248 static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
249 {
250 debugfs_remove_recursive(lvts_td->dom_dentry);
251 }
252
253 #else
254
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)255 static inline int lvts_debugfs_init(struct device *dev,
256 struct lvts_domain *lvts_td)
257 {
258 return 0;
259 }
260
lvts_debugfs_exit(struct lvts_domain * lvts_td)261 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
262
263 #endif
264
lvts_raw_to_temp(u32 raw_temp,int temp_factor)265 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
266 {
267 int temperature;
268
269 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
270 temperature += golden_temp_offset;
271
272 return temperature;
273 }
274
lvts_temp_to_raw(int temperature,int temp_factor)275 static u32 lvts_temp_to_raw(int temperature, int temp_factor)
276 {
277 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
278
279 raw_temp = div_s64(raw_temp, -temp_factor);
280
281 return raw_temp;
282 }
283
lvts_get_temp(struct thermal_zone_device * tz,int * temp)284 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
285 {
286 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
287 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
288 sensors[lvts_sensor->id]);
289 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
290 void __iomem *msr = lvts_sensor->msr;
291 u32 value;
292 int rc;
293
294 /*
295 * Measurement registers:
296 *
297 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
298 *
299 * Bits:
300 *
301 * 32-17: Unused
302 * 16 : Valid temperature
303 * 15-0 : Raw temperature
304 */
305 rc = readl_poll_timeout(msr, value, value & BIT(16),
306 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
307
308 /*
309 * As the thermal zone temperature will read before the
310 * hardware sensor is fully initialized, we have to check the
311 * validity of the temperature returned when reading the
312 * measurement register. The thermal controller will set the
313 * valid bit temperature only when it is totally initialized.
314 *
315 * Otherwise, we may end up with garbage values out of the
316 * functionning temperature and directly jump to a system
317 * shutdown.
318 */
319 if (rc)
320 return -EAGAIN;
321
322 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
323
324 return 0;
325 }
326
lvts_update_irq_mask(struct lvts_ctrl * lvts_ctrl)327 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
328 {
329 static const u32 masks[] = {
330 LVTS_MONINT_OFFSET_SENSOR0,
331 LVTS_MONINT_OFFSET_SENSOR1,
332 LVTS_MONINT_OFFSET_SENSOR2,
333 LVTS_MONINT_OFFSET_SENSOR3,
334 };
335 u32 value = 0;
336 int i;
337
338 value = readl(LVTS_MONINT(lvts_ctrl->base));
339
340 for (i = 0; i < ARRAY_SIZE(masks); i++) {
341 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
342 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
343 value |= masks[i];
344 else
345 value &= ~masks[i];
346 }
347
348 writel(value, LVTS_MONINT(lvts_ctrl->base));
349 }
350
lvts_should_update_thresh(struct lvts_ctrl * lvts_ctrl,int high)351 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
352 {
353 int i;
354
355 if (high > lvts_ctrl->high_thresh)
356 return true;
357
358 lvts_for_each_valid_sensor(i, lvts_ctrl)
359 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
360 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
361 return false;
362
363 return true;
364 }
365
lvts_set_trips(struct thermal_zone_device * tz,int low,int high)366 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
367 {
368 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
369 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
370 sensors[lvts_sensor->id]);
371 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
372 void __iomem *base = lvts_sensor->base;
373 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
374 lvts_data->temp_factor);
375 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
376 bool should_update_thresh;
377
378 lvts_sensor->low_thresh = low;
379 lvts_sensor->high_thresh = high;
380
381 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
382 if (should_update_thresh) {
383 lvts_ctrl->high_thresh = high;
384 lvts_ctrl->low_thresh = low;
385 }
386 lvts_update_irq_mask(lvts_ctrl);
387
388 if (!should_update_thresh)
389 return 0;
390
391 /*
392 * Low offset temperature threshold
393 *
394 * LVTS_OFFSETL
395 *
396 * Bits:
397 *
398 * 14-0 : Raw temperature for threshold
399 */
400 pr_debug("%s: Setting low limit temperature interrupt: %d\n",
401 thermal_zone_device_type(tz), low);
402 writel(raw_low, LVTS_OFFSETL(base));
403
404 /*
405 * High offset temperature threshold
406 *
407 * LVTS_OFFSETH
408 *
409 * Bits:
410 *
411 * 14-0 : Raw temperature for threshold
412 */
413 pr_debug("%s: Setting high limit temperature interrupt: %d\n",
414 thermal_zone_device_type(tz), high);
415 writel(raw_high, LVTS_OFFSETH(base));
416
417 return 0;
418 }
419
lvts_ctrl_irq_handler(struct lvts_ctrl * lvts_ctrl)420 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
421 {
422 irqreturn_t iret = IRQ_NONE;
423 u32 value;
424 static const u32 masks[] = {
425 LVTS_INT_SENSOR0,
426 LVTS_INT_SENSOR1,
427 LVTS_INT_SENSOR2,
428 LVTS_INT_SENSOR3
429 };
430 int i;
431
432 /*
433 * Interrupt monitoring status
434 *
435 * LVTS_MONINTST
436 *
437 * Bits:
438 *
439 * 31 : Interrupt for stage 3
440 * 30 : Interrupt for stage 2
441 * 29 : Interrupt for state 1
442 * 28 : Interrupt using filter on sensor 3
443 *
444 * 27 : Interrupt using immediate on sensor 3
445 * 26 : Interrupt normal to hot on sensor 3
446 * 25 : Interrupt high offset on sensor 3
447 * 24 : Interrupt low offset on sensor 3
448 *
449 * 23 : Interrupt hot threshold on sensor 3
450 * 22 : Interrupt cold threshold on sensor 3
451 * 21 : Interrupt using filter on sensor 2
452 * 20 : Interrupt using filter on sensor 1
453 *
454 * 19 : Interrupt using filter on sensor 0
455 * 18 : Interrupt using immediate on sensor 2
456 * 17 : Interrupt using immediate on sensor 1
457 * 16 : Interrupt using immediate on sensor 0
458 *
459 * 15 : Interrupt device access timeout interrupt
460 * 14 : Interrupt normal to hot on sensor 2
461 * 13 : Interrupt high offset interrupt on sensor 2
462 * 12 : Interrupt low offset interrupt on sensor 2
463 *
464 * 11 : Interrupt hot threshold on sensor 2
465 * 10 : Interrupt cold threshold on sensor 2
466 * 9 : Interrupt normal to hot on sensor 1
467 * 8 : Interrupt high offset interrupt on sensor 1
468 *
469 * 7 : Interrupt low offset interrupt on sensor 1
470 * 6 : Interrupt hot threshold on sensor 1
471 * 5 : Interrupt cold threshold on sensor 1
472 * 4 : Interrupt normal to hot on sensor 0
473 *
474 * 3 : Interrupt high offset interrupt on sensor 0
475 * 2 : Interrupt low offset interrupt on sensor 0
476 * 1 : Interrupt hot threshold on sensor 0
477 * 0 : Interrupt cold threshold on sensor 0
478 *
479 * We are interested in the sensor(s) responsible of the
480 * interrupt event. We update the thermal framework with the
481 * thermal zone associated with the sensor. The framework will
482 * take care of the rest whatever the kind of interrupt, we
483 * are only interested in which sensor raised the interrupt.
484 *
485 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
486 * => 0x1FC00000
487 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
488 * => 0x00247C00
489 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
490 * => 0X001203E0
491 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
492 * => 0x0009001F
493 */
494 value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
495
496 /*
497 * Let's figure out which sensors raised the interrupt
498 *
499 * NOTE: the masks array must be ordered with the index
500 * corresponding to the sensor id eg. index=0, mask for
501 * sensor0.
502 */
503 for (i = 0; i < ARRAY_SIZE(masks); i++) {
504
505 if (!(value & masks[i]))
506 continue;
507
508 thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
509 THERMAL_TRIP_VIOLATED);
510 iret = IRQ_HANDLED;
511 }
512
513 /*
514 * Write back to clear the interrupt status (W1C)
515 */
516 writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
517
518 return iret;
519 }
520
521 /*
522 * Temperature interrupt handler. Even if the driver supports more
523 * interrupt modes, we use the interrupt when the temperature crosses
524 * the hot threshold the way up and the way down (modulo the
525 * hysteresis).
526 *
527 * Each thermal domain has a couple of interrupts, one for hardware
528 * reset and another one for all the thermal events happening on the
529 * different sensors.
530 *
531 * The interrupt is configured for thermal events when crossing the
532 * hot temperature limit. At each interrupt, we check in every
533 * controller if there is an interrupt pending.
534 */
lvts_irq_handler(int irq,void * data)535 static irqreturn_t lvts_irq_handler(int irq, void *data)
536 {
537 struct lvts_domain *lvts_td = data;
538 irqreturn_t aux, iret = IRQ_NONE;
539 int i;
540
541 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
542
543 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
544 if (aux != IRQ_HANDLED)
545 continue;
546
547 iret = IRQ_HANDLED;
548 }
549
550 return iret;
551 }
552
553 static struct thermal_zone_device_ops lvts_ops = {
554 .get_temp = lvts_get_temp,
555 .set_trips = lvts_set_trips,
556 };
557
lvts_sensor_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data)558 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
559 const struct lvts_ctrl_data *lvts_ctrl_data)
560 {
561 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
562
563 void __iomem *msr_regs[] = {
564 LVTS_MSR0(lvts_ctrl->base),
565 LVTS_MSR1(lvts_ctrl->base),
566 LVTS_MSR2(lvts_ctrl->base),
567 LVTS_MSR3(lvts_ctrl->base)
568 };
569
570 void __iomem *imm_regs[] = {
571 LVTS_IMMD0(lvts_ctrl->base),
572 LVTS_IMMD1(lvts_ctrl->base),
573 LVTS_IMMD2(lvts_ctrl->base),
574 LVTS_IMMD3(lvts_ctrl->base)
575 };
576
577 int i;
578
579 lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
580
581 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
582
583 /*
584 * At this point, we don't know which id matches which
585 * sensor. Let's set arbitrally the id from the index.
586 */
587 lvts_sensor[i].id = i;
588
589 /*
590 * The thermal zone registration will set the trip
591 * point interrupt in the thermal controller
592 * register. But this one will be reset in the
593 * initialization after. So we need to post pone the
594 * thermal zone creation after the controller is
595 * setup. For this reason, we store the device tree
596 * node id from the data in the sensor structure
597 */
598 lvts_sensor[i].dt_id = dt_id;
599
600 /*
601 * We assign the base address of the thermal
602 * controller as a back pointer. So it will be
603 * accessible from the different thermal framework ops
604 * as we pass the lvts_sensor pointer as thermal zone
605 * private data.
606 */
607 lvts_sensor[i].base = lvts_ctrl->base;
608
609 /*
610 * Each sensor has its own register address to read from.
611 */
612 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
613 imm_regs[i] : msr_regs[i];
614
615 lvts_sensor[i].low_thresh = INT_MIN;
616 lvts_sensor[i].high_thresh = INT_MIN;
617 };
618
619 lvts_ctrl->valid_sensor_mask = lvts_ctrl_data->valid_sensor_mask;
620
621 return 0;
622 }
623
624 /*
625 * The efuse blob values follows the sensor enumeration per thermal
626 * controller. The decoding of the stream is as follow:
627 *
628 * MT8192 :
629 * Stream index map for MCU Domain mt8192 :
630 *
631 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
632 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
633 *
634 * <-----sensor#2-----> <-----sensor#3----->
635 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
636 *
637 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
638 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
639 *
640 * Stream index map for AP Domain mt8192 :
641 *
642 * <-----sensor#0-----> <-----sensor#1----->
643 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
644 *
645 * <-----sensor#2-----> <-----sensor#3----->
646 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
647 *
648 * <-----sensor#4-----> <-----sensor#5----->
649 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
650 *
651 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
652 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
653 *
654 * MT8195 :
655 * Stream index map for MCU Domain mt8195 :
656 *
657 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
658 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
659 *
660 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
661 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
662 *
663 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
664 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
665 *
666 * Stream index map for AP Domain mt8195 :
667 *
668 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
669 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
670 *
671 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
672 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
673 *
674 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
675 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
676 *
677 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
678 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
679 *
680 * Note: In some cases, values don't strictly follow a little endian ordering.
681 * The data description gives byte offsets constituting each calibration value
682 * for each sensor.
683 */
lvts_calibration_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data,u8 * efuse_calibration,size_t calib_len)684 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
685 const struct lvts_ctrl_data *lvts_ctrl_data,
686 u8 *efuse_calibration,
687 size_t calib_len)
688 {
689 int i;
690 u32 gt;
691
692 /* A zero value for gt means that device has invalid efuse data */
693 gt = (((u32 *)efuse_calibration)[0] >> lvts_ctrl->lvts_data->gt_calib_bit_offset) & 0xff;
694
695 lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
696 const struct lvts_sensor_data *sensor =
697 &lvts_ctrl_data->lvts_sensor[i];
698
699 if (sensor->cal_offsets[0] >= calib_len ||
700 sensor->cal_offsets[1] >= calib_len ||
701 sensor->cal_offsets[2] >= calib_len)
702 return -EINVAL;
703
704 if (gt) {
705 lvts_ctrl->calibration[i] =
706 (efuse_calibration[sensor->cal_offsets[0]] << 0) +
707 (efuse_calibration[sensor->cal_offsets[1]] << 8) +
708 (efuse_calibration[sensor->cal_offsets[2]] << 16);
709 } else if (lvts_ctrl->lvts_data->def_calibration) {
710 lvts_ctrl->calibration[i] = lvts_ctrl->lvts_data->def_calibration;
711 } else {
712 dev_err(dev, "efuse contains invalid calibration data and no default given.\n");
713 return -ENODATA;
714 }
715 }
716
717 return 0;
718 }
719
720 /*
721 * The efuse bytes stream can be split into different chunk of
722 * nvmems. This function reads and concatenate those into a single
723 * buffer so it can be read sequentially when initializing the
724 * calibration data.
725 */
lvts_calibration_read(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)726 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
727 const struct lvts_data *lvts_data)
728 {
729 struct device_node *np = dev_of_node(dev);
730 struct nvmem_cell *cell;
731 struct property *prop;
732 const char *cell_name;
733
734 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
735 size_t len;
736 u8 *efuse;
737
738 cell = of_nvmem_cell_get(np, cell_name);
739 if (IS_ERR(cell)) {
740 dev_err(dev, "Failed to get cell '%s'\n", cell_name);
741 return PTR_ERR(cell);
742 }
743
744 efuse = nvmem_cell_read(cell, &len);
745
746 nvmem_cell_put(cell);
747
748 if (IS_ERR(efuse)) {
749 dev_err(dev, "Failed to read cell '%s'\n", cell_name);
750 return PTR_ERR(efuse);
751 }
752
753 lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
754 lvts_td->calib_len + len, GFP_KERNEL);
755 if (!lvts_td->calib) {
756 kfree(efuse);
757 return -ENOMEM;
758 }
759
760 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
761
762 lvts_td->calib_len += len;
763
764 kfree(efuse);
765 }
766
767 return 0;
768 }
769
lvts_golden_temp_init(struct device * dev,u8 * calib,const struct lvts_data * lvts_data)770 static int lvts_golden_temp_init(struct device *dev, u8 *calib,
771 const struct lvts_data *lvts_data)
772 {
773 u32 gt;
774
775 /*
776 * The golden temp information is contained in the first 32-bit
777 * word of efuse data at a specific bit offset.
778 */
779 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff;
780
781 /* A zero value for gt means that device has invalid efuse data */
782 if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
783 golden_temp = gt;
784
785 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset;
786
787 dev_info(dev, "%sgolden temp=%d\n", gt ? "" : "fake ", golden_temp);
788
789 return 0;
790 }
791
lvts_ctrl_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)792 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
793 const struct lvts_data *lvts_data)
794 {
795 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
796 struct lvts_ctrl *lvts_ctrl;
797 int i, ret;
798
799 /*
800 * Create the calibration bytes stream from efuse data
801 */
802 ret = lvts_calibration_read(dev, lvts_td, lvts_data);
803 if (ret)
804 return ret;
805
806 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data);
807 if (ret)
808 return ret;
809
810 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
811 if (!lvts_ctrl)
812 return -ENOMEM;
813
814 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
815
816 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
817 lvts_ctrl[i].lvts_data = lvts_data;
818
819 ret = lvts_sensor_init(dev, &lvts_ctrl[i],
820 &lvts_data->lvts_ctrl[i]);
821 if (ret)
822 return ret;
823
824 ret = lvts_calibration_init(dev, &lvts_ctrl[i],
825 &lvts_data->lvts_ctrl[i],
826 lvts_td->calib,
827 lvts_td->calib_len);
828 if (ret)
829 return ret;
830
831 /*
832 * The mode the ctrl will use to read the temperature
833 * (filtered or immediate)
834 */
835 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
836
837 lvts_ctrl[i].low_thresh = INT_MIN;
838 lvts_ctrl[i].high_thresh = INT_MIN;
839 }
840
841 /*
842 * We no longer need the efuse bytes stream, let's free it
843 */
844 devm_kfree(dev, lvts_td->calib);
845
846 lvts_td->lvts_ctrl = lvts_ctrl;
847 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
848
849 return 0;
850 }
851
lvts_ctrl_monitor_enable(struct device * dev,struct lvts_ctrl * lvts_ctrl,bool enable)852 static void lvts_ctrl_monitor_enable(struct device *dev, struct lvts_ctrl *lvts_ctrl, bool enable)
853 {
854 /*
855 * Bitmaps to enable each sensor on filtered mode in the MONCTL0
856 * register.
857 */
858 static const u8 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
859 u32 sensor_map = 0;
860 int i;
861
862 if (lvts_ctrl->mode != LVTS_MSR_FILTERED_MODE)
863 return;
864
865 if (enable) {
866 lvts_for_each_valid_sensor(i, lvts_ctrl)
867 sensor_map |= sensor_filt_bitmap[i];
868 }
869
870 /*
871 * Bits:
872 * 9: Single point access flow
873 * 0-3: Enable sensing point 0-3
874 */
875 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
876 }
877
878 /*
879 * At this point the configuration register is the only place in the
880 * driver where we write multiple values. Per hardware constraint,
881 * each write in the configuration register must be separated by a
882 * delay of 2 us.
883 */
lvts_write_config(struct lvts_ctrl * lvts_ctrl,u32 * cmds,int nr_cmds)884 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
885 {
886 int i;
887
888 /*
889 * Configuration register
890 */
891 for (i = 0; i < nr_cmds; i++) {
892 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
893 usleep_range(2, 4);
894 }
895 }
896
lvts_irq_init(struct lvts_ctrl * lvts_ctrl)897 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
898 {
899 /*
900 * LVTS_PROTCTL : Thermal Protection Sensor Selection
901 *
902 * Bits:
903 *
904 * 19-18 : Sensor to base the protection on
905 * 17-16 : Strategy:
906 * 00 : Average of 4 sensors
907 * 01 : Max of 4 sensors
908 * 10 : Selected sensor with bits 19-18
909 * 11 : Reserved
910 */
911
912 /*
913 * LVTS_PROTTA : Stage 1 temperature threshold
914 * LVTS_PROTTB : Stage 2 temperature threshold
915 * LVTS_PROTTC : Stage 3 temperature threshold
916 *
917 * Bits:
918 *
919 * 14-0: Raw temperature threshold
920 *
921 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
922 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
923 * writel(0x0, LVTS_PROTTC(lvts_ctrl->base));
924 */
925
926 /*
927 * LVTS_MONINT : Interrupt configuration register
928 *
929 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
930 * register, except we set the bits to enable the interrupt.
931 */
932 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
933
934 return 0;
935 }
936
lvts_domain_reset(struct device * dev,struct reset_control * reset)937 static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
938 {
939 int ret;
940
941 ret = reset_control_assert(reset);
942 if (ret)
943 return ret;
944
945 return reset_control_deassert(reset);
946 }
947
948 /*
949 * Enable or disable the clocks of a specified thermal controller
950 */
lvts_ctrl_set_enable(struct lvts_ctrl * lvts_ctrl,int enable)951 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
952 {
953 /*
954 * LVTS_CLKEN : Internal LVTS clock
955 *
956 * Bits:
957 *
958 * 0 : enable / disable clock
959 */
960 writel(enable, LVTS_CLKEN(lvts_ctrl->base));
961
962 return 0;
963 }
964
lvts_ctrl_connect(struct device * dev,struct lvts_ctrl * lvts_ctrl)965 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
966 {
967 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
968
969 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
970
971 /*
972 * LVTS_ID : Get ID and status of the thermal controller
973 *
974 * Bits:
975 *
976 * 0-5 : thermal controller id
977 * 7 : thermal controller connection is valid
978 */
979 id = readl(LVTS_ID(lvts_ctrl->base));
980 if (!(id & BIT(7)))
981 return -EIO;
982
983 return 0;
984 }
985
lvts_ctrl_initialize(struct device * dev,struct lvts_ctrl * lvts_ctrl)986 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
987 {
988 /*
989 * Write device mask: 0xC1030000
990 */
991 u32 cmds[] = {
992 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
993 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
994 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
995 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
996 };
997
998 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
999
1000 return 0;
1001 }
1002
lvts_ctrl_calibrate(struct device * dev,struct lvts_ctrl * lvts_ctrl)1003 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1004 {
1005 int i;
1006 void __iomem *lvts_edata[] = {
1007 LVTS_EDATA00(lvts_ctrl->base),
1008 LVTS_EDATA01(lvts_ctrl->base),
1009 LVTS_EDATA02(lvts_ctrl->base),
1010 LVTS_EDATA03(lvts_ctrl->base)
1011 };
1012
1013 /*
1014 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
1015 *
1016 * Bits:
1017 *
1018 * 20-0 : Efuse value for normalization data
1019 */
1020 for (i = 0; i < LVTS_SENSOR_MAX; i++)
1021 writel(lvts_ctrl->calibration[i], lvts_edata[i]);
1022
1023 return 0;
1024 }
1025
lvts_ctrl_configure(struct device * dev,struct lvts_ctrl * lvts_ctrl)1026 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1027 {
1028 u32 value;
1029
1030 /*
1031 * LVTS_TSSEL : Sensing point index numbering
1032 *
1033 * Bits:
1034 *
1035 * 31-24: ADC Sense 3
1036 * 23-16: ADC Sense 2
1037 * 15-8 : ADC Sense 1
1038 * 7-0 : ADC Sense 0
1039 */
1040 value = LVTS_TSSEL_CONF;
1041 writel(value, LVTS_TSSEL(lvts_ctrl->base));
1042
1043 /*
1044 * LVTS_CALSCALE : ADC voltage round
1045 */
1046 value = 0x300;
1047 value = LVTS_CALSCALE_CONF;
1048
1049 /*
1050 * LVTS_MSRCTL0 : Sensor filtering strategy
1051 *
1052 * Filters:
1053 *
1054 * 000 : One sample
1055 * 001 : Avg 2 samples
1056 * 010 : 4 samples, drop min and max, avg 2 samples
1057 * 011 : 6 samples, drop min and max, avg 4 samples
1058 * 100 : 10 samples, drop min and max, avg 8 samples
1059 * 101 : 18 samples, drop min and max, avg 16 samples
1060 *
1061 * Bits:
1062 *
1063 * 0-2 : Sensor0 filter
1064 * 3-5 : Sensor1 filter
1065 * 6-8 : Sensor2 filter
1066 * 9-11 : Sensor3 filter
1067 */
1068 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 |
1069 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
1070 writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
1071
1072 /*
1073 * LVTS_MONCTL1 : Period unit and group interval configuration
1074 *
1075 * The clock source of LVTS thermal controller is 26MHz.
1076 *
1077 * The period unit is a time base for all the interval delays
1078 * specified in the registers. By default we use 12. The time
1079 * conversion is done by multiplying by 256 and 1/26.10^6
1080 *
1081 * An interval delay multiplied by the period unit gives the
1082 * duration in seconds.
1083 *
1084 * - Filter interval delay is a delay between two samples of
1085 * the same sensor.
1086 *
1087 * - Sensor interval delay is a delay between two samples of
1088 * different sensors.
1089 *
1090 * - Group interval delay is a delay between different rounds.
1091 *
1092 * For example:
1093 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
1094 * and two sensors, TS1 and TS2, are in a LVTS thermal controller
1095 * and then
1096 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
1097 * Filter interval delay = 1 * Period unit = 118.149us
1098 * Sensor interval delay = 2 * Period unit = 236.298us
1099 * Group interval delay = 1 * Period unit = 118.149us
1100 *
1101 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1...
1102 * <--> Filter interval delay
1103 * <--> Sensor interval delay
1104 * <--> Group interval delay
1105 * Bits:
1106 * 29 - 20 : Group interval
1107 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1)
1108 * or an interrupt everytime the hot threshold is crossed (0)
1109 * 9 - 0 : Period unit
1110 *
1111 */
1112 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
1113 writel(value, LVTS_MONCTL1(lvts_ctrl->base));
1114
1115 /*
1116 * LVTS_MONCTL2 : Filtering and sensor interval
1117 *
1118 * Bits:
1119 *
1120 * 25-16 : Interval unit in PERIOD_UNIT between sample on
1121 * the same sensor, filter interval
1122 * 9-0 : Interval unit in PERIOD_UNIT between each sensor
1123 *
1124 */
1125 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
1126 writel(value, LVTS_MONCTL2(lvts_ctrl->base));
1127
1128 return lvts_irq_init(lvts_ctrl);
1129 }
1130
lvts_ctrl_start(struct device * dev,struct lvts_ctrl * lvts_ctrl)1131 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1132 {
1133 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
1134 struct thermal_zone_device *tz;
1135 u32 sensor_map = 0;
1136 int i;
1137 /*
1138 * Bitmaps to enable each sensor on immediate and filtered modes, as
1139 * described in MSRCTL1 and MONCTL0 registers below, respectively.
1140 */
1141 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
1142 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
1143
1144 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
1145 sensor_imm_bitmap : sensor_filt_bitmap;
1146
1147 lvts_for_each_valid_sensor(i, lvts_ctrl) {
1148
1149 int dt_id = lvts_sensors[i].dt_id;
1150
1151 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
1152 &lvts_ops);
1153 if (IS_ERR(tz)) {
1154 /*
1155 * This thermal zone is not described in the
1156 * device tree. It is not an error from the
1157 * thermal OF code POV, we just continue.
1158 */
1159 if (PTR_ERR(tz) == -ENODEV)
1160 continue;
1161
1162 return PTR_ERR(tz);
1163 }
1164
1165 devm_thermal_add_hwmon_sysfs(dev, tz);
1166
1167 /*
1168 * The thermal zone pointer will be needed in the
1169 * interrupt handler, we store it in the sensor
1170 * structure. The thermal domain structure will be
1171 * passed to the interrupt handler private data as the
1172 * interrupt is shared for all the controller
1173 * belonging to the thermal domain.
1174 */
1175 lvts_sensors[i].tz = tz;
1176
1177 /*
1178 * This sensor was correctly associated with a thermal
1179 * zone, let's set the corresponding bit in the sensor
1180 * map, so we can enable the temperature monitoring in
1181 * the hardware thermal controller.
1182 */
1183 sensor_map |= sensor_bitmap[i];
1184 }
1185
1186 /*
1187 * The initialization of the thermal zones give us
1188 * which sensor point to enable. If any thermal zone
1189 * was not described in the device tree, it won't be
1190 * enabled here in the sensor map.
1191 */
1192 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
1193 /*
1194 * LVTS_MSRCTL1 : Measurement control
1195 *
1196 * Bits:
1197 *
1198 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
1199 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
1200 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
1201 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
1202 *
1203 * That configuration will ignore the filtering and the delays
1204 * introduced in MONCTL1 and MONCTL2
1205 */
1206 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
1207 } else {
1208 /*
1209 * Bits:
1210 * 9: Single point access flow
1211 * 0-3: Enable sensing point 0-3
1212 */
1213 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
1214 }
1215
1216 return 0;
1217 }
1218
lvts_domain_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)1219 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
1220 const struct lvts_data *lvts_data)
1221 {
1222 struct lvts_ctrl *lvts_ctrl;
1223 int i, ret;
1224
1225 ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
1226 if (ret)
1227 return ret;
1228
1229 ret = lvts_domain_reset(dev, lvts_td->reset);
1230 if (ret) {
1231 dev_dbg(dev, "Failed to reset domain");
1232 return ret;
1233 }
1234
1235 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1236
1237 lvts_ctrl = &lvts_td->lvts_ctrl[i];
1238
1239 /*
1240 * Initialization steps:
1241 *
1242 * - Enable the clock
1243 * - Connect to the LVTS
1244 * - Initialize the LVTS
1245 * - Prepare the calibration data
1246 * - Select monitored sensors
1247 * [ Configure sampling ]
1248 * [ Configure the interrupt ]
1249 * - Start measurement
1250 */
1251 ret = lvts_ctrl_set_enable(lvts_ctrl, true);
1252 if (ret) {
1253 dev_dbg(dev, "Failed to enable LVTS clock");
1254 return ret;
1255 }
1256
1257 ret = lvts_ctrl_connect(dev, lvts_ctrl);
1258 if (ret) {
1259 dev_dbg(dev, "Failed to connect to LVTS controller");
1260 return ret;
1261 }
1262
1263 ret = lvts_ctrl_initialize(dev, lvts_ctrl);
1264 if (ret) {
1265 dev_dbg(dev, "Failed to initialize controller");
1266 return ret;
1267 }
1268
1269 ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
1270 if (ret) {
1271 dev_dbg(dev, "Failed to calibrate controller");
1272 return ret;
1273 }
1274
1275 ret = lvts_ctrl_configure(dev, lvts_ctrl);
1276 if (ret) {
1277 dev_dbg(dev, "Failed to configure controller");
1278 return ret;
1279 }
1280
1281 ret = lvts_ctrl_start(dev, lvts_ctrl);
1282 if (ret) {
1283 dev_dbg(dev, "Failed to start controller");
1284 return ret;
1285 }
1286 }
1287
1288 return lvts_debugfs_init(dev, lvts_td);
1289 }
1290
lvts_probe(struct platform_device * pdev)1291 static int lvts_probe(struct platform_device *pdev)
1292 {
1293 const struct lvts_data *lvts_data;
1294 struct lvts_domain *lvts_td;
1295 struct device *dev = &pdev->dev;
1296 struct resource *res;
1297 int irq, ret;
1298
1299 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
1300 if (!lvts_td)
1301 return -ENOMEM;
1302
1303 lvts_data = of_device_get_match_data(dev);
1304 if (!lvts_data)
1305 return -ENODEV;
1306
1307 lvts_td->clk = devm_clk_get_enabled(dev, NULL);
1308 if (IS_ERR(lvts_td->clk))
1309 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
1310
1311 res = platform_get_mem_or_io(pdev, 0);
1312 if (!res)
1313 return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
1314
1315 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1316 if (IS_ERR(lvts_td->base))
1317 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
1318
1319 lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
1320 if (IS_ERR(lvts_td->reset))
1321 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
1322
1323 irq = platform_get_irq(pdev, 0);
1324 if (irq < 0)
1325 return irq;
1326
1327 golden_temp_offset = lvts_data->temp_offset;
1328
1329 ret = lvts_domain_init(dev, lvts_td, lvts_data);
1330 if (ret)
1331 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
1332
1333 /*
1334 * At this point the LVTS is initialized and enabled. We can
1335 * safely enable the interrupt.
1336 */
1337 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
1338 IRQF_ONESHOT, dev_name(dev), lvts_td);
1339 if (ret)
1340 return dev_err_probe(dev, ret, "Failed to request interrupt\n");
1341
1342 platform_set_drvdata(pdev, lvts_td);
1343
1344 return 0;
1345 }
1346
lvts_remove(struct platform_device * pdev)1347 static void lvts_remove(struct platform_device *pdev)
1348 {
1349 struct lvts_domain *lvts_td;
1350 int i;
1351
1352 lvts_td = platform_get_drvdata(pdev);
1353
1354 for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1355 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1356
1357 lvts_debugfs_exit(lvts_td);
1358 }
1359
1360 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
1361 {
1362 .lvts_sensor = {
1363 { .dt_id = MT7988_CPU_0,
1364 .cal_offsets = { 0x00, 0x01, 0x02 } },
1365 { .dt_id = MT7988_CPU_1,
1366 .cal_offsets = { 0x04, 0x05, 0x06 } },
1367 { .dt_id = MT7988_ETH2P5G_0,
1368 .cal_offsets = { 0x08, 0x09, 0x0a } },
1369 { .dt_id = MT7988_ETH2P5G_1,
1370 .cal_offsets = { 0x0c, 0x0d, 0x0e } }
1371 },
1372 VALID_SENSOR_MAP(1, 1, 1, 1),
1373 .offset = 0x0,
1374 },
1375 {
1376 .lvts_sensor = {
1377 { .dt_id = MT7988_TOPS_0,
1378 .cal_offsets = { 0x14, 0x15, 0x16 } },
1379 { .dt_id = MT7988_TOPS_1,
1380 .cal_offsets = { 0x18, 0x19, 0x1a } },
1381 { .dt_id = MT7988_ETHWARP_0,
1382 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1383 { .dt_id = MT7988_ETHWARP_1,
1384 .cal_offsets = { 0x20, 0x21, 0x22 } }
1385 },
1386 VALID_SENSOR_MAP(1, 1, 1, 1),
1387 .offset = 0x100,
1388 }
1389 };
1390
lvts_suspend(struct device * dev)1391 static int lvts_suspend(struct device *dev)
1392 {
1393 struct lvts_domain *lvts_td;
1394 int i;
1395
1396 lvts_td = dev_get_drvdata(dev);
1397
1398 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1399 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], false);
1400 usleep_range(100, 200);
1401 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1402 }
1403
1404 clk_disable_unprepare(lvts_td->clk);
1405
1406 return 0;
1407 }
1408
lvts_resume(struct device * dev)1409 static int lvts_resume(struct device *dev)
1410 {
1411 struct lvts_domain *lvts_td;
1412 int i, ret;
1413
1414 lvts_td = dev_get_drvdata(dev);
1415
1416 ret = clk_prepare_enable(lvts_td->clk);
1417 if (ret)
1418 return ret;
1419
1420 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1421 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
1422 usleep_range(100, 200);
1423 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], true);
1424 }
1425
1426 return 0;
1427 }
1428
1429 /*
1430 * The MT8186 calibration data is stored as packed 3-byte little-endian
1431 * values using a weird layout that makes sense only when viewed as a 32-bit
1432 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and
1433 * y = byte number where the LSB is y=0. We then have:
1434 *
1435 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0]
1436 *
1437 * However, when considering a byte stream, those appear as follows:
1438 *
1439 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0]
1440 *
1441 * Hence the rather confusing offsets provided below.
1442 */
1443 static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = {
1444 {
1445 .lvts_sensor = {
1446 { .dt_id = MT8186_LITTLE_CPU0,
1447 .cal_offsets = { 5, 6, 7 } },
1448 { .dt_id = MT8186_LITTLE_CPU1,
1449 .cal_offsets = { 10, 11, 4 } },
1450 { .dt_id = MT8186_LITTLE_CPU2,
1451 .cal_offsets = { 15, 8, 9 } },
1452 { .dt_id = MT8186_CAM,
1453 .cal_offsets = { 12, 13, 14 } }
1454 },
1455 VALID_SENSOR_MAP(1, 1, 1, 1),
1456 .offset = 0x0,
1457 },
1458 {
1459 .lvts_sensor = {
1460 { .dt_id = MT8186_BIG_CPU0,
1461 .cal_offsets = { 22, 23, 16 } },
1462 { .dt_id = MT8186_BIG_CPU1,
1463 .cal_offsets = { 27, 20, 21 } }
1464 },
1465 VALID_SENSOR_MAP(1, 1, 0, 0),
1466 .offset = 0x100,
1467 },
1468 {
1469 .lvts_sensor = {
1470 { .dt_id = MT8186_NNA,
1471 .cal_offsets = { 29, 30, 31 } },
1472 { .dt_id = MT8186_ADSP,
1473 .cal_offsets = { 34, 35, 28 } },
1474 { .dt_id = MT8186_GPU,
1475 .cal_offsets = { 39, 32, 33 } }
1476 },
1477 VALID_SENSOR_MAP(1, 1, 1, 0),
1478 .offset = 0x200,
1479 }
1480 };
1481
1482 static const struct lvts_ctrl_data mt8188_lvts_mcu_data_ctrl[] = {
1483 {
1484 .lvts_sensor = {
1485 { .dt_id = MT8188_MCU_LITTLE_CPU0,
1486 .cal_offsets = { 22, 23, 24 } },
1487 { .dt_id = MT8188_MCU_LITTLE_CPU1,
1488 .cal_offsets = { 25, 26, 27 } },
1489 { .dt_id = MT8188_MCU_LITTLE_CPU2,
1490 .cal_offsets = { 28, 29, 30 } },
1491 { .dt_id = MT8188_MCU_LITTLE_CPU3,
1492 .cal_offsets = { 31, 32, 33 } },
1493 },
1494 VALID_SENSOR_MAP(1, 1, 1, 1),
1495 .offset = 0x0,
1496 },
1497 {
1498 .lvts_sensor = {
1499 { .dt_id = MT8188_MCU_BIG_CPU0,
1500 .cal_offsets = { 34, 35, 36 } },
1501 { .dt_id = MT8188_MCU_BIG_CPU1,
1502 .cal_offsets = { 37, 38, 39 } },
1503 },
1504 VALID_SENSOR_MAP(1, 1, 0, 0),
1505 .offset = 0x100,
1506 }
1507 };
1508
1509 static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = {
1510 {
1511 .lvts_sensor = {
1512
1513 { /* unused */ },
1514 { .dt_id = MT8188_AP_APU,
1515 .cal_offsets = { 40, 41, 42 } },
1516 },
1517 VALID_SENSOR_MAP(0, 1, 0, 0),
1518 .offset = 0x0,
1519 },
1520 {
1521 .lvts_sensor = {
1522 { .dt_id = MT8188_AP_GPU0,
1523 .cal_offsets = { 43, 44, 45 } },
1524 { .dt_id = MT8188_AP_GPU1,
1525 .cal_offsets = { 46, 47, 48 } },
1526 { .dt_id = MT8188_AP_ADSP,
1527 .cal_offsets = { 49, 50, 51 } },
1528 },
1529 VALID_SENSOR_MAP(1, 1, 1, 0),
1530 .offset = 0x100,
1531 },
1532 {
1533 .lvts_sensor = {
1534 { .dt_id = MT8188_AP_VDO,
1535 .cal_offsets = { 52, 53, 54 } },
1536 { .dt_id = MT8188_AP_INFRA,
1537 .cal_offsets = { 55, 56, 57 } },
1538 },
1539 VALID_SENSOR_MAP(1, 1, 0, 0),
1540 .offset = 0x200,
1541 },
1542 {
1543 .lvts_sensor = {
1544 { .dt_id = MT8188_AP_CAM1,
1545 .cal_offsets = { 58, 59, 60 } },
1546 { .dt_id = MT8188_AP_CAM2,
1547 .cal_offsets = { 61, 62, 63 } },
1548 },
1549 VALID_SENSOR_MAP(1, 1, 0, 0),
1550 .offset = 0x300,
1551 }
1552 };
1553
1554 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
1555 {
1556 .lvts_sensor = {
1557 { .dt_id = MT8192_MCU_BIG_CPU0,
1558 .cal_offsets = { 0x04, 0x05, 0x06 } },
1559 { .dt_id = MT8192_MCU_BIG_CPU1,
1560 .cal_offsets = { 0x08, 0x09, 0x0a } }
1561 },
1562 VALID_SENSOR_MAP(1, 1, 0, 0),
1563 .offset = 0x0,
1564 .mode = LVTS_MSR_FILTERED_MODE,
1565 },
1566 {
1567 .lvts_sensor = {
1568 { .dt_id = MT8192_MCU_BIG_CPU2,
1569 .cal_offsets = { 0x0c, 0x0d, 0x0e } },
1570 { .dt_id = MT8192_MCU_BIG_CPU3,
1571 .cal_offsets = { 0x10, 0x11, 0x12 } }
1572 },
1573 VALID_SENSOR_MAP(1, 1, 0, 0),
1574 .offset = 0x100,
1575 .mode = LVTS_MSR_FILTERED_MODE,
1576 },
1577 {
1578 .lvts_sensor = {
1579 { .dt_id = MT8192_MCU_LITTLE_CPU0,
1580 .cal_offsets = { 0x14, 0x15, 0x16 } },
1581 { .dt_id = MT8192_MCU_LITTLE_CPU1,
1582 .cal_offsets = { 0x18, 0x19, 0x1a } },
1583 { .dt_id = MT8192_MCU_LITTLE_CPU2,
1584 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1585 { .dt_id = MT8192_MCU_LITTLE_CPU3,
1586 .cal_offsets = { 0x20, 0x21, 0x22 } }
1587 },
1588 VALID_SENSOR_MAP(1, 1, 1, 1),
1589 .offset = 0x200,
1590 .mode = LVTS_MSR_FILTERED_MODE,
1591 }
1592 };
1593
1594 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
1595 {
1596 .lvts_sensor = {
1597 { .dt_id = MT8192_AP_VPU0,
1598 .cal_offsets = { 0x24, 0x25, 0x26 } },
1599 { .dt_id = MT8192_AP_VPU1,
1600 .cal_offsets = { 0x28, 0x29, 0x2a } }
1601 },
1602 VALID_SENSOR_MAP(1, 1, 0, 0),
1603 .offset = 0x0,
1604 },
1605 {
1606 .lvts_sensor = {
1607 { .dt_id = MT8192_AP_GPU0,
1608 .cal_offsets = { 0x2c, 0x2d, 0x2e } },
1609 { .dt_id = MT8192_AP_GPU1,
1610 .cal_offsets = { 0x30, 0x31, 0x32 } }
1611 },
1612 VALID_SENSOR_MAP(1, 1, 0, 0),
1613 .offset = 0x100,
1614 },
1615 {
1616 .lvts_sensor = {
1617 { .dt_id = MT8192_AP_INFRA,
1618 .cal_offsets = { 0x34, 0x35, 0x36 } },
1619 { .dt_id = MT8192_AP_CAM,
1620 .cal_offsets = { 0x38, 0x39, 0x3a } },
1621 },
1622 VALID_SENSOR_MAP(1, 1, 0, 0),
1623 .offset = 0x200,
1624 },
1625 {
1626 .lvts_sensor = {
1627 { .dt_id = MT8192_AP_MD0,
1628 .cal_offsets = { 0x3c, 0x3d, 0x3e } },
1629 { .dt_id = MT8192_AP_MD1,
1630 .cal_offsets = { 0x40, 0x41, 0x42 } },
1631 { .dt_id = MT8192_AP_MD2,
1632 .cal_offsets = { 0x44, 0x45, 0x46 } }
1633 },
1634 VALID_SENSOR_MAP(1, 1, 1, 0),
1635 .offset = 0x300,
1636 }
1637 };
1638
1639 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
1640 {
1641 .lvts_sensor = {
1642 { .dt_id = MT8195_MCU_BIG_CPU0,
1643 .cal_offsets = { 0x04, 0x05, 0x06 } },
1644 { .dt_id = MT8195_MCU_BIG_CPU1,
1645 .cal_offsets = { 0x07, 0x08, 0x09 } }
1646 },
1647 VALID_SENSOR_MAP(1, 1, 0, 0),
1648 .offset = 0x0,
1649 },
1650 {
1651 .lvts_sensor = {
1652 { .dt_id = MT8195_MCU_BIG_CPU2,
1653 .cal_offsets = { 0x0d, 0x0e, 0x0f } },
1654 { .dt_id = MT8195_MCU_BIG_CPU3,
1655 .cal_offsets = { 0x10, 0x11, 0x12 } }
1656 },
1657 VALID_SENSOR_MAP(1, 1, 0, 0),
1658 .offset = 0x100,
1659 },
1660 {
1661 .lvts_sensor = {
1662 { .dt_id = MT8195_MCU_LITTLE_CPU0,
1663 .cal_offsets = { 0x16, 0x17, 0x18 } },
1664 { .dt_id = MT8195_MCU_LITTLE_CPU1,
1665 .cal_offsets = { 0x19, 0x1a, 0x1b } },
1666 { .dt_id = MT8195_MCU_LITTLE_CPU2,
1667 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1668 { .dt_id = MT8195_MCU_LITTLE_CPU3,
1669 .cal_offsets = { 0x1f, 0x20, 0x21 } }
1670 },
1671 VALID_SENSOR_MAP(1, 1, 1, 1),
1672 .offset = 0x200,
1673 }
1674 };
1675
1676 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
1677 {
1678 .lvts_sensor = {
1679 { .dt_id = MT8195_AP_VPU0,
1680 .cal_offsets = { 0x25, 0x26, 0x27 } },
1681 { .dt_id = MT8195_AP_VPU1,
1682 .cal_offsets = { 0x28, 0x29, 0x2a } }
1683 },
1684 VALID_SENSOR_MAP(1, 1, 0, 0),
1685 .offset = 0x0,
1686 },
1687 {
1688 .lvts_sensor = {
1689 { .dt_id = MT8195_AP_GPU0,
1690 .cal_offsets = { 0x2e, 0x2f, 0x30 } },
1691 { .dt_id = MT8195_AP_GPU1,
1692 .cal_offsets = { 0x31, 0x32, 0x33 } }
1693 },
1694 VALID_SENSOR_MAP(1, 1, 0, 0),
1695 .offset = 0x100,
1696 },
1697 {
1698 .lvts_sensor = {
1699 { .dt_id = MT8195_AP_VDEC,
1700 .cal_offsets = { 0x37, 0x38, 0x39 } },
1701 { .dt_id = MT8195_AP_IMG,
1702 .cal_offsets = { 0x3a, 0x3b, 0x3c } },
1703 { .dt_id = MT8195_AP_INFRA,
1704 .cal_offsets = { 0x3d, 0x3e, 0x3f } }
1705 },
1706 VALID_SENSOR_MAP(1, 1, 1, 0),
1707 .offset = 0x200,
1708 },
1709 {
1710 .lvts_sensor = {
1711 { .dt_id = MT8195_AP_CAM0,
1712 .cal_offsets = { 0x43, 0x44, 0x45 } },
1713 { .dt_id = MT8195_AP_CAM1,
1714 .cal_offsets = { 0x46, 0x47, 0x48 } }
1715 },
1716 VALID_SENSOR_MAP(1, 1, 0, 0),
1717 .offset = 0x300,
1718 }
1719 };
1720
1721 static const struct lvts_data mt7988_lvts_ap_data = {
1722 .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
1723 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
1724 .temp_factor = LVTS_COEFF_A_MT7988,
1725 .temp_offset = LVTS_COEFF_B_MT7988,
1726 .gt_calib_bit_offset = 24,
1727 };
1728
1729 static const struct lvts_data mt8186_lvts_data = {
1730 .lvts_ctrl = mt8186_lvts_data_ctrl,
1731 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl),
1732 .temp_factor = LVTS_COEFF_A_MT7988,
1733 .temp_offset = LVTS_COEFF_B_MT7988,
1734 .gt_calib_bit_offset = 24,
1735 .def_calibration = 19000,
1736 };
1737
1738 static const struct lvts_data mt8188_lvts_mcu_data = {
1739 .lvts_ctrl = mt8188_lvts_mcu_data_ctrl,
1740 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl),
1741 .temp_factor = LVTS_COEFF_A_MT8195,
1742 .temp_offset = LVTS_COEFF_B_MT8195,
1743 .gt_calib_bit_offset = 20,
1744 .def_calibration = 35000,
1745 };
1746
1747 static const struct lvts_data mt8188_lvts_ap_data = {
1748 .lvts_ctrl = mt8188_lvts_ap_data_ctrl,
1749 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl),
1750 .temp_factor = LVTS_COEFF_A_MT8195,
1751 .temp_offset = LVTS_COEFF_B_MT8195,
1752 .gt_calib_bit_offset = 20,
1753 .def_calibration = 35000,
1754 };
1755
1756 static const struct lvts_data mt8192_lvts_mcu_data = {
1757 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
1758 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
1759 .temp_factor = LVTS_COEFF_A_MT8195,
1760 .temp_offset = LVTS_COEFF_B_MT8195,
1761 .gt_calib_bit_offset = 24,
1762 .def_calibration = 35000,
1763 };
1764
1765 static const struct lvts_data mt8192_lvts_ap_data = {
1766 .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
1767 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
1768 .temp_factor = LVTS_COEFF_A_MT8195,
1769 .temp_offset = LVTS_COEFF_B_MT8195,
1770 .gt_calib_bit_offset = 24,
1771 .def_calibration = 35000,
1772 };
1773
1774 static const struct lvts_data mt8195_lvts_mcu_data = {
1775 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
1776 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
1777 .temp_factor = LVTS_COEFF_A_MT8195,
1778 .temp_offset = LVTS_COEFF_B_MT8195,
1779 .gt_calib_bit_offset = 24,
1780 .def_calibration = 35000,
1781 };
1782
1783 static const struct lvts_data mt8195_lvts_ap_data = {
1784 .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
1785 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
1786 .temp_factor = LVTS_COEFF_A_MT8195,
1787 .temp_offset = LVTS_COEFF_B_MT8195,
1788 .gt_calib_bit_offset = 24,
1789 .def_calibration = 35000,
1790 };
1791
1792 static const struct of_device_id lvts_of_match[] = {
1793 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
1794 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data },
1795 { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data },
1796 { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data },
1797 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
1798 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
1799 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
1800 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
1801 {},
1802 };
1803 MODULE_DEVICE_TABLE(of, lvts_of_match);
1804
1805 static const struct dev_pm_ops lvts_pm_ops = {
1806 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
1807 };
1808
1809 static struct platform_driver lvts_driver = {
1810 .probe = lvts_probe,
1811 .remove = lvts_remove,
1812 .driver = {
1813 .name = "mtk-lvts-thermal",
1814 .of_match_table = lvts_of_match,
1815 .pm = &lvts_pm_ops,
1816 },
1817 };
1818 module_platform_driver(lvts_driver);
1819
1820 MODULE_AUTHOR("Balsam CHIHI <[email protected]>");
1821 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
1822 MODULE_LICENSE("GPL");
1823