1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: [email protected])
7 *
8 */
9
10 #include "mpi3mr.h"
11 #include <linux/io-64-nonatomic-lo-hi.h>
12
13 static int
14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason);
15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
17 struct mpi3_ioc_facts_data *facts_data);
18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
19 struct mpi3mr_drv_cmd *drv_cmd);
20 static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc);
21 static int poll_queues;
22 module_param(poll_queues, int, 0444);
23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
24
25 #if defined(writeq) && defined(CONFIG_64BIT)
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
27 {
28 writeq(b, addr);
29 }
30 #else
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
32 {
33 __u64 data_out = b;
34
35 writel((u32)(data_out), addr);
36 writel((u32)(data_out >> 32), (addr + 4));
37 }
38 #endif
39
40 static inline bool
mpi3mr_check_req_qfull(struct op_req_qinfo * op_req_q)41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
42 {
43 u16 pi, ci, max_entries;
44 bool is_qfull = false;
45
46 pi = op_req_q->pi;
47 ci = READ_ONCE(op_req_q->ci);
48 max_entries = op_req_q->num_requests;
49
50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
51 is_qfull = true;
52
53 return is_qfull;
54 }
55
mpi3mr_sync_irqs(struct mpi3mr_ioc * mrioc)56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
57 {
58 u16 i, max_vectors;
59
60 max_vectors = mrioc->intr_info_count;
61
62 for (i = 0; i < max_vectors; i++)
63 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
64 }
65
mpi3mr_ioc_disable_intr(struct mpi3mr_ioc * mrioc)66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
67 {
68 mrioc->intr_enabled = 0;
69 mpi3mr_sync_irqs(mrioc);
70 }
71
mpi3mr_ioc_enable_intr(struct mpi3mr_ioc * mrioc)72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
73 {
74 mrioc->intr_enabled = 1;
75 }
76
mpi3mr_cleanup_isr(struct mpi3mr_ioc * mrioc)77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
78 {
79 u16 i;
80
81 mpi3mr_ioc_disable_intr(mrioc);
82
83 if (!mrioc->intr_info)
84 return;
85
86 for (i = 0; i < mrioc->intr_info_count; i++)
87 free_irq(pci_irq_vector(mrioc->pdev, i),
88 (mrioc->intr_info + i));
89
90 kfree(mrioc->intr_info);
91 mrioc->intr_info = NULL;
92 mrioc->intr_info_count = 0;
93 mrioc->is_intr_info_set = false;
94 pci_free_irq_vectors(mrioc->pdev);
95 }
96
mpi3mr_add_sg_single(void * paddr,u8 flags,u32 length,dma_addr_t dma_addr)97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
98 dma_addr_t dma_addr)
99 {
100 struct mpi3_sge_common *sgel = paddr;
101
102 sgel->flags = flags;
103 sgel->length = cpu_to_le32(length);
104 sgel->address = cpu_to_le64(dma_addr);
105 }
106
mpi3mr_build_zero_len_sge(void * paddr)107 void mpi3mr_build_zero_len_sge(void *paddr)
108 {
109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
110
111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
112 }
113
mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
116 {
117 if (!phys_addr)
118 return NULL;
119
120 if ((phys_addr < mrioc->reply_buf_dma) ||
121 (phys_addr > mrioc->reply_buf_dma_max_address))
122 return NULL;
123
124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
125 }
126
mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
128 dma_addr_t phys_addr)
129 {
130 if (!phys_addr)
131 return NULL;
132
133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
134 }
135
mpi3mr_repost_reply_buf(struct mpi3mr_ioc * mrioc,u64 reply_dma)136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
137 u64 reply_dma)
138 {
139 u32 old_idx = 0;
140 unsigned long flags;
141
142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
143 old_idx = mrioc->reply_free_queue_host_index;
144 mrioc->reply_free_queue_host_index = (
145 (mrioc->reply_free_queue_host_index ==
146 (mrioc->reply_free_qsz - 1)) ? 0 :
147 (mrioc->reply_free_queue_host_index + 1));
148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
149 writel(mrioc->reply_free_queue_host_index,
150 &mrioc->sysif_regs->reply_free_host_index);
151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
152 }
153
mpi3mr_repost_sense_buf(struct mpi3mr_ioc * mrioc,u64 sense_buf_dma)154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
155 u64 sense_buf_dma)
156 {
157 u32 old_idx = 0;
158 unsigned long flags;
159
160 spin_lock_irqsave(&mrioc->sbq_lock, flags);
161 old_idx = mrioc->sbq_host_index;
162 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
163 (mrioc->sense_buf_q_sz - 1)) ? 0 :
164 (mrioc->sbq_host_index + 1));
165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
166 writel(mrioc->sbq_host_index,
167 &mrioc->sysif_regs->sense_buffer_free_host_index);
168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
169 }
170
mpi3mr_print_event_data(struct mpi3mr_ioc * mrioc,struct mpi3_event_notification_reply * event_reply)171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
172 struct mpi3_event_notification_reply *event_reply)
173 {
174 char *desc = NULL;
175 u16 event;
176
177 event = event_reply->event;
178
179 switch (event) {
180 case MPI3_EVENT_LOG_DATA:
181 desc = "Log Data";
182 break;
183 case MPI3_EVENT_CHANGE:
184 desc = "Event Change";
185 break;
186 case MPI3_EVENT_GPIO_INTERRUPT:
187 desc = "GPIO Interrupt";
188 break;
189 case MPI3_EVENT_CABLE_MGMT:
190 desc = "Cable Management";
191 break;
192 case MPI3_EVENT_ENERGY_PACK_CHANGE:
193 desc = "Energy Pack Change";
194 break;
195 case MPI3_EVENT_DEVICE_ADDED:
196 {
197 struct mpi3_device_page0 *event_data =
198 (struct mpi3_device_page0 *)event_reply->event_data;
199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
200 event_data->dev_handle, event_data->device_form);
201 return;
202 }
203 case MPI3_EVENT_DEVICE_INFO_CHANGED:
204 {
205 struct mpi3_device_page0 *event_data =
206 (struct mpi3_device_page0 *)event_reply->event_data;
207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
208 event_data->dev_handle, event_data->device_form);
209 return;
210 }
211 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
212 {
213 struct mpi3_event_data_device_status_change *event_data =
214 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
216 event_data->dev_handle, event_data->reason_code);
217 return;
218 }
219 case MPI3_EVENT_SAS_DISCOVERY:
220 {
221 struct mpi3_event_data_sas_discovery *event_data =
222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
225 "start" : "stop",
226 le32_to_cpu(event_data->discovery_status));
227 return;
228 }
229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
230 desc = "SAS Broadcast Primitive";
231 break;
232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
233 desc = "SAS Notify Primitive";
234 break;
235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
236 desc = "SAS Init Device Status Change";
237 break;
238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
239 desc = "SAS Init Table Overflow";
240 break;
241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
242 desc = "SAS Topology Change List";
243 break;
244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
245 desc = "Enclosure Device Status Change";
246 break;
247 case MPI3_EVENT_ENCL_DEVICE_ADDED:
248 desc = "Enclosure Added";
249 break;
250 case MPI3_EVENT_HARD_RESET_RECEIVED:
251 desc = "Hard Reset Received";
252 break;
253 case MPI3_EVENT_SAS_PHY_COUNTER:
254 desc = "SAS PHY Counter";
255 break;
256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
257 desc = "SAS Device Discovery Error";
258 break;
259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
260 desc = "PCIE Topology Change List";
261 break;
262 case MPI3_EVENT_PCIE_ENUMERATION:
263 {
264 struct mpi3_event_data_pcie_enumeration *event_data =
265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
266 ioc_info(mrioc, "PCIE Enumeration: (%s)",
267 (event_data->reason_code ==
268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
269 if (event_data->enumeration_status)
270 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
271 le32_to_cpu(event_data->enumeration_status));
272 return;
273 }
274 case MPI3_EVENT_PREPARE_FOR_RESET:
275 desc = "Prepare For Reset";
276 break;
277 case MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE:
278 desc = "Diagnostic Buffer Status Change";
279 break;
280 }
281
282 if (!desc)
283 return;
284
285 ioc_info(mrioc, "%s\n", desc);
286 }
287
mpi3mr_handle_events(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply * def_reply)288 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
289 struct mpi3_default_reply *def_reply)
290 {
291 struct mpi3_event_notification_reply *event_reply =
292 (struct mpi3_event_notification_reply *)def_reply;
293
294 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
295 mpi3mr_print_event_data(mrioc, event_reply);
296 mpi3mr_os_handle_events(mrioc, event_reply);
297 }
298
299 static struct mpi3mr_drv_cmd *
mpi3mr_get_drv_cmd(struct mpi3mr_ioc * mrioc,u16 host_tag,struct mpi3_default_reply * def_reply)300 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
301 struct mpi3_default_reply *def_reply)
302 {
303 u16 idx;
304
305 switch (host_tag) {
306 case MPI3MR_HOSTTAG_INITCMDS:
307 return &mrioc->init_cmds;
308 case MPI3MR_HOSTTAG_CFG_CMDS:
309 return &mrioc->cfg_cmds;
310 case MPI3MR_HOSTTAG_BSG_CMDS:
311 return &mrioc->bsg_cmds;
312 case MPI3MR_HOSTTAG_BLK_TMS:
313 return &mrioc->host_tm_cmds;
314 case MPI3MR_HOSTTAG_PEL_ABORT:
315 return &mrioc->pel_abort_cmd;
316 case MPI3MR_HOSTTAG_PEL_WAIT:
317 return &mrioc->pel_cmds;
318 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
319 return &mrioc->transport_cmds;
320 case MPI3MR_HOSTTAG_INVALID:
321 if (def_reply && def_reply->function ==
322 MPI3_FUNCTION_EVENT_NOTIFICATION)
323 mpi3mr_handle_events(mrioc, def_reply);
324 return NULL;
325 default:
326 break;
327 }
328 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
329 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
330 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
331 return &mrioc->dev_rmhs_cmds[idx];
332 }
333
334 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
335 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
336 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
337 return &mrioc->evtack_cmds[idx];
338 }
339
340 return NULL;
341 }
342
mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply_descriptor * reply_desc,u64 * reply_dma)343 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
344 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
345 {
346 u16 reply_desc_type, host_tag = 0;
347 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
348 u16 masked_ioc_status = MPI3_IOCSTATUS_SUCCESS;
349 u32 ioc_loginfo = 0, sense_count = 0;
350 struct mpi3_status_reply_descriptor *status_desc;
351 struct mpi3_address_reply_descriptor *addr_desc;
352 struct mpi3_success_reply_descriptor *success_desc;
353 struct mpi3_default_reply *def_reply = NULL;
354 struct mpi3mr_drv_cmd *cmdptr = NULL;
355 struct mpi3_scsi_io_reply *scsi_reply;
356 struct scsi_sense_hdr sshdr;
357 u8 *sense_buf = NULL;
358
359 *reply_dma = 0;
360 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
361 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
362 switch (reply_desc_type) {
363 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
364 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
365 host_tag = le16_to_cpu(status_desc->host_tag);
366 ioc_status = le16_to_cpu(status_desc->ioc_status);
367 if (ioc_status &
368 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
369 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
370 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
371 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
372 break;
373 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
374 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
375 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
376 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
377 if (!def_reply)
378 goto out;
379 host_tag = le16_to_cpu(def_reply->host_tag);
380 ioc_status = le16_to_cpu(def_reply->ioc_status);
381 if (ioc_status &
382 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
383 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
384 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
385 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
386 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
387 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
388 le64_to_cpu(scsi_reply->sense_data_buffer_address));
389 sense_count = le32_to_cpu(scsi_reply->sense_count);
390 if (sense_buf) {
391 scsi_normalize_sense(sense_buf, sense_count,
392 &sshdr);
393 mpi3mr_scsisense_trigger(mrioc, sshdr.sense_key,
394 sshdr.asc, sshdr.ascq);
395 }
396 }
397 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
398 break;
399 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
400 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
401 host_tag = le16_to_cpu(success_desc->host_tag);
402 break;
403 default:
404 break;
405 }
406
407 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
408 if (cmdptr) {
409 if (cmdptr->state & MPI3MR_CMD_PENDING) {
410 cmdptr->state |= MPI3MR_CMD_COMPLETE;
411 cmdptr->ioc_loginfo = ioc_loginfo;
412 if (host_tag == MPI3MR_HOSTTAG_BSG_CMDS)
413 cmdptr->ioc_status = ioc_status;
414 else
415 cmdptr->ioc_status = masked_ioc_status;
416 cmdptr->state &= ~MPI3MR_CMD_PENDING;
417 if (def_reply) {
418 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
419 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
420 mrioc->reply_sz);
421 }
422 if (sense_buf && cmdptr->sensebuf) {
423 cmdptr->is_sense = 1;
424 memcpy(cmdptr->sensebuf, sense_buf,
425 MPI3MR_SENSE_BUF_SZ);
426 }
427 if (cmdptr->is_waiting) {
428 complete(&cmdptr->done);
429 cmdptr->is_waiting = 0;
430 } else if (cmdptr->callback)
431 cmdptr->callback(mrioc, cmdptr);
432 }
433 }
434 out:
435 if (sense_buf)
436 mpi3mr_repost_sense_buf(mrioc,
437 le64_to_cpu(scsi_reply->sense_data_buffer_address));
438 }
439
mpi3mr_process_admin_reply_q(struct mpi3mr_ioc * mrioc)440 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
441 {
442 u32 exp_phase = mrioc->admin_reply_ephase;
443 u32 admin_reply_ci = mrioc->admin_reply_ci;
444 u32 num_admin_replies = 0;
445 u64 reply_dma = 0;
446 u16 threshold_comps = 0;
447 struct mpi3_default_reply_descriptor *reply_desc;
448
449 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
450 return 0;
451
452 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
453 admin_reply_ci;
454
455 if ((le16_to_cpu(reply_desc->reply_flags) &
456 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
457 atomic_dec(&mrioc->admin_reply_q_in_use);
458 return 0;
459 }
460
461 do {
462 if (mrioc->unrecoverable || mrioc->io_admin_reset_sync)
463 break;
464
465 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
466 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
467 if (reply_dma)
468 mpi3mr_repost_reply_buf(mrioc, reply_dma);
469 num_admin_replies++;
470 threshold_comps++;
471 if (++admin_reply_ci == mrioc->num_admin_replies) {
472 admin_reply_ci = 0;
473 exp_phase ^= 1;
474 }
475 reply_desc =
476 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
477 admin_reply_ci;
478 if ((le16_to_cpu(reply_desc->reply_flags) &
479 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
480 break;
481 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
482 writel(admin_reply_ci,
483 &mrioc->sysif_regs->admin_reply_queue_ci);
484 threshold_comps = 0;
485 }
486 } while (1);
487
488 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
489 mrioc->admin_reply_ci = admin_reply_ci;
490 mrioc->admin_reply_ephase = exp_phase;
491 atomic_dec(&mrioc->admin_reply_q_in_use);
492
493 return num_admin_replies;
494 }
495
496 /**
497 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
498 * queue's consumer index from operational reply descriptor queue.
499 * @op_reply_q: op_reply_qinfo object
500 * @reply_ci: operational reply descriptor's queue consumer index
501 *
502 * Returns: reply descriptor frame address
503 */
504 static inline struct mpi3_default_reply_descriptor *
mpi3mr_get_reply_desc(struct op_reply_qinfo * op_reply_q,u32 reply_ci)505 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
506 {
507 void *segment_base_addr;
508 struct segments *segments = op_reply_q->q_segments;
509 struct mpi3_default_reply_descriptor *reply_desc = NULL;
510
511 segment_base_addr =
512 segments[reply_ci / op_reply_q->segment_qd].segment;
513 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
514 (reply_ci % op_reply_q->segment_qd);
515 return reply_desc;
516 }
517
518 /**
519 * mpi3mr_process_op_reply_q - Operational reply queue handler
520 * @mrioc: Adapter instance reference
521 * @op_reply_q: Operational reply queue info
522 *
523 * Checks the specific operational reply queue and drains the
524 * reply queue entries until the queue is empty and process the
525 * individual reply descriptors.
526 *
527 * Return: 0 if queue is already processed,or number of reply
528 * descriptors processed.
529 */
mpi3mr_process_op_reply_q(struct mpi3mr_ioc * mrioc,struct op_reply_qinfo * op_reply_q)530 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
531 struct op_reply_qinfo *op_reply_q)
532 {
533 struct op_req_qinfo *op_req_q;
534 u32 exp_phase;
535 u32 reply_ci;
536 u32 num_op_reply = 0;
537 u64 reply_dma = 0;
538 struct mpi3_default_reply_descriptor *reply_desc;
539 u16 req_q_idx = 0, reply_qidx, threshold_comps = 0;
540
541 reply_qidx = op_reply_q->qid - 1;
542
543 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
544 return 0;
545
546 exp_phase = op_reply_q->ephase;
547 reply_ci = op_reply_q->ci;
548
549 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
550 if ((le16_to_cpu(reply_desc->reply_flags) &
551 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
552 atomic_dec(&op_reply_q->in_use);
553 return 0;
554 }
555
556 do {
557 if (mrioc->unrecoverable || mrioc->io_admin_reset_sync)
558 break;
559
560 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
561 op_req_q = &mrioc->req_qinfo[req_q_idx];
562
563 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
564 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
565 reply_qidx);
566 atomic_dec(&op_reply_q->pend_ios);
567 if (reply_dma)
568 mpi3mr_repost_reply_buf(mrioc, reply_dma);
569 num_op_reply++;
570 threshold_comps++;
571
572 if (++reply_ci == op_reply_q->num_replies) {
573 reply_ci = 0;
574 exp_phase ^= 1;
575 }
576
577 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
578
579 if ((le16_to_cpu(reply_desc->reply_flags) &
580 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
581 break;
582 #ifndef CONFIG_PREEMPT_RT
583 /*
584 * Exit completion loop to avoid CPU lockup
585 * Ensure remaining completion happens from threaded ISR.
586 */
587 if (num_op_reply > mrioc->max_host_ios) {
588 op_reply_q->enable_irq_poll = true;
589 break;
590 }
591 #endif
592 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
593 writel(reply_ci,
594 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
595 atomic_sub(threshold_comps, &op_reply_q->pend_ios);
596 threshold_comps = 0;
597 }
598 } while (1);
599
600 writel(reply_ci,
601 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
602 op_reply_q->ci = reply_ci;
603 op_reply_q->ephase = exp_phase;
604 atomic_sub(threshold_comps, &op_reply_q->pend_ios);
605 atomic_dec(&op_reply_q->in_use);
606 return num_op_reply;
607 }
608
609 /**
610 * mpi3mr_blk_mq_poll - Operational reply queue handler
611 * @shost: SCSI Host reference
612 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
613 *
614 * Checks the specific operational reply queue and drains the
615 * reply queue entries until the queue is empty and process the
616 * individual reply descriptors.
617 *
618 * Return: 0 if queue is already processed,or number of reply
619 * descriptors processed.
620 */
mpi3mr_blk_mq_poll(struct Scsi_Host * shost,unsigned int queue_num)621 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
622 {
623 int num_entries = 0;
624 struct mpi3mr_ioc *mrioc;
625
626 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
627
628 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
629 mrioc->unrecoverable || mrioc->pci_err_recovery))
630 return 0;
631
632 num_entries = mpi3mr_process_op_reply_q(mrioc,
633 &mrioc->op_reply_qinfo[queue_num]);
634
635 return num_entries;
636 }
637
mpi3mr_isr_primary(int irq,void * privdata)638 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
639 {
640 struct mpi3mr_intr_info *intr_info = privdata;
641 struct mpi3mr_ioc *mrioc;
642 u16 midx;
643 u32 num_admin_replies = 0, num_op_reply = 0;
644
645 if (!intr_info)
646 return IRQ_NONE;
647
648 mrioc = intr_info->mrioc;
649
650 if (!mrioc->intr_enabled)
651 return IRQ_NONE;
652
653 midx = intr_info->msix_index;
654
655 if (!midx)
656 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
657 if (intr_info->op_reply_q)
658 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
659 intr_info->op_reply_q);
660
661 if (num_admin_replies || num_op_reply)
662 return IRQ_HANDLED;
663 else
664 return IRQ_NONE;
665 }
666
667 #ifndef CONFIG_PREEMPT_RT
668
mpi3mr_isr(int irq,void * privdata)669 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
670 {
671 struct mpi3mr_intr_info *intr_info = privdata;
672 int ret;
673
674 if (!intr_info)
675 return IRQ_NONE;
676
677 /* Call primary ISR routine */
678 ret = mpi3mr_isr_primary(irq, privdata);
679
680 /*
681 * If more IOs are expected, schedule IRQ polling thread.
682 * Otherwise exit from ISR.
683 */
684 if (!intr_info->op_reply_q)
685 return ret;
686
687 if (!intr_info->op_reply_q->enable_irq_poll ||
688 !atomic_read(&intr_info->op_reply_q->pend_ios))
689 return ret;
690
691 disable_irq_nosync(intr_info->os_irq);
692
693 return IRQ_WAKE_THREAD;
694 }
695
696 /**
697 * mpi3mr_isr_poll - Reply queue polling routine
698 * @irq: IRQ
699 * @privdata: Interrupt info
700 *
701 * poll for pending I/O completions in a loop until pending I/Os
702 * present or controller queue depth I/Os are processed.
703 *
704 * Return: IRQ_NONE or IRQ_HANDLED
705 */
mpi3mr_isr_poll(int irq,void * privdata)706 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
707 {
708 struct mpi3mr_intr_info *intr_info = privdata;
709 struct mpi3mr_ioc *mrioc;
710 u16 midx;
711 u32 num_op_reply = 0;
712
713 if (!intr_info || !intr_info->op_reply_q)
714 return IRQ_NONE;
715
716 mrioc = intr_info->mrioc;
717 midx = intr_info->msix_index;
718
719 /* Poll for pending IOs completions */
720 do {
721 if (!mrioc->intr_enabled || mrioc->unrecoverable)
722 break;
723
724 if (!midx)
725 mpi3mr_process_admin_reply_q(mrioc);
726 if (intr_info->op_reply_q)
727 num_op_reply +=
728 mpi3mr_process_op_reply_q(mrioc,
729 intr_info->op_reply_q);
730
731 usleep_range(MPI3MR_IRQ_POLL_SLEEP, MPI3MR_IRQ_POLL_SLEEP + 1);
732
733 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
734 (num_op_reply < mrioc->max_host_ios));
735
736 intr_info->op_reply_q->enable_irq_poll = false;
737 enable_irq(intr_info->os_irq);
738
739 return IRQ_HANDLED;
740 }
741
742 #endif
743
744 /**
745 * mpi3mr_request_irq - Request IRQ and register ISR
746 * @mrioc: Adapter instance reference
747 * @index: IRQ vector index
748 *
749 * Request threaded ISR with primary ISR and secondary
750 *
751 * Return: 0 on success and non zero on failures.
752 */
mpi3mr_request_irq(struct mpi3mr_ioc * mrioc,u16 index)753 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
754 {
755 struct pci_dev *pdev = mrioc->pdev;
756 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
757 int retval = 0;
758
759 intr_info->mrioc = mrioc;
760 intr_info->msix_index = index;
761 intr_info->op_reply_q = NULL;
762
763 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
764 mrioc->driver_name, mrioc->id, index);
765
766 #ifndef CONFIG_PREEMPT_RT
767 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
768 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
769 #else
770 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
771 NULL, IRQF_SHARED, intr_info->name, intr_info);
772 #endif
773 if (retval) {
774 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
775 intr_info->name, pci_irq_vector(pdev, index));
776 return retval;
777 }
778
779 intr_info->os_irq = pci_irq_vector(pdev, index);
780 return retval;
781 }
782
mpi3mr_calc_poll_queues(struct mpi3mr_ioc * mrioc,u16 max_vectors)783 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
784 {
785 if (!mrioc->requested_poll_qcount)
786 return;
787
788 /* Reserved for Admin and Default Queue */
789 if (max_vectors > 2 &&
790 (mrioc->requested_poll_qcount < max_vectors - 2)) {
791 ioc_info(mrioc,
792 "enabled polled queues (%d) msix (%d)\n",
793 mrioc->requested_poll_qcount, max_vectors);
794 } else {
795 ioc_info(mrioc,
796 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
797 mrioc->requested_poll_qcount, max_vectors);
798 mrioc->requested_poll_qcount = 0;
799 }
800 }
801
802 /**
803 * mpi3mr_setup_isr - Setup ISR for the controller
804 * @mrioc: Adapter instance reference
805 * @setup_one: Request one IRQ or more
806 *
807 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
808 *
809 * Return: 0 on success and non zero on failures.
810 */
mpi3mr_setup_isr(struct mpi3mr_ioc * mrioc,u8 setup_one)811 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
812 {
813 unsigned int irq_flags = PCI_IRQ_MSIX;
814 int max_vectors, min_vec;
815 int retval;
816 int i;
817 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
818
819 if (mrioc->is_intr_info_set)
820 return 0;
821
822 mpi3mr_cleanup_isr(mrioc);
823
824 if (setup_one || reset_devices) {
825 max_vectors = 1;
826 retval = pci_alloc_irq_vectors(mrioc->pdev,
827 1, max_vectors, irq_flags);
828 if (retval < 0) {
829 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
830 retval);
831 goto out_failed;
832 }
833 } else {
834 max_vectors =
835 min_t(int, mrioc->cpu_count + 1 +
836 mrioc->requested_poll_qcount, mrioc->msix_count);
837
838 mpi3mr_calc_poll_queues(mrioc, max_vectors);
839
840 ioc_info(mrioc,
841 "MSI-X vectors supported: %d, no of cores: %d,",
842 mrioc->msix_count, mrioc->cpu_count);
843 ioc_info(mrioc,
844 "MSI-x vectors requested: %d poll_queues %d\n",
845 max_vectors, mrioc->requested_poll_qcount);
846
847 desc.post_vectors = mrioc->requested_poll_qcount;
848 min_vec = desc.pre_vectors + desc.post_vectors;
849 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
850
851 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
852 min_vec, max_vectors, irq_flags, &desc);
853
854 if (retval < 0) {
855 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
856 retval);
857 goto out_failed;
858 }
859
860
861 /*
862 * If only one MSI-x is allocated, then MSI-x 0 will be shared
863 * between Admin queue and operational queue
864 */
865 if (retval == min_vec)
866 mrioc->op_reply_q_offset = 0;
867 else if (retval != (max_vectors)) {
868 ioc_info(mrioc,
869 "allocated vectors (%d) are less than configured (%d)\n",
870 retval, max_vectors);
871 }
872
873 max_vectors = retval;
874 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
875
876 mpi3mr_calc_poll_queues(mrioc, max_vectors);
877
878 }
879
880 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
881 GFP_KERNEL);
882 if (!mrioc->intr_info) {
883 retval = -ENOMEM;
884 pci_free_irq_vectors(mrioc->pdev);
885 goto out_failed;
886 }
887 for (i = 0; i < max_vectors; i++) {
888 retval = mpi3mr_request_irq(mrioc, i);
889 if (retval) {
890 mrioc->intr_info_count = i;
891 goto out_failed;
892 }
893 }
894 if (reset_devices || !setup_one)
895 mrioc->is_intr_info_set = true;
896 mrioc->intr_info_count = max_vectors;
897 mpi3mr_ioc_enable_intr(mrioc);
898 return 0;
899
900 out_failed:
901 mpi3mr_cleanup_isr(mrioc);
902
903 return retval;
904 }
905
906 static const struct {
907 enum mpi3mr_iocstate value;
908 char *name;
909 } mrioc_states[] = {
910 { MRIOC_STATE_READY, "ready" },
911 { MRIOC_STATE_FAULT, "fault" },
912 { MRIOC_STATE_RESET, "reset" },
913 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
914 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
915 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
916 };
917
mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)918 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
919 {
920 int i;
921 char *name = NULL;
922
923 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
924 if (mrioc_states[i].value == mrioc_state) {
925 name = mrioc_states[i].name;
926 break;
927 }
928 }
929 return name;
930 }
931
932 /* Reset reason to name mapper structure*/
933 static const struct {
934 enum mpi3mr_reset_reason value;
935 char *name;
936 } mpi3mr_reset_reason_codes[] = {
937 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
938 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
939 { MPI3MR_RESET_FROM_APP, "application invocation" },
940 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
941 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
942 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
943 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
944 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
945 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
946 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
947 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
948 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
949 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
950 {
951 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
952 "create request queue timeout"
953 },
954 {
955 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
956 "create reply queue timeout"
957 },
958 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
959 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
960 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
961 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
962 {
963 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
964 "component image activation timeout"
965 },
966 {
967 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
968 "get package version timeout"
969 },
970 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
971 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
972 {
973 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT,
974 "diagnostic buffer post timeout"
975 },
976 {
977 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT,
978 "diagnostic buffer release timeout"
979 },
980 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
981 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
982 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
983 };
984
985 /**
986 * mpi3mr_reset_rc_name - get reset reason code name
987 * @reason_code: reset reason code value
988 *
989 * Map reset reason to an NULL terminated ASCII string
990 *
991 * Return: name corresponding to reset reason value or NULL.
992 */
mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)993 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
994 {
995 int i;
996 char *name = NULL;
997
998 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
999 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
1000 name = mpi3mr_reset_reason_codes[i].name;
1001 break;
1002 }
1003 }
1004 return name;
1005 }
1006
1007 /* Reset type to name mapper structure*/
1008 static const struct {
1009 u16 reset_type;
1010 char *name;
1011 } mpi3mr_reset_types[] = {
1012 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
1013 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
1014 };
1015
1016 /**
1017 * mpi3mr_reset_type_name - get reset type name
1018 * @reset_type: reset type value
1019 *
1020 * Map reset type to an NULL terminated ASCII string
1021 *
1022 * Return: name corresponding to reset type value or NULL.
1023 */
mpi3mr_reset_type_name(u16 reset_type)1024 static const char *mpi3mr_reset_type_name(u16 reset_type)
1025 {
1026 int i;
1027 char *name = NULL;
1028
1029 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
1030 if (mpi3mr_reset_types[i].reset_type == reset_type) {
1031 name = mpi3mr_reset_types[i].name;
1032 break;
1033 }
1034 }
1035 return name;
1036 }
1037
1038 /**
1039 * mpi3mr_is_fault_recoverable - Read fault code and decide
1040 * whether the controller can be recoverable
1041 * @mrioc: Adapter instance reference
1042 * Return: true if fault is recoverable, false otherwise.
1043 */
mpi3mr_is_fault_recoverable(struct mpi3mr_ioc * mrioc)1044 static inline bool mpi3mr_is_fault_recoverable(struct mpi3mr_ioc *mrioc)
1045 {
1046 u32 fault;
1047
1048 fault = (readl(&mrioc->sysif_regs->fault) &
1049 MPI3_SYSIF_FAULT_CODE_MASK);
1050
1051 switch (fault) {
1052 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
1053 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
1054 ioc_warn(mrioc,
1055 "controller requires system power cycle, marking controller as unrecoverable\n");
1056 return false;
1057 case MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER:
1058 ioc_warn(mrioc,
1059 "controller faulted due to insufficient power,\n"
1060 " try by connecting it to a different slot\n");
1061 return false;
1062 default:
1063 break;
1064 }
1065 return true;
1066 }
1067
1068 /**
1069 * mpi3mr_print_fault_info - Display fault information
1070 * @mrioc: Adapter instance reference
1071 *
1072 * Display the controller fault information if there is a
1073 * controller fault.
1074 *
1075 * Return: Nothing.
1076 */
mpi3mr_print_fault_info(struct mpi3mr_ioc * mrioc)1077 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1078 {
1079 u32 ioc_status, code, code1, code2, code3;
1080
1081 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1082
1083 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1084 code = readl(&mrioc->sysif_regs->fault);
1085 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1086 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1087 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1088
1089 ioc_info(mrioc,
1090 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1091 code, code1, code2, code3);
1092 }
1093 }
1094
1095 /**
1096 * mpi3mr_get_iocstate - Get IOC State
1097 * @mrioc: Adapter instance reference
1098 *
1099 * Return a proper IOC state enum based on the IOC status and
1100 * IOC configuration and unrcoverable state of the controller.
1101 *
1102 * Return: Current IOC state.
1103 */
mpi3mr_get_iocstate(struct mpi3mr_ioc * mrioc)1104 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1105 {
1106 u32 ioc_status, ioc_config;
1107 u8 ready, enabled;
1108
1109 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1110 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1111
1112 if (mrioc->unrecoverable)
1113 return MRIOC_STATE_UNRECOVERABLE;
1114 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1115 return MRIOC_STATE_FAULT;
1116
1117 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1118 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1119
1120 if (ready && enabled)
1121 return MRIOC_STATE_READY;
1122 if ((!ready) && (!enabled))
1123 return MRIOC_STATE_RESET;
1124 if ((!ready) && (enabled))
1125 return MRIOC_STATE_BECOMING_READY;
1126
1127 return MRIOC_STATE_RESET_REQUESTED;
1128 }
1129
1130 /**
1131 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma
1132 * @mrioc: Adapter instance reference
1133 *
1134 * Free the DMA memory allocated for IOCTL handling purpose.
1135 *
1136 * Return: None
1137 */
mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc * mrioc)1138 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1139 {
1140 struct dma_memory_desc *mem_desc;
1141 u16 i;
1142
1143 if (!mrioc->ioctl_dma_pool)
1144 return;
1145
1146 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1147 mem_desc = &mrioc->ioctl_sge[i];
1148 if (mem_desc->addr) {
1149 dma_pool_free(mrioc->ioctl_dma_pool,
1150 mem_desc->addr,
1151 mem_desc->dma_addr);
1152 mem_desc->addr = NULL;
1153 }
1154 }
1155 dma_pool_destroy(mrioc->ioctl_dma_pool);
1156 mrioc->ioctl_dma_pool = NULL;
1157 mem_desc = &mrioc->ioctl_chain_sge;
1158
1159 if (mem_desc->addr) {
1160 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1161 mem_desc->addr, mem_desc->dma_addr);
1162 mem_desc->addr = NULL;
1163 }
1164 mem_desc = &mrioc->ioctl_resp_sge;
1165 if (mem_desc->addr) {
1166 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1167 mem_desc->addr, mem_desc->dma_addr);
1168 mem_desc->addr = NULL;
1169 }
1170
1171 mrioc->ioctl_sges_allocated = false;
1172 }
1173
1174 /**
1175 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma
1176 * @mrioc: Adapter instance reference
1177 *
1178 * This function allocates dmaable memory required to handle the
1179 * application issued MPI3 IOCTL requests.
1180 *
1181 * Return: None
1182 */
mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc * mrioc)1183 static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1184
1185 {
1186 struct dma_memory_desc *mem_desc;
1187 u16 i;
1188
1189 mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool",
1190 &mrioc->pdev->dev,
1191 MPI3MR_IOCTL_SGE_SIZE,
1192 MPI3MR_PAGE_SIZE_4K, 0);
1193
1194 if (!mrioc->ioctl_dma_pool) {
1195 ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n");
1196 goto out_failed;
1197 }
1198
1199 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1200 mem_desc = &mrioc->ioctl_sge[i];
1201 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE;
1202 mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool,
1203 GFP_KERNEL,
1204 &mem_desc->dma_addr);
1205 if (!mem_desc->addr)
1206 goto out_failed;
1207 }
1208
1209 mem_desc = &mrioc->ioctl_chain_sge;
1210 mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1211 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1212 mem_desc->size,
1213 &mem_desc->dma_addr,
1214 GFP_KERNEL);
1215 if (!mem_desc->addr)
1216 goto out_failed;
1217
1218 mem_desc = &mrioc->ioctl_resp_sge;
1219 mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1220 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1221 mem_desc->size,
1222 &mem_desc->dma_addr,
1223 GFP_KERNEL);
1224 if (!mem_desc->addr)
1225 goto out_failed;
1226
1227 mrioc->ioctl_sges_allocated = true;
1228
1229 return;
1230 out_failed:
1231 ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n"
1232 "from the applications, application interface for MPT command is disabled\n");
1233 mpi3mr_free_ioctl_dma_memory(mrioc);
1234 }
1235
1236 /**
1237 * mpi3mr_clear_reset_history - clear reset history
1238 * @mrioc: Adapter instance reference
1239 *
1240 * Write the reset history bit in IOC status to clear the bit,
1241 * if it is already set.
1242 *
1243 * Return: Nothing.
1244 */
mpi3mr_clear_reset_history(struct mpi3mr_ioc * mrioc)1245 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1246 {
1247 u32 ioc_status;
1248
1249 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1250 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1251 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1252 }
1253
1254 /**
1255 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1256 * @mrioc: Adapter instance reference
1257 * @reset_reason: Reset reason code
1258 *
1259 * Issue Message unit Reset to the controller and wait for it to
1260 * be complete.
1261 *
1262 * Return: 0 on success, -1 on failure.
1263 */
mpi3mr_issue_and_process_mur(struct mpi3mr_ioc * mrioc,u32 reset_reason)1264 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1265 u32 reset_reason)
1266 {
1267 u32 ioc_config, timeout, ioc_status, scratch_pad0;
1268 int retval = -1;
1269
1270 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1271 if (mrioc->unrecoverable) {
1272 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1273 return retval;
1274 }
1275 mpi3mr_clear_reset_history(mrioc);
1276 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1277 MPI3MR_RESET_REASON_OSTYPE_SHIFT) |
1278 (mrioc->facts.ioc_num <<
1279 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1280 writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
1281 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1282 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1283 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1284
1285 timeout = MPI3MR_MUR_TIMEOUT * 10;
1286 do {
1287 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1288 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1289 mpi3mr_clear_reset_history(mrioc);
1290 break;
1291 }
1292 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1293 mpi3mr_print_fault_info(mrioc);
1294 break;
1295 }
1296 msleep(100);
1297 } while (--timeout);
1298
1299 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1300 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1301 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1302 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1303 retval = 0;
1304
1305 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1306 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1307 return retval;
1308 }
1309
1310 /**
1311 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1312 * during reset/resume
1313 * @mrioc: Adapter instance reference
1314 *
1315 * Return: zero if the new IOCFacts parameters value is compatible with
1316 * older values else return -EPERM
1317 */
1318 static int
mpi3mr_revalidate_factsdata(struct mpi3mr_ioc * mrioc)1319 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1320 {
1321 unsigned long *removepend_bitmap;
1322
1323 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1324 ioc_err(mrioc,
1325 "cannot increase reply size from %d to %d\n",
1326 mrioc->reply_sz, mrioc->facts.reply_sz);
1327 return -EPERM;
1328 }
1329
1330 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1331 ioc_err(mrioc,
1332 "cannot reduce number of operational reply queues from %d to %d\n",
1333 mrioc->num_op_reply_q,
1334 mrioc->facts.max_op_reply_q);
1335 return -EPERM;
1336 }
1337
1338 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1339 ioc_err(mrioc,
1340 "cannot reduce number of operational request queues from %d to %d\n",
1341 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1342 return -EPERM;
1343 }
1344
1345 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512))
1346 ioc_err(mrioc, "Warning: The maximum data transfer length\n"
1347 "\tchanged after reset: previous(%d), new(%d),\n"
1348 "the driver cannot change this at run time\n",
1349 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
1350
1351 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1352 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED))
1353 ioc_err(mrioc,
1354 "critical error: multipath capability is enabled at the\n"
1355 "\tcontroller while sas transport support is enabled at the\n"
1356 "\tdriver, please reboot the system or reload the driver\n");
1357
1358 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1359 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1360 GFP_KERNEL);
1361 if (!removepend_bitmap) {
1362 ioc_err(mrioc,
1363 "failed to increase removepend_bitmap bits from %d to %d\n",
1364 mrioc->dev_handle_bitmap_bits,
1365 mrioc->facts.max_devhandle);
1366 return -EPERM;
1367 }
1368 bitmap_free(mrioc->removepend_bitmap);
1369 mrioc->removepend_bitmap = removepend_bitmap;
1370 ioc_info(mrioc,
1371 "increased bits of dev_handle_bitmap from %d to %d\n",
1372 mrioc->dev_handle_bitmap_bits,
1373 mrioc->facts.max_devhandle);
1374 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1375 }
1376
1377 return 0;
1378 }
1379
1380 /**
1381 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1382 * @mrioc: Adapter instance reference
1383 *
1384 * Set Enable IOC bit in IOC configuration register and wait for
1385 * the controller to become ready.
1386 *
1387 * Return: 0 on success, appropriate error on failure.
1388 */
mpi3mr_bring_ioc_ready(struct mpi3mr_ioc * mrioc)1389 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1390 {
1391 u32 ioc_config, ioc_status, timeout, host_diagnostic;
1392 int retval = 0;
1393 enum mpi3mr_iocstate ioc_state;
1394 u64 base_info;
1395 u8 retry = 0;
1396 u64 start_time, elapsed_time_sec;
1397
1398 retry_bring_ioc_ready:
1399
1400 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1401 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1402 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1403 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1404 ioc_status, ioc_config, base_info);
1405
1406 if (!mpi3mr_is_fault_recoverable(mrioc)) {
1407 mrioc->unrecoverable = 1;
1408 goto out_device_not_present;
1409 }
1410
1411 /*The timeout value is in 2sec unit, changing it to seconds*/
1412 mrioc->ready_timeout =
1413 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1414 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1415
1416 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1417
1418 ioc_state = mpi3mr_get_iocstate(mrioc);
1419 ioc_info(mrioc, "controller is in %s state during detection\n",
1420 mpi3mr_iocstate_name(ioc_state));
1421
1422 timeout = mrioc->ready_timeout * 10;
1423
1424 do {
1425 ioc_state = mpi3mr_get_iocstate(mrioc);
1426
1427 if (ioc_state != MRIOC_STATE_BECOMING_READY &&
1428 ioc_state != MRIOC_STATE_RESET_REQUESTED)
1429 break;
1430
1431 if (!pci_device_is_present(mrioc->pdev)) {
1432 mrioc->unrecoverable = 1;
1433 ioc_err(mrioc, "controller is not present while waiting to reset\n");
1434 goto out_device_not_present;
1435 }
1436
1437 msleep(100);
1438 } while (--timeout);
1439
1440 if (ioc_state == MRIOC_STATE_READY) {
1441 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1442 retval = mpi3mr_issue_and_process_mur(mrioc,
1443 MPI3MR_RESET_FROM_BRINGUP);
1444 ioc_state = mpi3mr_get_iocstate(mrioc);
1445 if (retval)
1446 ioc_err(mrioc,
1447 "message unit reset failed with error %d current state %s\n",
1448 retval, mpi3mr_iocstate_name(ioc_state));
1449 }
1450 if (ioc_state != MRIOC_STATE_RESET) {
1451 if (ioc_state == MRIOC_STATE_FAULT) {
1452 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1453 mpi3mr_print_fault_info(mrioc);
1454 do {
1455 host_diagnostic =
1456 readl(&mrioc->sysif_regs->host_diagnostic);
1457 if (!(host_diagnostic &
1458 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1459 break;
1460 if (!pci_device_is_present(mrioc->pdev)) {
1461 mrioc->unrecoverable = 1;
1462 ioc_err(mrioc, "controller is not present at the bringup\n");
1463 goto out_device_not_present;
1464 }
1465 msleep(100);
1466 } while (--timeout);
1467 }
1468 mpi3mr_print_fault_info(mrioc);
1469 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1470 retval = mpi3mr_issue_reset(mrioc,
1471 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1472 MPI3MR_RESET_FROM_BRINGUP);
1473 if (retval) {
1474 ioc_err(mrioc,
1475 "soft reset failed with error %d\n", retval);
1476 goto out_failed;
1477 }
1478 }
1479 ioc_state = mpi3mr_get_iocstate(mrioc);
1480 if (ioc_state != MRIOC_STATE_RESET) {
1481 ioc_err(mrioc,
1482 "cannot bring controller to reset state, current state: %s\n",
1483 mpi3mr_iocstate_name(ioc_state));
1484 goto out_failed;
1485 }
1486 mpi3mr_clear_reset_history(mrioc);
1487 retval = mpi3mr_setup_admin_qpair(mrioc);
1488 if (retval) {
1489 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1490 retval);
1491 goto out_failed;
1492 }
1493
1494 ioc_info(mrioc, "bringing controller to ready state\n");
1495 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1496 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1497 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1498
1499 if (retry == 0)
1500 start_time = jiffies;
1501
1502 timeout = mrioc->ready_timeout * 10;
1503 do {
1504 ioc_state = mpi3mr_get_iocstate(mrioc);
1505 if (ioc_state == MRIOC_STATE_READY) {
1506 ioc_info(mrioc,
1507 "successfully transitioned to %s state\n",
1508 mpi3mr_iocstate_name(ioc_state));
1509 return 0;
1510 }
1511 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1512 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
1513 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
1514 mpi3mr_print_fault_info(mrioc);
1515 goto out_failed;
1516 }
1517 if (!pci_device_is_present(mrioc->pdev)) {
1518 mrioc->unrecoverable = 1;
1519 ioc_err(mrioc,
1520 "controller is not present at the bringup\n");
1521 retval = -1;
1522 goto out_device_not_present;
1523 }
1524 msleep(100);
1525 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1526 } while (elapsed_time_sec < mrioc->ready_timeout);
1527
1528 out_failed:
1529 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1530 if ((retry < 2) && (elapsed_time_sec < (mrioc->ready_timeout - 60))) {
1531 retry++;
1532
1533 ioc_warn(mrioc, "retrying to bring IOC ready, retry_count:%d\n"
1534 " elapsed time =%llu\n", retry, elapsed_time_sec);
1535
1536 goto retry_bring_ioc_ready;
1537 }
1538 ioc_state = mpi3mr_get_iocstate(mrioc);
1539 ioc_err(mrioc,
1540 "failed to bring to ready state, current state: %s\n",
1541 mpi3mr_iocstate_name(ioc_state));
1542 out_device_not_present:
1543 return retval;
1544 }
1545
1546 /**
1547 * mpi3mr_soft_reset_success - Check softreset is success or not
1548 * @ioc_status: IOC status register value
1549 * @ioc_config: IOC config register value
1550 *
1551 * Check whether the soft reset is successful or not based on
1552 * IOC status and IOC config register values.
1553 *
1554 * Return: True when the soft reset is success, false otherwise.
1555 */
1556 static inline bool
mpi3mr_soft_reset_success(u32 ioc_status,u32 ioc_config)1557 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1558 {
1559 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1560 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1561 return true;
1562 return false;
1563 }
1564
1565 /**
1566 * mpi3mr_diagfault_success - Check diag fault is success or not
1567 * @mrioc: Adapter reference
1568 * @ioc_status: IOC status register value
1569 *
1570 * Check whether the controller hit diag reset fault code.
1571 *
1572 * Return: True when there is diag fault, false otherwise.
1573 */
mpi3mr_diagfault_success(struct mpi3mr_ioc * mrioc,u32 ioc_status)1574 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1575 u32 ioc_status)
1576 {
1577 u32 fault;
1578
1579 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1580 return false;
1581 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1582 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1583 mpi3mr_print_fault_info(mrioc);
1584 return true;
1585 }
1586 return false;
1587 }
1588
1589 /**
1590 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1591 * @mrioc: Adapter reference
1592 *
1593 * Set diag save bit in IOC configuration register to enable
1594 * snapdump.
1595 *
1596 * Return: Nothing.
1597 */
mpi3mr_set_diagsave(struct mpi3mr_ioc * mrioc)1598 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1599 {
1600 u32 ioc_config;
1601
1602 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1603 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1604 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1605 }
1606
1607 /**
1608 * mpi3mr_issue_reset - Issue reset to the controller
1609 * @mrioc: Adapter reference
1610 * @reset_type: Reset type
1611 * @reset_reason: Reset reason code
1612 *
1613 * Unlock the host diagnostic registers and write the specific
1614 * reset type to that, wait for reset acknowledgment from the
1615 * controller, if the reset is not successful retry for the
1616 * predefined number of times.
1617 *
1618 * Return: 0 on success, non-zero on failure.
1619 */
mpi3mr_issue_reset(struct mpi3mr_ioc * mrioc,u16 reset_type,u16 reset_reason)1620 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1621 u16 reset_reason)
1622 {
1623 int retval = -1;
1624 u8 unlock_retry_count = 0;
1625 u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0;
1626 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1627
1628 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1629 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1630 return retval;
1631 if (mrioc->unrecoverable)
1632 return retval;
1633 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1634 retval = 0;
1635 return retval;
1636 }
1637
1638 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1639 mpi3mr_reset_type_name(reset_type),
1640 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1641
1642 mpi3mr_clear_reset_history(mrioc);
1643 do {
1644 ioc_info(mrioc,
1645 "Write magic sequence to unlock host diag register (retry=%d)\n",
1646 ++unlock_retry_count);
1647 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1648 ioc_err(mrioc,
1649 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1650 mpi3mr_reset_type_name(reset_type),
1651 host_diagnostic);
1652 mrioc->unrecoverable = 1;
1653 return retval;
1654 }
1655
1656 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1657 &mrioc->sysif_regs->write_sequence);
1658 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1659 &mrioc->sysif_regs->write_sequence);
1660 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1661 &mrioc->sysif_regs->write_sequence);
1662 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1663 &mrioc->sysif_regs->write_sequence);
1664 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1665 &mrioc->sysif_regs->write_sequence);
1666 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1667 &mrioc->sysif_regs->write_sequence);
1668 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1669 &mrioc->sysif_regs->write_sequence);
1670 usleep_range(1000, 1100);
1671 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1672 ioc_info(mrioc,
1673 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1674 unlock_retry_count, host_diagnostic);
1675 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1676
1677 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1678 MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num <<
1679 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1680 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1681 writel(host_diagnostic | reset_type,
1682 &mrioc->sysif_regs->host_diagnostic);
1683 switch (reset_type) {
1684 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1685 do {
1686 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1687 ioc_config =
1688 readl(&mrioc->sysif_regs->ioc_configuration);
1689 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1690 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1691 ) {
1692 mpi3mr_clear_reset_history(mrioc);
1693 retval = 0;
1694 break;
1695 }
1696 msleep(100);
1697 } while (--timeout);
1698 mpi3mr_print_fault_info(mrioc);
1699 break;
1700 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1701 do {
1702 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1703 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1704 retval = 0;
1705 break;
1706 }
1707 msleep(100);
1708 } while (--timeout);
1709 break;
1710 default:
1711 break;
1712 }
1713
1714 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1715 &mrioc->sysif_regs->write_sequence);
1716
1717 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1718 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1719 ioc_info(mrioc,
1720 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1721 (!retval)?"successful":"failed", ioc_status,
1722 ioc_config);
1723 if (retval)
1724 mrioc->unrecoverable = 1;
1725 return retval;
1726 }
1727
1728 /**
1729 * mpi3mr_admin_request_post - Post request to admin queue
1730 * @mrioc: Adapter reference
1731 * @admin_req: MPI3 request
1732 * @admin_req_sz: Request size
1733 * @ignore_reset: Ignore reset in process
1734 *
1735 * Post the MPI3 request into admin request queue and
1736 * inform the controller, if the queue is full return
1737 * appropriate error.
1738 *
1739 * Return: 0 on success, non-zero on failure.
1740 */
mpi3mr_admin_request_post(struct mpi3mr_ioc * mrioc,void * admin_req,u16 admin_req_sz,u8 ignore_reset)1741 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1742 u16 admin_req_sz, u8 ignore_reset)
1743 {
1744 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1745 int retval = 0;
1746 unsigned long flags;
1747 u8 *areq_entry;
1748
1749 if (mrioc->unrecoverable) {
1750 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1751 return -EFAULT;
1752 }
1753
1754 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1755 areq_pi = mrioc->admin_req_pi;
1756 areq_ci = mrioc->admin_req_ci;
1757 max_entries = mrioc->num_admin_req;
1758 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1759 (areq_pi == (max_entries - 1)))) {
1760 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1761 retval = -EAGAIN;
1762 goto out;
1763 }
1764 if (!ignore_reset && mrioc->reset_in_progress) {
1765 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1766 retval = -EAGAIN;
1767 goto out;
1768 }
1769 if (mrioc->pci_err_recovery) {
1770 ioc_err(mrioc, "admin request queue submission failed due to pci error recovery in progress\n");
1771 retval = -EAGAIN;
1772 goto out;
1773 }
1774
1775 areq_entry = (u8 *)mrioc->admin_req_base +
1776 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1777 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1778 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1779
1780 if (++areq_pi == max_entries)
1781 areq_pi = 0;
1782 mrioc->admin_req_pi = areq_pi;
1783
1784 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1785
1786 out:
1787 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1788
1789 return retval;
1790 }
1791
1792 /**
1793 * mpi3mr_free_op_req_q_segments - free request memory segments
1794 * @mrioc: Adapter instance reference
1795 * @q_idx: operational request queue index
1796 *
1797 * Free memory segments allocated for operational request queue
1798 *
1799 * Return: Nothing.
1800 */
mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1801 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1802 {
1803 u16 j;
1804 int size;
1805 struct segments *segments;
1806
1807 segments = mrioc->req_qinfo[q_idx].q_segments;
1808 if (!segments)
1809 return;
1810
1811 if (mrioc->enable_segqueue) {
1812 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1813 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1814 dma_free_coherent(&mrioc->pdev->dev,
1815 MPI3MR_MAX_SEG_LIST_SIZE,
1816 mrioc->req_qinfo[q_idx].q_segment_list,
1817 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1818 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1819 }
1820 } else
1821 size = mrioc->req_qinfo[q_idx].segment_qd *
1822 mrioc->facts.op_req_sz;
1823
1824 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1825 if (!segments[j].segment)
1826 continue;
1827 dma_free_coherent(&mrioc->pdev->dev,
1828 size, segments[j].segment, segments[j].segment_dma);
1829 segments[j].segment = NULL;
1830 }
1831 kfree(mrioc->req_qinfo[q_idx].q_segments);
1832 mrioc->req_qinfo[q_idx].q_segments = NULL;
1833 mrioc->req_qinfo[q_idx].qid = 0;
1834 }
1835
1836 /**
1837 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1838 * @mrioc: Adapter instance reference
1839 * @q_idx: operational reply queue index
1840 *
1841 * Free memory segments allocated for operational reply queue
1842 *
1843 * Return: Nothing.
1844 */
mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1845 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1846 {
1847 u16 j;
1848 int size;
1849 struct segments *segments;
1850
1851 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1852 if (!segments)
1853 return;
1854
1855 if (mrioc->enable_segqueue) {
1856 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1857 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1858 dma_free_coherent(&mrioc->pdev->dev,
1859 MPI3MR_MAX_SEG_LIST_SIZE,
1860 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1861 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1862 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1863 }
1864 } else
1865 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1866 mrioc->op_reply_desc_sz;
1867
1868 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1869 if (!segments[j].segment)
1870 continue;
1871 dma_free_coherent(&mrioc->pdev->dev,
1872 size, segments[j].segment, segments[j].segment_dma);
1873 segments[j].segment = NULL;
1874 }
1875
1876 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1877 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1878 mrioc->op_reply_qinfo[q_idx].qid = 0;
1879 }
1880
1881 /**
1882 * mpi3mr_delete_op_reply_q - delete operational reply queue
1883 * @mrioc: Adapter instance reference
1884 * @qidx: operational reply queue index
1885 *
1886 * Delete operatinal reply queue by issuing MPI request
1887 * through admin queue.
1888 *
1889 * Return: 0 on success, non-zero on failure.
1890 */
mpi3mr_delete_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1891 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1892 {
1893 struct mpi3_delete_reply_queue_request delq_req;
1894 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1895 int retval = 0;
1896 u16 reply_qid = 0, midx;
1897
1898 reply_qid = op_reply_q->qid;
1899
1900 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1901
1902 if (!reply_qid) {
1903 retval = -1;
1904 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1905 goto out;
1906 }
1907
1908 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1909 mrioc->active_poll_qcount--;
1910
1911 memset(&delq_req, 0, sizeof(delq_req));
1912 mutex_lock(&mrioc->init_cmds.mutex);
1913 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1914 retval = -1;
1915 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1916 mutex_unlock(&mrioc->init_cmds.mutex);
1917 goto out;
1918 }
1919 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1920 mrioc->init_cmds.is_waiting = 1;
1921 mrioc->init_cmds.callback = NULL;
1922 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1923 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1924 delq_req.queue_id = cpu_to_le16(reply_qid);
1925
1926 init_completion(&mrioc->init_cmds.done);
1927 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1928 1);
1929 if (retval) {
1930 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1931 goto out_unlock;
1932 }
1933 wait_for_completion_timeout(&mrioc->init_cmds.done,
1934 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1935 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1936 ioc_err(mrioc, "delete reply queue timed out\n");
1937 mpi3mr_check_rh_fault_ioc(mrioc,
1938 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1939 retval = -1;
1940 goto out_unlock;
1941 }
1942 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1943 != MPI3_IOCSTATUS_SUCCESS) {
1944 ioc_err(mrioc,
1945 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1946 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1947 mrioc->init_cmds.ioc_loginfo);
1948 retval = -1;
1949 goto out_unlock;
1950 }
1951 mrioc->intr_info[midx].op_reply_q = NULL;
1952
1953 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1954 out_unlock:
1955 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1956 mutex_unlock(&mrioc->init_cmds.mutex);
1957 out:
1958
1959 return retval;
1960 }
1961
1962 /**
1963 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1964 * @mrioc: Adapter instance reference
1965 * @qidx: request queue index
1966 *
1967 * Allocate segmented memory pools for operational reply
1968 * queue.
1969 *
1970 * Return: 0 on success, non-zero on failure.
1971 */
mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1972 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1973 {
1974 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1975 int i, size;
1976 u64 *q_segment_list_entry = NULL;
1977 struct segments *segments;
1978
1979 if (mrioc->enable_segqueue) {
1980 op_reply_q->segment_qd =
1981 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1982
1983 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1984
1985 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1986 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1987 GFP_KERNEL);
1988 if (!op_reply_q->q_segment_list)
1989 return -ENOMEM;
1990 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1991 } else {
1992 op_reply_q->segment_qd = op_reply_q->num_replies;
1993 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1994 }
1995
1996 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1997 op_reply_q->segment_qd);
1998
1999 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
2000 sizeof(struct segments), GFP_KERNEL);
2001 if (!op_reply_q->q_segments)
2002 return -ENOMEM;
2003
2004 segments = op_reply_q->q_segments;
2005 for (i = 0; i < op_reply_q->num_segments; i++) {
2006 segments[i].segment =
2007 dma_alloc_coherent(&mrioc->pdev->dev,
2008 size, &segments[i].segment_dma, GFP_KERNEL);
2009 if (!segments[i].segment)
2010 return -ENOMEM;
2011 if (mrioc->enable_segqueue)
2012 q_segment_list_entry[i] =
2013 (unsigned long)segments[i].segment_dma;
2014 }
2015
2016 return 0;
2017 }
2018
2019 /**
2020 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
2021 * @mrioc: Adapter instance reference
2022 * @qidx: request queue index
2023 *
2024 * Allocate segmented memory pools for operational request
2025 * queue.
2026 *
2027 * Return: 0 on success, non-zero on failure.
2028 */
mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)2029 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
2030 {
2031 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
2032 int i, size;
2033 u64 *q_segment_list_entry = NULL;
2034 struct segments *segments;
2035
2036 if (mrioc->enable_segqueue) {
2037 op_req_q->segment_qd =
2038 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
2039
2040 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
2041
2042 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
2043 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
2044 GFP_KERNEL);
2045 if (!op_req_q->q_segment_list)
2046 return -ENOMEM;
2047 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
2048
2049 } else {
2050 op_req_q->segment_qd = op_req_q->num_requests;
2051 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
2052 }
2053
2054 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
2055 op_req_q->segment_qd);
2056
2057 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
2058 sizeof(struct segments), GFP_KERNEL);
2059 if (!op_req_q->q_segments)
2060 return -ENOMEM;
2061
2062 segments = op_req_q->q_segments;
2063 for (i = 0; i < op_req_q->num_segments; i++) {
2064 segments[i].segment =
2065 dma_alloc_coherent(&mrioc->pdev->dev,
2066 size, &segments[i].segment_dma, GFP_KERNEL);
2067 if (!segments[i].segment)
2068 return -ENOMEM;
2069 if (mrioc->enable_segqueue)
2070 q_segment_list_entry[i] =
2071 (unsigned long)segments[i].segment_dma;
2072 }
2073
2074 return 0;
2075 }
2076
2077 /**
2078 * mpi3mr_create_op_reply_q - create operational reply queue
2079 * @mrioc: Adapter instance reference
2080 * @qidx: operational reply queue index
2081 *
2082 * Create operatinal reply queue by issuing MPI request
2083 * through admin queue.
2084 *
2085 * Return: 0 on success, non-zero on failure.
2086 */
mpi3mr_create_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)2087 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
2088 {
2089 struct mpi3_create_reply_queue_request create_req;
2090 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2091 int retval = 0;
2092 u16 reply_qid = 0, midx;
2093
2094 reply_qid = op_reply_q->qid;
2095
2096 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
2097
2098 if (reply_qid) {
2099 retval = -1;
2100 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
2101 reply_qid);
2102
2103 return retval;
2104 }
2105
2106 reply_qid = qidx + 1;
2107
2108 if (mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) {
2109 if (mrioc->pdev->revision)
2110 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
2111 else
2112 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
2113 } else
2114 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD2K;
2115
2116 op_reply_q->ci = 0;
2117 op_reply_q->ephase = 1;
2118 atomic_set(&op_reply_q->pend_ios, 0);
2119 atomic_set(&op_reply_q->in_use, 0);
2120 op_reply_q->enable_irq_poll = false;
2121 op_reply_q->qfull_watermark =
2122 op_reply_q->num_replies - (MPI3MR_THRESHOLD_REPLY_COUNT * 2);
2123
2124 if (!op_reply_q->q_segments) {
2125 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
2126 if (retval) {
2127 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
2128 goto out;
2129 }
2130 }
2131
2132 memset(&create_req, 0, sizeof(create_req));
2133 mutex_lock(&mrioc->init_cmds.mutex);
2134 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2135 retval = -1;
2136 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
2137 goto out_unlock;
2138 }
2139 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2140 mrioc->init_cmds.is_waiting = 1;
2141 mrioc->init_cmds.callback = NULL;
2142 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2143 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
2144 create_req.queue_id = cpu_to_le16(reply_qid);
2145
2146 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
2147 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
2148 else
2149 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
2150
2151 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
2152 create_req.flags =
2153 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
2154 create_req.msix_index =
2155 cpu_to_le16(mrioc->intr_info[midx].msix_index);
2156 } else {
2157 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
2158 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
2159 reply_qid, midx);
2160 if (!mrioc->active_poll_qcount)
2161 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
2162 mrioc->intr_info_count - 1));
2163 }
2164
2165 if (mrioc->enable_segqueue) {
2166 create_req.flags |=
2167 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2168 create_req.base_address = cpu_to_le64(
2169 op_reply_q->q_segment_list_dma);
2170 } else
2171 create_req.base_address = cpu_to_le64(
2172 op_reply_q->q_segments[0].segment_dma);
2173
2174 create_req.size = cpu_to_le16(op_reply_q->num_replies);
2175
2176 init_completion(&mrioc->init_cmds.done);
2177 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2178 sizeof(create_req), 1);
2179 if (retval) {
2180 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
2181 goto out_unlock;
2182 }
2183 wait_for_completion_timeout(&mrioc->init_cmds.done,
2184 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2185 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2186 ioc_err(mrioc, "create reply queue timed out\n");
2187 mpi3mr_check_rh_fault_ioc(mrioc,
2188 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
2189 retval = -1;
2190 goto out_unlock;
2191 }
2192 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2193 != MPI3_IOCSTATUS_SUCCESS) {
2194 ioc_err(mrioc,
2195 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2196 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2197 mrioc->init_cmds.ioc_loginfo);
2198 retval = -1;
2199 goto out_unlock;
2200 }
2201 op_reply_q->qid = reply_qid;
2202 if (midx < mrioc->intr_info_count)
2203 mrioc->intr_info[midx].op_reply_q = op_reply_q;
2204
2205 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
2206 mrioc->active_poll_qcount++;
2207
2208 out_unlock:
2209 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2210 mutex_unlock(&mrioc->init_cmds.mutex);
2211 out:
2212
2213 return retval;
2214 }
2215
2216 /**
2217 * mpi3mr_create_op_req_q - create operational request queue
2218 * @mrioc: Adapter instance reference
2219 * @idx: operational request queue index
2220 * @reply_qid: Reply queue ID
2221 *
2222 * Create operatinal request queue by issuing MPI request
2223 * through admin queue.
2224 *
2225 * Return: 0 on success, non-zero on failure.
2226 */
mpi3mr_create_op_req_q(struct mpi3mr_ioc * mrioc,u16 idx,u16 reply_qid)2227 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2228 u16 reply_qid)
2229 {
2230 struct mpi3_create_request_queue_request create_req;
2231 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2232 int retval = 0;
2233 u16 req_qid = 0;
2234
2235 req_qid = op_req_q->qid;
2236
2237 if (req_qid) {
2238 retval = -1;
2239 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2240 req_qid);
2241
2242 return retval;
2243 }
2244 req_qid = idx + 1;
2245
2246 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2247 op_req_q->ci = 0;
2248 op_req_q->pi = 0;
2249 op_req_q->reply_qid = reply_qid;
2250 spin_lock_init(&op_req_q->q_lock);
2251
2252 if (!op_req_q->q_segments) {
2253 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2254 if (retval) {
2255 mpi3mr_free_op_req_q_segments(mrioc, idx);
2256 goto out;
2257 }
2258 }
2259
2260 memset(&create_req, 0, sizeof(create_req));
2261 mutex_lock(&mrioc->init_cmds.mutex);
2262 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2263 retval = -1;
2264 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2265 goto out_unlock;
2266 }
2267 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2268 mrioc->init_cmds.is_waiting = 1;
2269 mrioc->init_cmds.callback = NULL;
2270 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2271 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2272 create_req.queue_id = cpu_to_le16(req_qid);
2273 if (mrioc->enable_segqueue) {
2274 create_req.flags =
2275 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2276 create_req.base_address = cpu_to_le64(
2277 op_req_q->q_segment_list_dma);
2278 } else
2279 create_req.base_address = cpu_to_le64(
2280 op_req_q->q_segments[0].segment_dma);
2281 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2282 create_req.size = cpu_to_le16(op_req_q->num_requests);
2283
2284 init_completion(&mrioc->init_cmds.done);
2285 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2286 sizeof(create_req), 1);
2287 if (retval) {
2288 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2289 goto out_unlock;
2290 }
2291 wait_for_completion_timeout(&mrioc->init_cmds.done,
2292 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2293 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2294 ioc_err(mrioc, "create request queue timed out\n");
2295 mpi3mr_check_rh_fault_ioc(mrioc,
2296 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2297 retval = -1;
2298 goto out_unlock;
2299 }
2300 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2301 != MPI3_IOCSTATUS_SUCCESS) {
2302 ioc_err(mrioc,
2303 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2304 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2305 mrioc->init_cmds.ioc_loginfo);
2306 retval = -1;
2307 goto out_unlock;
2308 }
2309 op_req_q->qid = req_qid;
2310
2311 out_unlock:
2312 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2313 mutex_unlock(&mrioc->init_cmds.mutex);
2314 out:
2315
2316 return retval;
2317 }
2318
2319 /**
2320 * mpi3mr_create_op_queues - create operational queue pairs
2321 * @mrioc: Adapter instance reference
2322 *
2323 * Allocate memory for operational queue meta data and call
2324 * create request and reply queue functions.
2325 *
2326 * Return: 0 on success, non-zero on failures.
2327 */
mpi3mr_create_op_queues(struct mpi3mr_ioc * mrioc)2328 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2329 {
2330 int retval = 0;
2331 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2332
2333 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2334 mrioc->facts.max_op_req_q);
2335
2336 msix_count_op_q =
2337 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2338 if (!mrioc->num_queues)
2339 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2340 /*
2341 * During reset set the num_queues to the number of queues
2342 * that was set before the reset.
2343 */
2344 num_queues = mrioc->num_op_reply_q ?
2345 mrioc->num_op_reply_q : mrioc->num_queues;
2346 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2347 num_queues);
2348
2349 if (!mrioc->req_qinfo) {
2350 mrioc->req_qinfo = kcalloc(num_queues,
2351 sizeof(struct op_req_qinfo), GFP_KERNEL);
2352 if (!mrioc->req_qinfo) {
2353 retval = -1;
2354 goto out_failed;
2355 }
2356
2357 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2358 num_queues, GFP_KERNEL);
2359 if (!mrioc->op_reply_qinfo) {
2360 retval = -1;
2361 goto out_failed;
2362 }
2363 }
2364
2365 if (mrioc->enable_segqueue)
2366 ioc_info(mrioc,
2367 "allocating operational queues through segmented queues\n");
2368
2369 for (i = 0; i < num_queues; i++) {
2370 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2371 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2372 break;
2373 }
2374 if (mpi3mr_create_op_req_q(mrioc, i,
2375 mrioc->op_reply_qinfo[i].qid)) {
2376 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2377 mpi3mr_delete_op_reply_q(mrioc, i);
2378 break;
2379 }
2380 }
2381
2382 if (i == 0) {
2383 /* Not even one queue is created successfully*/
2384 retval = -1;
2385 goto out_failed;
2386 }
2387 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2388 ioc_info(mrioc,
2389 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2390 mrioc->num_op_reply_q, mrioc->default_qcount,
2391 mrioc->active_poll_qcount);
2392
2393 return retval;
2394 out_failed:
2395 kfree(mrioc->req_qinfo);
2396 mrioc->req_qinfo = NULL;
2397
2398 kfree(mrioc->op_reply_qinfo);
2399 mrioc->op_reply_qinfo = NULL;
2400
2401 return retval;
2402 }
2403
2404 /**
2405 * mpi3mr_op_request_post - Post request to operational queue
2406 * @mrioc: Adapter reference
2407 * @op_req_q: Operational request queue info
2408 * @req: MPI3 request
2409 *
2410 * Post the MPI3 request into operational request queue and
2411 * inform the controller, if the queue is full return
2412 * appropriate error.
2413 *
2414 * Return: 0 on success, non-zero on failure.
2415 */
mpi3mr_op_request_post(struct mpi3mr_ioc * mrioc,struct op_req_qinfo * op_req_q,u8 * req)2416 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2417 struct op_req_qinfo *op_req_q, u8 *req)
2418 {
2419 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2420 int retval = 0;
2421 unsigned long flags;
2422 u8 *req_entry;
2423 void *segment_base_addr;
2424 u16 req_sz = mrioc->facts.op_req_sz;
2425 struct segments *segments = op_req_q->q_segments;
2426 struct op_reply_qinfo *op_reply_q = NULL;
2427
2428 reply_qidx = op_req_q->reply_qid - 1;
2429 op_reply_q = mrioc->op_reply_qinfo + reply_qidx;
2430
2431 if (mrioc->unrecoverable)
2432 return -EFAULT;
2433
2434 spin_lock_irqsave(&op_req_q->q_lock, flags);
2435 pi = op_req_q->pi;
2436 max_entries = op_req_q->num_requests;
2437
2438 if (mpi3mr_check_req_qfull(op_req_q)) {
2439 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2440 reply_qidx, mrioc->op_reply_q_offset);
2441 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2442
2443 if (mpi3mr_check_req_qfull(op_req_q)) {
2444 retval = -EAGAIN;
2445 goto out;
2446 }
2447 }
2448
2449 if (mrioc->reset_in_progress) {
2450 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2451 retval = -EAGAIN;
2452 goto out;
2453 }
2454 if (mrioc->pci_err_recovery) {
2455 ioc_err(mrioc, "operational request queue submission failed due to pci error recovery in progress\n");
2456 retval = -EAGAIN;
2457 goto out;
2458 }
2459
2460 /* Reply queue is nearing to get full, push back IOs to SML */
2461 if ((mrioc->prevent_reply_qfull == true) &&
2462 (atomic_read(&op_reply_q->pend_ios) >
2463 (op_reply_q->qfull_watermark))) {
2464 atomic_inc(&mrioc->reply_qfull_count);
2465 retval = -EAGAIN;
2466 goto out;
2467 }
2468
2469 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2470 req_entry = (u8 *)segment_base_addr +
2471 ((pi % op_req_q->segment_qd) * req_sz);
2472
2473 memset(req_entry, 0, req_sz);
2474 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2475
2476 if (++pi == max_entries)
2477 pi = 0;
2478 op_req_q->pi = pi;
2479
2480 #ifndef CONFIG_PREEMPT_RT
2481 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2482 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2483 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2484 #else
2485 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2486 #endif
2487
2488 writel(op_req_q->pi,
2489 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2490
2491 out:
2492 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2493 return retval;
2494 }
2495
2496 /**
2497 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2498 * controller
2499 * @mrioc: Adapter instance reference
2500 * @reason_code: reason code for the fault.
2501 *
2502 * This routine will save snapdump and fault the controller with
2503 * the given reason code if it is not already in the fault or
2504 * not asynchronosuly reset. This will be used to handle
2505 * initilaization time faults/resets/timeout as in those cases
2506 * immediate soft reset invocation is not required.
2507 *
2508 * Return: None.
2509 */
mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc * mrioc,u32 reason_code)2510 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2511 {
2512 u32 ioc_status, host_diagnostic, timeout;
2513 union mpi3mr_trigger_data trigger_data;
2514
2515 if (mrioc->unrecoverable) {
2516 ioc_err(mrioc, "controller is unrecoverable\n");
2517 return;
2518 }
2519
2520 if (!pci_device_is_present(mrioc->pdev)) {
2521 mrioc->unrecoverable = 1;
2522 ioc_err(mrioc, "controller is not present\n");
2523 return;
2524 }
2525 memset(&trigger_data, 0, sizeof(trigger_data));
2526 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2527
2528 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2529 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2530 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2531 return;
2532 } else if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
2533 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2534 MPI3_SYSIF_FAULT_CODE_MASK);
2535
2536 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2537 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2538 mpi3mr_print_fault_info(mrioc);
2539 return;
2540 }
2541
2542 mpi3mr_set_diagsave(mrioc);
2543 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2544 reason_code);
2545 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2546 MPI3_SYSIF_FAULT_CODE_MASK);
2547 mpi3mr_set_trigger_data_in_all_hdb(mrioc, MPI3MR_HDB_TRIGGER_TYPE_FAULT,
2548 &trigger_data, 0);
2549 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2550 do {
2551 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2552 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2553 break;
2554 msleep(100);
2555 } while (--timeout);
2556 }
2557
2558 /**
2559 * mpi3mr_sync_timestamp - Issue time stamp sync request
2560 * @mrioc: Adapter reference
2561 *
2562 * Issue IO unit control MPI request to synchornize firmware
2563 * timestamp with host time.
2564 *
2565 * Return: 0 on success, non-zero on failure.
2566 */
mpi3mr_sync_timestamp(struct mpi3mr_ioc * mrioc)2567 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2568 {
2569 ktime_t current_time;
2570 struct mpi3_iounit_control_request iou_ctrl;
2571 int retval = 0;
2572
2573 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2574 mutex_lock(&mrioc->init_cmds.mutex);
2575 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2576 retval = -1;
2577 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2578 mutex_unlock(&mrioc->init_cmds.mutex);
2579 goto out;
2580 }
2581 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2582 mrioc->init_cmds.is_waiting = 1;
2583 mrioc->init_cmds.callback = NULL;
2584 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2585 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2586 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2587 current_time = ktime_get_real();
2588 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2589
2590 init_completion(&mrioc->init_cmds.done);
2591 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2592 sizeof(iou_ctrl), 0);
2593 if (retval) {
2594 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2595 goto out_unlock;
2596 }
2597
2598 wait_for_completion_timeout(&mrioc->init_cmds.done,
2599 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2600 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2601 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2602 mrioc->init_cmds.is_waiting = 0;
2603 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2604 mpi3mr_check_rh_fault_ioc(mrioc,
2605 MPI3MR_RESET_FROM_TSU_TIMEOUT);
2606 retval = -1;
2607 goto out_unlock;
2608 }
2609 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2610 != MPI3_IOCSTATUS_SUCCESS) {
2611 ioc_err(mrioc,
2612 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2613 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2614 mrioc->init_cmds.ioc_loginfo);
2615 retval = -1;
2616 goto out_unlock;
2617 }
2618
2619 out_unlock:
2620 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2621 mutex_unlock(&mrioc->init_cmds.mutex);
2622
2623 out:
2624 return retval;
2625 }
2626
2627 /**
2628 * mpi3mr_print_pkg_ver - display controller fw package version
2629 * @mrioc: Adapter reference
2630 *
2631 * Retrieve firmware package version from the component image
2632 * header of the controller flash and display it.
2633 *
2634 * Return: 0 on success and non-zero on failure.
2635 */
mpi3mr_print_pkg_ver(struct mpi3mr_ioc * mrioc)2636 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2637 {
2638 struct mpi3_ci_upload_request ci_upload;
2639 int retval = -1;
2640 void *data = NULL;
2641 dma_addr_t data_dma;
2642 struct mpi3_ci_manifest_mpi *manifest;
2643 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2644 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2645
2646 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2647 GFP_KERNEL);
2648 if (!data)
2649 return -ENOMEM;
2650
2651 memset(&ci_upload, 0, sizeof(ci_upload));
2652 mutex_lock(&mrioc->init_cmds.mutex);
2653 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2654 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2655 mutex_unlock(&mrioc->init_cmds.mutex);
2656 goto out;
2657 }
2658 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2659 mrioc->init_cmds.is_waiting = 1;
2660 mrioc->init_cmds.callback = NULL;
2661 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2662 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2663 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2664 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2665 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2666 ci_upload.segment_size = cpu_to_le32(data_len);
2667
2668 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2669 data_dma);
2670 init_completion(&mrioc->init_cmds.done);
2671 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2672 sizeof(ci_upload), 1);
2673 if (retval) {
2674 ioc_err(mrioc, "posting get package version failed\n");
2675 goto out_unlock;
2676 }
2677 wait_for_completion_timeout(&mrioc->init_cmds.done,
2678 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2679 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2680 ioc_err(mrioc, "get package version timed out\n");
2681 mpi3mr_check_rh_fault_ioc(mrioc,
2682 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2683 retval = -1;
2684 goto out_unlock;
2685 }
2686 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2687 == MPI3_IOCSTATUS_SUCCESS) {
2688 manifest = (struct mpi3_ci_manifest_mpi *) data;
2689 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2690 ioc_info(mrioc,
2691 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2692 manifest->package_version.gen_major,
2693 manifest->package_version.gen_minor,
2694 manifest->package_version.phase_major,
2695 manifest->package_version.phase_minor,
2696 manifest->package_version.customer_id,
2697 manifest->package_version.build_num);
2698 }
2699 }
2700 retval = 0;
2701 out_unlock:
2702 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2703 mutex_unlock(&mrioc->init_cmds.mutex);
2704
2705 out:
2706 if (data)
2707 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2708 data_dma);
2709 return retval;
2710 }
2711
2712 /**
2713 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2714 * @work: work struct
2715 *
2716 * Watch dog work periodically executed (1 second interval) to
2717 * monitor firmware fault and to issue periodic timer sync to
2718 * the firmware.
2719 *
2720 * Return: Nothing.
2721 */
mpi3mr_watchdog_work(struct work_struct * work)2722 static void mpi3mr_watchdog_work(struct work_struct *work)
2723 {
2724 struct mpi3mr_ioc *mrioc =
2725 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2726 unsigned long flags;
2727 enum mpi3mr_iocstate ioc_state;
2728 u32 host_diagnostic, ioc_status;
2729 union mpi3mr_trigger_data trigger_data;
2730 u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2731
2732 if (mrioc->reset_in_progress || mrioc->pci_err_recovery)
2733 return;
2734
2735 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2736 ioc_err(mrioc, "watchdog could not detect the controller\n");
2737 mrioc->unrecoverable = 1;
2738 }
2739
2740 if (mrioc->unrecoverable) {
2741 ioc_err(mrioc,
2742 "flush pending commands for unrecoverable controller\n");
2743 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2744 return;
2745 }
2746
2747 if (mrioc->ts_update_counter++ >= mrioc->ts_update_interval) {
2748 mrioc->ts_update_counter = 0;
2749 mpi3mr_sync_timestamp(mrioc);
2750 }
2751
2752 if ((mrioc->prepare_for_reset) &&
2753 ((mrioc->prepare_for_reset_timeout_counter++) >=
2754 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2755 mpi3mr_soft_reset_handler(mrioc,
2756 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2757 return;
2758 }
2759
2760 memset(&trigger_data, 0, sizeof(trigger_data));
2761 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2762 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2763 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2764 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2765 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2766 return;
2767 }
2768
2769 /*Check for fault state every one second and issue Soft reset*/
2770 ioc_state = mpi3mr_get_iocstate(mrioc);
2771 if (ioc_state != MRIOC_STATE_FAULT)
2772 goto schedule_work;
2773
2774 trigger_data.fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2775 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2776 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2777 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2778 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2779 if (!mrioc->diagsave_timeout) {
2780 mpi3mr_print_fault_info(mrioc);
2781 ioc_warn(mrioc, "diag save in progress\n");
2782 }
2783 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2784 goto schedule_work;
2785 }
2786
2787 mpi3mr_print_fault_info(mrioc);
2788 mrioc->diagsave_timeout = 0;
2789
2790 if (!mpi3mr_is_fault_recoverable(mrioc)) {
2791 mrioc->unrecoverable = 1;
2792 goto schedule_work;
2793 }
2794
2795 switch (trigger_data.fault) {
2796 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2797 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2798 ioc_warn(mrioc,
2799 "controller requires system power cycle, marking controller as unrecoverable\n");
2800 mrioc->unrecoverable = 1;
2801 goto schedule_work;
2802 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2803 goto schedule_work;
2804 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2805 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2806 break;
2807 default:
2808 break;
2809 }
2810 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2811 return;
2812
2813 schedule_work:
2814 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2815 if (mrioc->watchdog_work_q)
2816 queue_delayed_work(mrioc->watchdog_work_q,
2817 &mrioc->watchdog_work,
2818 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2819 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2820 return;
2821 }
2822
2823 /**
2824 * mpi3mr_start_watchdog - Start watchdog
2825 * @mrioc: Adapter instance reference
2826 *
2827 * Create and start the watchdog thread to monitor controller
2828 * faults.
2829 *
2830 * Return: Nothing.
2831 */
mpi3mr_start_watchdog(struct mpi3mr_ioc * mrioc)2832 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2833 {
2834 if (mrioc->watchdog_work_q)
2835 return;
2836
2837 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2838 snprintf(mrioc->watchdog_work_q_name,
2839 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2840 mrioc->id);
2841 mrioc->watchdog_work_q = alloc_ordered_workqueue(
2842 "%s", WQ_MEM_RECLAIM, mrioc->watchdog_work_q_name);
2843 if (!mrioc->watchdog_work_q) {
2844 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2845 return;
2846 }
2847
2848 if (mrioc->watchdog_work_q)
2849 queue_delayed_work(mrioc->watchdog_work_q,
2850 &mrioc->watchdog_work,
2851 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2852 }
2853
2854 /**
2855 * mpi3mr_stop_watchdog - Stop watchdog
2856 * @mrioc: Adapter instance reference
2857 *
2858 * Stop the watchdog thread created to monitor controller
2859 * faults.
2860 *
2861 * Return: Nothing.
2862 */
mpi3mr_stop_watchdog(struct mpi3mr_ioc * mrioc)2863 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2864 {
2865 unsigned long flags;
2866 struct workqueue_struct *wq;
2867
2868 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2869 wq = mrioc->watchdog_work_q;
2870 mrioc->watchdog_work_q = NULL;
2871 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2872 if (wq) {
2873 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2874 flush_workqueue(wq);
2875 destroy_workqueue(wq);
2876 }
2877 }
2878
2879 /**
2880 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2881 * @mrioc: Adapter instance reference
2882 *
2883 * Allocate memory for admin queue pair if required and register
2884 * the admin queue with the controller.
2885 *
2886 * Return: 0 on success, non-zero on failures.
2887 */
mpi3mr_setup_admin_qpair(struct mpi3mr_ioc * mrioc)2888 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2889 {
2890 int retval = 0;
2891 u32 num_admin_entries = 0;
2892
2893 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2894 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2895 MPI3MR_ADMIN_REQ_FRAME_SZ;
2896 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2897
2898 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2899 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2900 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2901 mrioc->admin_reply_ci = 0;
2902 mrioc->admin_reply_ephase = 1;
2903 atomic_set(&mrioc->admin_reply_q_in_use, 0);
2904
2905 if (!mrioc->admin_req_base) {
2906 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2907 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2908
2909 if (!mrioc->admin_req_base) {
2910 retval = -1;
2911 goto out_failed;
2912 }
2913
2914 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2915 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2916 GFP_KERNEL);
2917
2918 if (!mrioc->admin_reply_base) {
2919 retval = -1;
2920 goto out_failed;
2921 }
2922 }
2923
2924 num_admin_entries = (mrioc->num_admin_replies << 16) |
2925 (mrioc->num_admin_req);
2926 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2927 mpi3mr_writeq(mrioc->admin_req_dma,
2928 &mrioc->sysif_regs->admin_request_queue_address);
2929 mpi3mr_writeq(mrioc->admin_reply_dma,
2930 &mrioc->sysif_regs->admin_reply_queue_address);
2931 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2932 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2933 return retval;
2934
2935 out_failed:
2936
2937 if (mrioc->admin_reply_base) {
2938 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2939 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2940 mrioc->admin_reply_base = NULL;
2941 }
2942 if (mrioc->admin_req_base) {
2943 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2944 mrioc->admin_req_base, mrioc->admin_req_dma);
2945 mrioc->admin_req_base = NULL;
2946 }
2947 return retval;
2948 }
2949
2950 /**
2951 * mpi3mr_issue_iocfacts - Send IOC Facts
2952 * @mrioc: Adapter instance reference
2953 * @facts_data: Cached IOC facts data
2954 *
2955 * Issue IOC Facts MPI request through admin queue and wait for
2956 * the completion of it or time out.
2957 *
2958 * Return: 0 on success, non-zero on failures.
2959 */
mpi3mr_issue_iocfacts(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2960 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2961 struct mpi3_ioc_facts_data *facts_data)
2962 {
2963 struct mpi3_ioc_facts_request iocfacts_req;
2964 void *data = NULL;
2965 dma_addr_t data_dma;
2966 u32 data_len = sizeof(*facts_data);
2967 int retval = 0;
2968 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2969
2970 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2971 GFP_KERNEL);
2972
2973 if (!data) {
2974 retval = -1;
2975 goto out;
2976 }
2977
2978 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2979 mutex_lock(&mrioc->init_cmds.mutex);
2980 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2981 retval = -1;
2982 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2983 mutex_unlock(&mrioc->init_cmds.mutex);
2984 goto out;
2985 }
2986 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2987 mrioc->init_cmds.is_waiting = 1;
2988 mrioc->init_cmds.callback = NULL;
2989 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2990 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2991
2992 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2993 data_dma);
2994
2995 init_completion(&mrioc->init_cmds.done);
2996 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2997 sizeof(iocfacts_req), 1);
2998 if (retval) {
2999 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
3000 goto out_unlock;
3001 }
3002 wait_for_completion_timeout(&mrioc->init_cmds.done,
3003 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3004 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3005 ioc_err(mrioc, "ioc_facts timed out\n");
3006 mpi3mr_check_rh_fault_ioc(mrioc,
3007 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
3008 retval = -1;
3009 goto out_unlock;
3010 }
3011 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3012 != MPI3_IOCSTATUS_SUCCESS) {
3013 ioc_err(mrioc,
3014 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3015 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3016 mrioc->init_cmds.ioc_loginfo);
3017 retval = -1;
3018 goto out_unlock;
3019 }
3020 memcpy(facts_data, (u8 *)data, data_len);
3021 mpi3mr_process_factsdata(mrioc, facts_data);
3022 out_unlock:
3023 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3024 mutex_unlock(&mrioc->init_cmds.mutex);
3025
3026 out:
3027 if (data)
3028 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
3029
3030 return retval;
3031 }
3032
3033 /**
3034 * mpi3mr_check_reset_dma_mask - Process IOC facts data
3035 * @mrioc: Adapter instance reference
3036 *
3037 * Check whether the new DMA mask requested through IOCFacts by
3038 * firmware needs to be set, if so set it .
3039 *
3040 * Return: 0 on success, non-zero on failure.
3041 */
mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc * mrioc)3042 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
3043 {
3044 struct pci_dev *pdev = mrioc->pdev;
3045 int r;
3046 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
3047
3048 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
3049 return 0;
3050
3051 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
3052 mrioc->dma_mask, facts_dma_mask);
3053
3054 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
3055 if (r) {
3056 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
3057 facts_dma_mask, r);
3058 return r;
3059 }
3060 mrioc->dma_mask = facts_dma_mask;
3061 return r;
3062 }
3063
3064 /**
3065 * mpi3mr_process_factsdata - Process IOC facts data
3066 * @mrioc: Adapter instance reference
3067 * @facts_data: Cached IOC facts data
3068 *
3069 * Convert IOC facts data into cpu endianness and cache it in
3070 * the driver .
3071 *
3072 * Return: Nothing.
3073 */
mpi3mr_process_factsdata(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)3074 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
3075 struct mpi3_ioc_facts_data *facts_data)
3076 {
3077 u32 ioc_config, req_sz, facts_flags;
3078
3079 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
3080 (sizeof(*facts_data) / 4)) {
3081 ioc_warn(mrioc,
3082 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
3083 sizeof(*facts_data),
3084 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
3085 }
3086
3087 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3088 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
3089 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
3090 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
3091 ioc_err(mrioc,
3092 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
3093 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
3094 }
3095
3096 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
3097
3098 facts_flags = le32_to_cpu(facts_data->flags);
3099 mrioc->facts.op_req_sz = req_sz;
3100 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
3101 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
3102 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
3103
3104 mrioc->facts.ioc_num = facts_data->ioc_number;
3105 mrioc->facts.who_init = facts_data->who_init;
3106 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
3107 mrioc->facts.personality = (facts_flags &
3108 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
3109 mrioc->facts.dma_mask = (facts_flags &
3110 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3111 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3112 mrioc->facts.dma_mask = (facts_flags &
3113 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3114 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3115 mrioc->facts.protocol_flags = facts_data->protocol_flags;
3116 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
3117 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
3118 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
3119 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
3120 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
3121 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
3122 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
3123 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
3124 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
3125 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
3126 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
3127 mrioc->facts.max_pcie_switches =
3128 le16_to_cpu(facts_data->max_pcie_switches);
3129 mrioc->facts.max_sasexpanders =
3130 le16_to_cpu(facts_data->max_sas_expanders);
3131 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length);
3132 mrioc->facts.max_sasinitiators =
3133 le16_to_cpu(facts_data->max_sas_initiators);
3134 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
3135 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
3136 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
3137 mrioc->facts.max_op_req_q =
3138 le16_to_cpu(facts_data->max_operational_request_queues);
3139 mrioc->facts.max_op_reply_q =
3140 le16_to_cpu(facts_data->max_operational_reply_queues);
3141 mrioc->facts.ioc_capabilities =
3142 le32_to_cpu(facts_data->ioc_capabilities);
3143 mrioc->facts.fw_ver.build_num =
3144 le16_to_cpu(facts_data->fw_version.build_num);
3145 mrioc->facts.fw_ver.cust_id =
3146 le16_to_cpu(facts_data->fw_version.customer_id);
3147 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
3148 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
3149 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
3150 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
3151 mrioc->msix_count = min_t(int, mrioc->msix_count,
3152 mrioc->facts.max_msix_vectors);
3153 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
3154 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
3155 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
3156 mrioc->facts.shutdown_timeout =
3157 le16_to_cpu(facts_data->shutdown_timeout);
3158 mrioc->facts.diag_trace_sz =
3159 le32_to_cpu(facts_data->diag_trace_size);
3160 mrioc->facts.diag_fw_sz =
3161 le32_to_cpu(facts_data->diag_fw_size);
3162 mrioc->facts.diag_drvr_sz = le32_to_cpu(facts_data->diag_driver_size);
3163 mrioc->facts.max_dev_per_tg =
3164 facts_data->max_devices_per_throttle_group;
3165 mrioc->facts.io_throttle_data_length =
3166 le16_to_cpu(facts_data->io_throttle_data_length);
3167 mrioc->facts.max_io_throttle_group =
3168 le16_to_cpu(facts_data->max_io_throttle_group);
3169 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
3170 mrioc->facts.io_throttle_high =
3171 le16_to_cpu(facts_data->io_throttle_high);
3172
3173 if (mrioc->facts.max_data_length ==
3174 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED)
3175 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE;
3176 else
3177 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K;
3178 /* Store in 512b block count */
3179 if (mrioc->facts.io_throttle_data_length)
3180 mrioc->io_throttle_data_length =
3181 (mrioc->facts.io_throttle_data_length * 2 * 4);
3182 else
3183 /* set the length to 1MB + 1K to disable throttle */
3184 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2;
3185
3186 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
3187 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
3188
3189 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
3190 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
3191 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
3192 ioc_info(mrioc,
3193 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
3194 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
3195 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
3196 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
3197 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
3198 mrioc->facts.sge_mod_shift);
3199 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n",
3200 mrioc->facts.dma_mask, (facts_flags &
3201 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length);
3202 ioc_info(mrioc,
3203 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
3204 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
3205 ioc_info(mrioc,
3206 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
3207 mrioc->facts.io_throttle_data_length * 4,
3208 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
3209 }
3210
3211 /**
3212 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
3213 * @mrioc: Adapter instance reference
3214 *
3215 * Allocate and initialize the reply free buffers, sense
3216 * buffers, reply free queue and sense buffer queue.
3217 *
3218 * Return: 0 on success, non-zero on failures.
3219 */
mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc * mrioc)3220 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
3221 {
3222 int retval = 0;
3223 u32 sz, i;
3224
3225 if (mrioc->init_cmds.reply)
3226 return retval;
3227
3228 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3229 if (!mrioc->init_cmds.reply)
3230 goto out_failed;
3231
3232 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3233 if (!mrioc->bsg_cmds.reply)
3234 goto out_failed;
3235
3236 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3237 if (!mrioc->transport_cmds.reply)
3238 goto out_failed;
3239
3240 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
3241 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
3242 GFP_KERNEL);
3243 if (!mrioc->dev_rmhs_cmds[i].reply)
3244 goto out_failed;
3245 }
3246
3247 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
3248 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
3249 GFP_KERNEL);
3250 if (!mrioc->evtack_cmds[i].reply)
3251 goto out_failed;
3252 }
3253
3254 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3255 if (!mrioc->host_tm_cmds.reply)
3256 goto out_failed;
3257
3258 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3259 if (!mrioc->pel_cmds.reply)
3260 goto out_failed;
3261
3262 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3263 if (!mrioc->pel_abort_cmd.reply)
3264 goto out_failed;
3265
3266 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
3267 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
3268 GFP_KERNEL);
3269 if (!mrioc->removepend_bitmap)
3270 goto out_failed;
3271
3272 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
3273 if (!mrioc->devrem_bitmap)
3274 goto out_failed;
3275
3276 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
3277 GFP_KERNEL);
3278 if (!mrioc->evtack_cmds_bitmap)
3279 goto out_failed;
3280
3281 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3282 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3283 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3284 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3285
3286 /* reply buffer pool, 16 byte align */
3287 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3288 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3289 &mrioc->pdev->dev, sz, 16, 0);
3290 if (!mrioc->reply_buf_pool) {
3291 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3292 goto out_failed;
3293 }
3294
3295 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3296 &mrioc->reply_buf_dma);
3297 if (!mrioc->reply_buf)
3298 goto out_failed;
3299
3300 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3301
3302 /* reply free queue, 8 byte align */
3303 sz = mrioc->reply_free_qsz * 8;
3304 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3305 &mrioc->pdev->dev, sz, 8, 0);
3306 if (!mrioc->reply_free_q_pool) {
3307 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3308 goto out_failed;
3309 }
3310 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3311 GFP_KERNEL, &mrioc->reply_free_q_dma);
3312 if (!mrioc->reply_free_q)
3313 goto out_failed;
3314
3315 /* sense buffer pool, 4 byte align */
3316 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3317 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3318 &mrioc->pdev->dev, sz, 4, 0);
3319 if (!mrioc->sense_buf_pool) {
3320 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3321 goto out_failed;
3322 }
3323 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3324 &mrioc->sense_buf_dma);
3325 if (!mrioc->sense_buf)
3326 goto out_failed;
3327
3328 /* sense buffer queue, 8 byte align */
3329 sz = mrioc->sense_buf_q_sz * 8;
3330 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3331 &mrioc->pdev->dev, sz, 8, 0);
3332 if (!mrioc->sense_buf_q_pool) {
3333 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3334 goto out_failed;
3335 }
3336 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3337 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3338 if (!mrioc->sense_buf_q)
3339 goto out_failed;
3340
3341 return retval;
3342
3343 out_failed:
3344 retval = -1;
3345 return retval;
3346 }
3347
3348 /**
3349 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3350 * buffers
3351 * @mrioc: Adapter instance reference
3352 *
3353 * Helper function to initialize reply and sense buffers along
3354 * with some debug prints.
3355 *
3356 * Return: None.
3357 */
mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc * mrioc)3358 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3359 {
3360 u32 sz, i;
3361 dma_addr_t phy_addr;
3362
3363 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3364 ioc_info(mrioc,
3365 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3366 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3367 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3368 sz = mrioc->reply_free_qsz * 8;
3369 ioc_info(mrioc,
3370 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3371 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3372 (unsigned long long)mrioc->reply_free_q_dma);
3373 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3374 ioc_info(mrioc,
3375 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3376 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3377 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3378 sz = mrioc->sense_buf_q_sz * 8;
3379 ioc_info(mrioc,
3380 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3381 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3382 (unsigned long long)mrioc->sense_buf_q_dma);
3383
3384 /* initialize Reply buffer Queue */
3385 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3386 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3387 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3388 mrioc->reply_free_q[i] = cpu_to_le64(0);
3389
3390 /* initialize Sense Buffer Queue */
3391 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3392 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3393 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3394 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3395 }
3396
3397 /**
3398 * mpi3mr_issue_iocinit - Send IOC Init
3399 * @mrioc: Adapter instance reference
3400 *
3401 * Issue IOC Init MPI request through admin queue and wait for
3402 * the completion of it or time out.
3403 *
3404 * Return: 0 on success, non-zero on failures.
3405 */
mpi3mr_issue_iocinit(struct mpi3mr_ioc * mrioc)3406 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3407 {
3408 struct mpi3_ioc_init_request iocinit_req;
3409 struct mpi3_driver_info_layout *drv_info;
3410 dma_addr_t data_dma;
3411 u32 data_len = sizeof(*drv_info);
3412 int retval = 0;
3413 ktime_t current_time;
3414
3415 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3416 GFP_KERNEL);
3417 if (!drv_info) {
3418 retval = -1;
3419 goto out;
3420 }
3421 mpimr_initialize_reply_sbuf_queues(mrioc);
3422
3423 drv_info->information_length = cpu_to_le32(data_len);
3424 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3425 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3426 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3427 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3428 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3429 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3430 sizeof(drv_info->driver_release_date));
3431 drv_info->driver_capabilities = 0;
3432 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3433 sizeof(mrioc->driver_info));
3434
3435 memset(&iocinit_req, 0, sizeof(iocinit_req));
3436 mutex_lock(&mrioc->init_cmds.mutex);
3437 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3438 retval = -1;
3439 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3440 mutex_unlock(&mrioc->init_cmds.mutex);
3441 goto out;
3442 }
3443 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3444 mrioc->init_cmds.is_waiting = 1;
3445 mrioc->init_cmds.callback = NULL;
3446 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3447 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3448 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3449 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3450 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3451 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3452 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3453 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3454 iocinit_req.reply_free_queue_address =
3455 cpu_to_le64(mrioc->reply_free_q_dma);
3456 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3457 iocinit_req.sense_buffer_free_queue_depth =
3458 cpu_to_le16(mrioc->sense_buf_q_sz);
3459 iocinit_req.sense_buffer_free_queue_address =
3460 cpu_to_le64(mrioc->sense_buf_q_dma);
3461 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3462
3463 current_time = ktime_get_real();
3464 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3465
3466 iocinit_req.msg_flags |=
3467 MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED;
3468 iocinit_req.msg_flags |=
3469 MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED;
3470
3471 init_completion(&mrioc->init_cmds.done);
3472 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3473 sizeof(iocinit_req), 1);
3474 if (retval) {
3475 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3476 goto out_unlock;
3477 }
3478 wait_for_completion_timeout(&mrioc->init_cmds.done,
3479 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3480 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3481 mpi3mr_check_rh_fault_ioc(mrioc,
3482 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3483 ioc_err(mrioc, "ioc_init timed out\n");
3484 retval = -1;
3485 goto out_unlock;
3486 }
3487 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3488 != MPI3_IOCSTATUS_SUCCESS) {
3489 ioc_err(mrioc,
3490 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3491 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3492 mrioc->init_cmds.ioc_loginfo);
3493 retval = -1;
3494 goto out_unlock;
3495 }
3496
3497 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3498 writel(mrioc->reply_free_queue_host_index,
3499 &mrioc->sysif_regs->reply_free_host_index);
3500
3501 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3502 writel(mrioc->sbq_host_index,
3503 &mrioc->sysif_regs->sense_buffer_free_host_index);
3504 out_unlock:
3505 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3506 mutex_unlock(&mrioc->init_cmds.mutex);
3507
3508 out:
3509 if (drv_info)
3510 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3511 data_dma);
3512
3513 return retval;
3514 }
3515
3516 /**
3517 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3518 * @mrioc: Adapter instance reference
3519 * @event: MPI event ID
3520 *
3521 * Un mask the specific event by resetting the event_mask
3522 * bitmap.
3523 *
3524 * Return: 0 on success, non-zero on failures.
3525 */
mpi3mr_unmask_events(struct mpi3mr_ioc * mrioc,u16 event)3526 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3527 {
3528 u32 desired_event;
3529 u8 word;
3530
3531 if (event >= 128)
3532 return;
3533
3534 desired_event = (1 << (event % 32));
3535 word = event / 32;
3536
3537 mrioc->event_masks[word] &= ~desired_event;
3538 }
3539
3540 /**
3541 * mpi3mr_issue_event_notification - Send event notification
3542 * @mrioc: Adapter instance reference
3543 *
3544 * Issue event notification MPI request through admin queue and
3545 * wait for the completion of it or time out.
3546 *
3547 * Return: 0 on success, non-zero on failures.
3548 */
mpi3mr_issue_event_notification(struct mpi3mr_ioc * mrioc)3549 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3550 {
3551 struct mpi3_event_notification_request evtnotify_req;
3552 int retval = 0;
3553 u8 i;
3554
3555 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3556 mutex_lock(&mrioc->init_cmds.mutex);
3557 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3558 retval = -1;
3559 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3560 mutex_unlock(&mrioc->init_cmds.mutex);
3561 goto out;
3562 }
3563 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3564 mrioc->init_cmds.is_waiting = 1;
3565 mrioc->init_cmds.callback = NULL;
3566 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3567 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3568 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3569 evtnotify_req.event_masks[i] =
3570 cpu_to_le32(mrioc->event_masks[i]);
3571 init_completion(&mrioc->init_cmds.done);
3572 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3573 sizeof(evtnotify_req), 1);
3574 if (retval) {
3575 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3576 goto out_unlock;
3577 }
3578 wait_for_completion_timeout(&mrioc->init_cmds.done,
3579 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3580 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3581 ioc_err(mrioc, "event notification timed out\n");
3582 mpi3mr_check_rh_fault_ioc(mrioc,
3583 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3584 retval = -1;
3585 goto out_unlock;
3586 }
3587 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3588 != MPI3_IOCSTATUS_SUCCESS) {
3589 ioc_err(mrioc,
3590 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3591 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3592 mrioc->init_cmds.ioc_loginfo);
3593 retval = -1;
3594 goto out_unlock;
3595 }
3596
3597 out_unlock:
3598 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3599 mutex_unlock(&mrioc->init_cmds.mutex);
3600 out:
3601 return retval;
3602 }
3603
3604 /**
3605 * mpi3mr_process_event_ack - Process event acknowledgment
3606 * @mrioc: Adapter instance reference
3607 * @event: MPI3 event ID
3608 * @event_ctx: event context
3609 *
3610 * Send event acknowledgment through admin queue and wait for
3611 * it to complete.
3612 *
3613 * Return: 0 on success, non-zero on failures.
3614 */
mpi3mr_process_event_ack(struct mpi3mr_ioc * mrioc,u8 event,u32 event_ctx)3615 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3616 u32 event_ctx)
3617 {
3618 struct mpi3_event_ack_request evtack_req;
3619 int retval = 0;
3620
3621 memset(&evtack_req, 0, sizeof(evtack_req));
3622 mutex_lock(&mrioc->init_cmds.mutex);
3623 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3624 retval = -1;
3625 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3626 mutex_unlock(&mrioc->init_cmds.mutex);
3627 goto out;
3628 }
3629 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3630 mrioc->init_cmds.is_waiting = 1;
3631 mrioc->init_cmds.callback = NULL;
3632 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3633 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3634 evtack_req.event = event;
3635 evtack_req.event_context = cpu_to_le32(event_ctx);
3636
3637 init_completion(&mrioc->init_cmds.done);
3638 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3639 sizeof(evtack_req), 1);
3640 if (retval) {
3641 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3642 goto out_unlock;
3643 }
3644 wait_for_completion_timeout(&mrioc->init_cmds.done,
3645 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3646 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3647 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3648 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3649 mpi3mr_check_rh_fault_ioc(mrioc,
3650 MPI3MR_RESET_FROM_EVTACK_TIMEOUT);
3651 retval = -1;
3652 goto out_unlock;
3653 }
3654 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3655 != MPI3_IOCSTATUS_SUCCESS) {
3656 ioc_err(mrioc,
3657 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3658 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3659 mrioc->init_cmds.ioc_loginfo);
3660 retval = -1;
3661 goto out_unlock;
3662 }
3663
3664 out_unlock:
3665 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3666 mutex_unlock(&mrioc->init_cmds.mutex);
3667 out:
3668 return retval;
3669 }
3670
3671 /**
3672 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3673 * @mrioc: Adapter instance reference
3674 *
3675 * Allocate chain buffers and set a bitmap to indicate free
3676 * chain buffers. Chain buffers are used to pass the SGE
3677 * information along with MPI3 SCSI IO requests for host I/O.
3678 *
3679 * Return: 0 on success, non-zero on failure
3680 */
mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc * mrioc)3681 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3682 {
3683 int retval = 0;
3684 u32 sz, i;
3685 u16 num_chains;
3686
3687 if (mrioc->chain_sgl_list)
3688 return retval;
3689
3690 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3691
3692 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3693 | SHOST_DIX_TYPE1_PROTECTION
3694 | SHOST_DIX_TYPE2_PROTECTION
3695 | SHOST_DIX_TYPE3_PROTECTION))
3696 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3697
3698 mrioc->chain_buf_count = num_chains;
3699 sz = sizeof(struct chain_element) * num_chains;
3700 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3701 if (!mrioc->chain_sgl_list)
3702 goto out_failed;
3703
3704 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length /
3705 MPI3MR_PAGE_SIZE_4K))
3706 mrioc->max_sgl_entries = mrioc->facts.max_data_length /
3707 MPI3MR_PAGE_SIZE_4K;
3708 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common);
3709 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n",
3710 mrioc->max_sgl_entries, sz/1024);
3711
3712 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3713 &mrioc->pdev->dev, sz, 16, 0);
3714 if (!mrioc->chain_buf_pool) {
3715 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3716 goto out_failed;
3717 }
3718
3719 for (i = 0; i < num_chains; i++) {
3720 mrioc->chain_sgl_list[i].addr =
3721 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3722 &mrioc->chain_sgl_list[i].dma_addr);
3723
3724 if (!mrioc->chain_sgl_list[i].addr)
3725 goto out_failed;
3726 }
3727 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3728 if (!mrioc->chain_bitmap)
3729 goto out_failed;
3730 return retval;
3731 out_failed:
3732 retval = -1;
3733 return retval;
3734 }
3735
3736 /**
3737 * mpi3mr_port_enable_complete - Mark port enable complete
3738 * @mrioc: Adapter instance reference
3739 * @drv_cmd: Internal command tracker
3740 *
3741 * Call back for asynchronous port enable request sets the
3742 * driver command to indicate port enable request is complete.
3743 *
3744 * Return: Nothing
3745 */
mpi3mr_port_enable_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)3746 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3747 struct mpi3mr_drv_cmd *drv_cmd)
3748 {
3749 drv_cmd->callback = NULL;
3750 mrioc->scan_started = 0;
3751 if (drv_cmd->state & MPI3MR_CMD_RESET)
3752 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3753 else
3754 mrioc->scan_failed = drv_cmd->ioc_status;
3755 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3756 }
3757
3758 /**
3759 * mpi3mr_issue_port_enable - Issue Port Enable
3760 * @mrioc: Adapter instance reference
3761 * @async: Flag to wait for completion or not
3762 *
3763 * Issue Port Enable MPI request through admin queue and if the
3764 * async flag is not set wait for the completion of the port
3765 * enable or time out.
3766 *
3767 * Return: 0 on success, non-zero on failures.
3768 */
mpi3mr_issue_port_enable(struct mpi3mr_ioc * mrioc,u8 async)3769 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3770 {
3771 struct mpi3_port_enable_request pe_req;
3772 int retval = 0;
3773 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3774
3775 memset(&pe_req, 0, sizeof(pe_req));
3776 mutex_lock(&mrioc->init_cmds.mutex);
3777 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3778 retval = -1;
3779 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3780 mutex_unlock(&mrioc->init_cmds.mutex);
3781 goto out;
3782 }
3783 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3784 if (async) {
3785 mrioc->init_cmds.is_waiting = 0;
3786 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3787 } else {
3788 mrioc->init_cmds.is_waiting = 1;
3789 mrioc->init_cmds.callback = NULL;
3790 init_completion(&mrioc->init_cmds.done);
3791 }
3792 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3793 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3794
3795 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3796 if (retval) {
3797 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3798 goto out_unlock;
3799 }
3800 if (async) {
3801 mutex_unlock(&mrioc->init_cmds.mutex);
3802 goto out;
3803 }
3804
3805 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3806 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3807 ioc_err(mrioc, "port enable timed out\n");
3808 retval = -1;
3809 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3810 goto out_unlock;
3811 }
3812 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3813
3814 out_unlock:
3815 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3816 mutex_unlock(&mrioc->init_cmds.mutex);
3817 out:
3818 return retval;
3819 }
3820
3821 /* Protocol type to name mapper structure */
3822 static const struct {
3823 u8 protocol;
3824 char *name;
3825 } mpi3mr_protocols[] = {
3826 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3827 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3828 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3829 };
3830
3831 /* Capability to name mapper structure*/
3832 static const struct {
3833 u32 capability;
3834 char *name;
3835 } mpi3mr_capabilities[] = {
3836 { MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" },
3837 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" },
3838 };
3839
3840 /**
3841 * mpi3mr_repost_diag_bufs - repost host diag buffers
3842 * @mrioc: Adapter instance reference
3843 *
3844 * repost firmware and trace diag buffers based on global
3845 * trigger flag from driver page 2
3846 *
3847 * Return: 0 on success, non-zero on failures.
3848 */
mpi3mr_repost_diag_bufs(struct mpi3mr_ioc * mrioc)3849 static int mpi3mr_repost_diag_bufs(struct mpi3mr_ioc *mrioc)
3850 {
3851 u64 global_trigger;
3852 union mpi3mr_trigger_data prev_trigger_data;
3853 struct diag_buffer_desc *trace_hdb = NULL;
3854 struct diag_buffer_desc *fw_hdb = NULL;
3855 int retval = 0;
3856 bool trace_repost_needed = false;
3857 bool fw_repost_needed = false;
3858 u8 prev_trigger_type;
3859
3860 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
3861 if (retval)
3862 return -1;
3863
3864 trace_hdb = mpi3mr_diag_buffer_for_type(mrioc,
3865 MPI3_DIAG_BUFFER_TYPE_TRACE);
3866
3867 if (trace_hdb &&
3868 trace_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3869 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3870 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3871 trace_repost_needed = true;
3872
3873 fw_hdb = mpi3mr_diag_buffer_for_type(mrioc, MPI3_DIAG_BUFFER_TYPE_FW);
3874
3875 if (fw_hdb && fw_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3876 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3877 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3878 fw_repost_needed = true;
3879
3880 if (trace_repost_needed || fw_repost_needed) {
3881 global_trigger = le64_to_cpu(mrioc->driver_pg2->global_trigger);
3882 if (global_trigger &
3883 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED)
3884 trace_repost_needed = false;
3885 if (global_trigger &
3886 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED)
3887 fw_repost_needed = false;
3888 }
3889
3890 if (trace_repost_needed) {
3891 prev_trigger_type = trace_hdb->trigger_type;
3892 memcpy(&prev_trigger_data, &trace_hdb->trigger_data,
3893 sizeof(trace_hdb->trigger_data));
3894 retval = mpi3mr_issue_diag_buf_post(mrioc, trace_hdb);
3895 if (!retval) {
3896 dprint_init(mrioc, "trace diag buffer reposted");
3897 mpi3mr_set_trigger_data_in_hdb(trace_hdb,
3898 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3899 } else {
3900 trace_hdb->trigger_type = prev_trigger_type;
3901 memcpy(&trace_hdb->trigger_data, &prev_trigger_data,
3902 sizeof(prev_trigger_data));
3903 ioc_err(mrioc, "trace diag buffer repost failed");
3904 return -1;
3905 }
3906 }
3907
3908 if (fw_repost_needed) {
3909 prev_trigger_type = fw_hdb->trigger_type;
3910 memcpy(&prev_trigger_data, &fw_hdb->trigger_data,
3911 sizeof(fw_hdb->trigger_data));
3912 retval = mpi3mr_issue_diag_buf_post(mrioc, fw_hdb);
3913 if (!retval) {
3914 dprint_init(mrioc, "firmware diag buffer reposted");
3915 mpi3mr_set_trigger_data_in_hdb(fw_hdb,
3916 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3917 } else {
3918 fw_hdb->trigger_type = prev_trigger_type;
3919 memcpy(&fw_hdb->trigger_data, &prev_trigger_data,
3920 sizeof(prev_trigger_data));
3921 ioc_err(mrioc, "firmware diag buffer repost failed");
3922 return -1;
3923 }
3924 }
3925 return retval;
3926 }
3927
3928 /**
3929 * mpi3mr_read_tsu_interval - Update time stamp interval
3930 * @mrioc: Adapter instance reference
3931 *
3932 * Update time stamp interval if its defined in driver page 1,
3933 * otherwise use default value.
3934 *
3935 * Return: Nothing
3936 */
3937 static void
mpi3mr_read_tsu_interval(struct mpi3mr_ioc * mrioc)3938 mpi3mr_read_tsu_interval(struct mpi3mr_ioc *mrioc)
3939 {
3940 struct mpi3_driver_page1 driver_pg1;
3941 u16 pg_sz = sizeof(driver_pg1);
3942 int retval = 0;
3943
3944 mrioc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL;
3945
3946 retval = mpi3mr_cfg_get_driver_pg1(mrioc, &driver_pg1, pg_sz);
3947 if (!retval && driver_pg1.time_stamp_update)
3948 mrioc->ts_update_interval = (driver_pg1.time_stamp_update * 60);
3949 }
3950
3951 /**
3952 * mpi3mr_print_ioc_info - Display controller information
3953 * @mrioc: Adapter instance reference
3954 *
3955 * Display controller personality, capability, supported
3956 * protocols etc.
3957 *
3958 * Return: Nothing
3959 */
3960 static void
mpi3mr_print_ioc_info(struct mpi3mr_ioc * mrioc)3961 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3962 {
3963 int i = 0, bytes_written = 0;
3964 const char *personality;
3965 char protocol[50] = {0};
3966 char capabilities[100] = {0};
3967 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3968
3969 switch (mrioc->facts.personality) {
3970 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3971 personality = "Enhanced HBA";
3972 break;
3973 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3974 personality = "RAID";
3975 break;
3976 default:
3977 personality = "Unknown";
3978 break;
3979 }
3980
3981 ioc_info(mrioc, "Running in %s Personality", personality);
3982
3983 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3984 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3985 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3986
3987 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3988 if (mrioc->facts.protocol_flags &
3989 mpi3mr_protocols[i].protocol) {
3990 bytes_written += scnprintf(protocol + bytes_written,
3991 sizeof(protocol) - bytes_written, "%s%s",
3992 bytes_written ? "," : "",
3993 mpi3mr_protocols[i].name);
3994 }
3995 }
3996
3997 bytes_written = 0;
3998 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3999 if (mrioc->facts.protocol_flags &
4000 mpi3mr_capabilities[i].capability) {
4001 bytes_written += scnprintf(capabilities + bytes_written,
4002 sizeof(capabilities) - bytes_written, "%s%s",
4003 bytes_written ? "," : "",
4004 mpi3mr_capabilities[i].name);
4005 }
4006 }
4007
4008 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
4009 protocol, capabilities);
4010 }
4011
4012 /**
4013 * mpi3mr_cleanup_resources - Free PCI resources
4014 * @mrioc: Adapter instance reference
4015 *
4016 * Unmap PCI device memory and disable PCI device.
4017 *
4018 * Return: 0 on success and non-zero on failure.
4019 */
mpi3mr_cleanup_resources(struct mpi3mr_ioc * mrioc)4020 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
4021 {
4022 struct pci_dev *pdev = mrioc->pdev;
4023
4024 mpi3mr_cleanup_isr(mrioc);
4025
4026 if (mrioc->sysif_regs) {
4027 iounmap((void __iomem *)mrioc->sysif_regs);
4028 mrioc->sysif_regs = NULL;
4029 }
4030
4031 if (pci_is_enabled(pdev)) {
4032 if (mrioc->bars)
4033 pci_release_selected_regions(pdev, mrioc->bars);
4034 pci_disable_device(pdev);
4035 }
4036 }
4037
4038 /**
4039 * mpi3mr_setup_resources - Enable PCI resources
4040 * @mrioc: Adapter instance reference
4041 *
4042 * Enable PCI device memory, MSI-x registers and set DMA mask.
4043 *
4044 * Return: 0 on success and non-zero on failure.
4045 */
mpi3mr_setup_resources(struct mpi3mr_ioc * mrioc)4046 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
4047 {
4048 struct pci_dev *pdev = mrioc->pdev;
4049 u32 memap_sz = 0;
4050 int i, retval = 0, capb = 0;
4051 u16 message_control;
4052 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
4053 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
4054
4055 if (pci_enable_device_mem(pdev)) {
4056 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
4057 retval = -ENODEV;
4058 goto out_failed;
4059 }
4060
4061 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
4062 if (!capb) {
4063 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
4064 retval = -ENODEV;
4065 goto out_failed;
4066 }
4067 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
4068
4069 if (pci_request_selected_regions(pdev, mrioc->bars,
4070 mrioc->driver_name)) {
4071 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
4072 retval = -ENODEV;
4073 goto out_failed;
4074 }
4075
4076 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
4077 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4078 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
4079 memap_sz = pci_resource_len(pdev, i);
4080 mrioc->sysif_regs =
4081 ioremap(mrioc->sysif_regs_phys, memap_sz);
4082 break;
4083 }
4084 }
4085
4086 pci_set_master(pdev);
4087
4088 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
4089 if (retval) {
4090 if (dma_mask != DMA_BIT_MASK(32)) {
4091 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
4092 dma_mask = DMA_BIT_MASK(32);
4093 retval = dma_set_mask_and_coherent(&pdev->dev,
4094 dma_mask);
4095 }
4096 if (retval) {
4097 mrioc->dma_mask = 0;
4098 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
4099 goto out_failed;
4100 }
4101 }
4102 mrioc->dma_mask = dma_mask;
4103
4104 if (!mrioc->sysif_regs) {
4105 ioc_err(mrioc,
4106 "Unable to map adapter memory or resource not found\n");
4107 retval = -EINVAL;
4108 goto out_failed;
4109 }
4110
4111 pci_read_config_word(pdev, capb + 2, &message_control);
4112 mrioc->msix_count = (message_control & 0x3FF) + 1;
4113
4114 pci_save_state(pdev);
4115
4116 pci_set_drvdata(pdev, mrioc->shost);
4117
4118 mpi3mr_ioc_disable_intr(mrioc);
4119
4120 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
4121 (unsigned long long)mrioc->sysif_regs_phys,
4122 mrioc->sysif_regs, memap_sz);
4123 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
4124 mrioc->msix_count);
4125
4126 if (!reset_devices && poll_queues > 0)
4127 mrioc->requested_poll_qcount = min_t(int, poll_queues,
4128 mrioc->msix_count - 2);
4129 return retval;
4130
4131 out_failed:
4132 mpi3mr_cleanup_resources(mrioc);
4133 return retval;
4134 }
4135
4136 /**
4137 * mpi3mr_enable_events - Enable required events
4138 * @mrioc: Adapter instance reference
4139 *
4140 * This routine unmasks the events required by the driver by
4141 * sennding appropriate event mask bitmapt through an event
4142 * notification request.
4143 *
4144 * Return: 0 on success and non-zero on failure.
4145 */
mpi3mr_enable_events(struct mpi3mr_ioc * mrioc)4146 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
4147 {
4148 int retval = 0;
4149 u32 i;
4150
4151 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4152 mrioc->event_masks[i] = -1;
4153
4154 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
4155 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
4156 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
4157 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
4158 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
4159 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4160 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
4161 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
4162 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
4163 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
4164 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
4165 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
4166 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
4167 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
4168 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE);
4169
4170 retval = mpi3mr_issue_event_notification(mrioc);
4171 if (retval)
4172 ioc_err(mrioc, "failed to issue event notification %d\n",
4173 retval);
4174 return retval;
4175 }
4176
4177 /**
4178 * mpi3mr_init_ioc - Initialize the controller
4179 * @mrioc: Adapter instance reference
4180 *
4181 * This the controller initialization routine, executed either
4182 * after soft reset or from pci probe callback.
4183 * Setup the required resources, memory map the controller
4184 * registers, create admin and operational reply queue pairs,
4185 * allocate required memory for reply pool, sense buffer pool,
4186 * issue IOC init request to the firmware, unmask the events and
4187 * issue port enable to discover SAS/SATA/NVMe devies and RAID
4188 * volumes.
4189 *
4190 * Return: 0 on success and non-zero on failure.
4191 */
mpi3mr_init_ioc(struct mpi3mr_ioc * mrioc)4192 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
4193 {
4194 int retval = 0;
4195 u8 retry = 0;
4196 struct mpi3_ioc_facts_data facts_data;
4197 u32 sz;
4198
4199 retry_init:
4200 retval = mpi3mr_bring_ioc_ready(mrioc);
4201 if (retval) {
4202 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
4203 retval);
4204 goto out_failed_noretry;
4205 }
4206
4207 retval = mpi3mr_setup_isr(mrioc, 1);
4208 if (retval) {
4209 ioc_err(mrioc, "Failed to setup ISR error %d\n",
4210 retval);
4211 goto out_failed_noretry;
4212 }
4213
4214 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4215 if (retval) {
4216 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
4217 retval);
4218 goto out_failed;
4219 }
4220
4221 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
4222 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512;
4223 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
4224 atomic_set(&mrioc->pend_large_data_sz, 0);
4225
4226 if (reset_devices)
4227 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
4228 MPI3MR_HOST_IOS_KDUMP);
4229
4230 if (!(mrioc->facts.ioc_capabilities &
4231 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) {
4232 mrioc->sas_transport_enabled = 1;
4233 mrioc->scsi_device_channel = 1;
4234 mrioc->shost->max_channel = 1;
4235 mrioc->shost->transportt = mpi3mr_transport_template;
4236 }
4237
4238 if (mrioc->facts.max_req_limit)
4239 mrioc->prevent_reply_qfull = true;
4240
4241 mrioc->reply_sz = mrioc->facts.reply_sz;
4242
4243 retval = mpi3mr_check_reset_dma_mask(mrioc);
4244 if (retval) {
4245 ioc_err(mrioc, "Resetting dma mask failed %d\n",
4246 retval);
4247 goto out_failed_noretry;
4248 }
4249
4250 mpi3mr_read_tsu_interval(mrioc);
4251 mpi3mr_print_ioc_info(mrioc);
4252
4253 dprint_init(mrioc, "allocating host diag buffers\n");
4254 mpi3mr_alloc_diag_bufs(mrioc);
4255
4256 dprint_init(mrioc, "allocating ioctl dma buffers\n");
4257 mpi3mr_alloc_ioctl_dma_memory(mrioc);
4258
4259 dprint_init(mrioc, "posting host diag buffers\n");
4260 retval = mpi3mr_post_diag_bufs(mrioc);
4261
4262 if (retval)
4263 ioc_warn(mrioc, "failed to post host diag buffers\n");
4264
4265 if (!mrioc->init_cmds.reply) {
4266 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
4267 if (retval) {
4268 ioc_err(mrioc,
4269 "%s :Failed to allocated reply sense buffers %d\n",
4270 __func__, retval);
4271 goto out_failed_noretry;
4272 }
4273 }
4274
4275 if (!mrioc->chain_sgl_list) {
4276 retval = mpi3mr_alloc_chain_bufs(mrioc);
4277 if (retval) {
4278 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
4279 retval);
4280 goto out_failed_noretry;
4281 }
4282 }
4283
4284 retval = mpi3mr_issue_iocinit(mrioc);
4285 if (retval) {
4286 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
4287 retval);
4288 goto out_failed;
4289 }
4290
4291 retval = mpi3mr_print_pkg_ver(mrioc);
4292 if (retval) {
4293 ioc_err(mrioc, "failed to get package version\n");
4294 goto out_failed;
4295 }
4296
4297 retval = mpi3mr_setup_isr(mrioc, 0);
4298 if (retval) {
4299 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
4300 retval);
4301 goto out_failed_noretry;
4302 }
4303
4304 retval = mpi3mr_create_op_queues(mrioc);
4305 if (retval) {
4306 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
4307 retval);
4308 goto out_failed;
4309 }
4310
4311 if (!mrioc->pel_seqnum_virt) {
4312 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
4313 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4314 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4315 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4316 GFP_KERNEL);
4317 if (!mrioc->pel_seqnum_virt) {
4318 retval = -ENOMEM;
4319 goto out_failed_noretry;
4320 }
4321 }
4322
4323 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
4324 dprint_init(mrioc, "allocating memory for throttle groups\n");
4325 sz = sizeof(struct mpi3mr_throttle_group_info);
4326 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
4327 if (!mrioc->throttle_groups) {
4328 retval = -1;
4329 goto out_failed_noretry;
4330 }
4331 }
4332
4333 retval = mpi3mr_enable_events(mrioc);
4334 if (retval) {
4335 ioc_err(mrioc, "failed to enable events %d\n",
4336 retval);
4337 goto out_failed;
4338 }
4339
4340 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
4341 if (retval) {
4342 ioc_err(mrioc, "failed to refresh triggers\n");
4343 goto out_failed;
4344 }
4345
4346 ioc_info(mrioc, "controller initialization completed successfully\n");
4347 return retval;
4348 out_failed:
4349 if (retry < 2) {
4350 retry++;
4351 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
4352 retry);
4353 mpi3mr_memset_buffers(mrioc);
4354 goto retry_init;
4355 }
4356 retval = -1;
4357 out_failed_noretry:
4358 ioc_err(mrioc, "controller initialization failed\n");
4359 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4360 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4361 mrioc->unrecoverable = 1;
4362 return retval;
4363 }
4364
4365 /**
4366 * mpi3mr_reinit_ioc - Re-Initialize the controller
4367 * @mrioc: Adapter instance reference
4368 * @is_resume: Called from resume or reset path
4369 *
4370 * This the controller re-initialization routine, executed from
4371 * the soft reset handler or resume callback. Creates
4372 * operational reply queue pairs, allocate required memory for
4373 * reply pool, sense buffer pool, issue IOC init request to the
4374 * firmware, unmask the events and issue port enable to discover
4375 * SAS/SATA/NVMe devices and RAID volumes.
4376 *
4377 * Return: 0 on success and non-zero on failure.
4378 */
mpi3mr_reinit_ioc(struct mpi3mr_ioc * mrioc,u8 is_resume)4379 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
4380 {
4381 int retval = 0;
4382 u8 retry = 0;
4383 struct mpi3_ioc_facts_data facts_data;
4384 u32 pe_timeout, ioc_status;
4385
4386 retry_init:
4387 pe_timeout =
4388 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
4389
4390 dprint_reset(mrioc, "bringing up the controller to ready state\n");
4391 retval = mpi3mr_bring_ioc_ready(mrioc);
4392 if (retval) {
4393 ioc_err(mrioc, "failed to bring to ready state\n");
4394 goto out_failed_noretry;
4395 }
4396
4397 mrioc->io_admin_reset_sync = 0;
4398 if (is_resume || mrioc->block_on_pci_err) {
4399 dprint_reset(mrioc, "setting up single ISR\n");
4400 retval = mpi3mr_setup_isr(mrioc, 1);
4401 if (retval) {
4402 ioc_err(mrioc, "failed to setup ISR\n");
4403 goto out_failed_noretry;
4404 }
4405 } else
4406 mpi3mr_ioc_enable_intr(mrioc);
4407
4408 dprint_reset(mrioc, "getting ioc_facts\n");
4409 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4410 if (retval) {
4411 ioc_err(mrioc, "failed to get ioc_facts\n");
4412 goto out_failed;
4413 }
4414
4415 dprint_reset(mrioc, "validating ioc_facts\n");
4416 retval = mpi3mr_revalidate_factsdata(mrioc);
4417 if (retval) {
4418 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4419 goto out_failed_noretry;
4420 }
4421
4422 mpi3mr_read_tsu_interval(mrioc);
4423 mpi3mr_print_ioc_info(mrioc);
4424
4425 if (is_resume) {
4426 dprint_reset(mrioc, "posting host diag buffers\n");
4427 retval = mpi3mr_post_diag_bufs(mrioc);
4428 if (retval)
4429 ioc_warn(mrioc, "failed to post host diag buffers\n");
4430 } else {
4431 retval = mpi3mr_repost_diag_bufs(mrioc);
4432 if (retval)
4433 ioc_warn(mrioc, "failed to re post host diag buffers\n");
4434 }
4435
4436 dprint_reset(mrioc, "sending ioc_init\n");
4437 retval = mpi3mr_issue_iocinit(mrioc);
4438 if (retval) {
4439 ioc_err(mrioc, "failed to send ioc_init\n");
4440 goto out_failed;
4441 }
4442
4443 dprint_reset(mrioc, "getting package version\n");
4444 retval = mpi3mr_print_pkg_ver(mrioc);
4445 if (retval) {
4446 ioc_err(mrioc, "failed to get package version\n");
4447 goto out_failed;
4448 }
4449
4450 if (is_resume || mrioc->block_on_pci_err) {
4451 dprint_reset(mrioc, "setting up multiple ISR\n");
4452 retval = mpi3mr_setup_isr(mrioc, 0);
4453 if (retval) {
4454 ioc_err(mrioc, "failed to re-setup ISR\n");
4455 goto out_failed_noretry;
4456 }
4457 }
4458
4459 dprint_reset(mrioc, "creating operational queue pairs\n");
4460 retval = mpi3mr_create_op_queues(mrioc);
4461 if (retval) {
4462 ioc_err(mrioc, "failed to create operational queue pairs\n");
4463 goto out_failed;
4464 }
4465
4466 if (!mrioc->pel_seqnum_virt) {
4467 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4468 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4469 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4470 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4471 GFP_KERNEL);
4472 if (!mrioc->pel_seqnum_virt) {
4473 retval = -ENOMEM;
4474 goto out_failed_noretry;
4475 }
4476 }
4477
4478 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4479 ioc_err(mrioc,
4480 "cannot create minimum number of operational queues expected:%d created:%d\n",
4481 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4482 retval = -1;
4483 goto out_failed_noretry;
4484 }
4485
4486 dprint_reset(mrioc, "enabling events\n");
4487 retval = mpi3mr_enable_events(mrioc);
4488 if (retval) {
4489 ioc_err(mrioc, "failed to enable events\n");
4490 goto out_failed;
4491 }
4492
4493 mrioc->device_refresh_on = 1;
4494 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4495
4496 ioc_info(mrioc, "sending port enable\n");
4497 retval = mpi3mr_issue_port_enable(mrioc, 1);
4498 if (retval) {
4499 ioc_err(mrioc, "failed to issue port enable\n");
4500 goto out_failed;
4501 }
4502 do {
4503 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4504 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4505 break;
4506 if (!pci_device_is_present(mrioc->pdev))
4507 mrioc->unrecoverable = 1;
4508 if (mrioc->unrecoverable) {
4509 retval = -1;
4510 goto out_failed_noretry;
4511 }
4512 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4513 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4514 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4515 mpi3mr_print_fault_info(mrioc);
4516 mrioc->init_cmds.is_waiting = 0;
4517 mrioc->init_cmds.callback = NULL;
4518 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4519 goto out_failed;
4520 }
4521 } while (--pe_timeout);
4522
4523 if (!pe_timeout) {
4524 ioc_err(mrioc, "port enable timed out\n");
4525 mpi3mr_check_rh_fault_ioc(mrioc,
4526 MPI3MR_RESET_FROM_PE_TIMEOUT);
4527 mrioc->init_cmds.is_waiting = 0;
4528 mrioc->init_cmds.callback = NULL;
4529 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4530 goto out_failed;
4531 } else if (mrioc->scan_failed) {
4532 ioc_err(mrioc,
4533 "port enable failed with status=0x%04x\n",
4534 mrioc->scan_failed);
4535 } else
4536 ioc_info(mrioc, "port enable completed successfully\n");
4537
4538 ioc_info(mrioc, "controller %s completed successfully\n",
4539 (is_resume)?"resume":"re-initialization");
4540 return retval;
4541 out_failed:
4542 if (retry < 2) {
4543 retry++;
4544 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4545 (is_resume)?"resume":"re-initialization", retry);
4546 mpi3mr_memset_buffers(mrioc);
4547 goto retry_init;
4548 }
4549 retval = -1;
4550 out_failed_noretry:
4551 ioc_err(mrioc, "controller %s is failed\n",
4552 (is_resume)?"resume":"re-initialization");
4553 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4554 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4555 mrioc->unrecoverable = 1;
4556 return retval;
4557 }
4558
4559 /**
4560 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4561 * segments
4562 * @mrioc: Adapter instance reference
4563 * @qidx: Operational reply queue index
4564 *
4565 * Return: Nothing.
4566 */
mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4567 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4568 {
4569 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4570 struct segments *segments;
4571 int i, size;
4572
4573 if (!op_reply_q->q_segments)
4574 return;
4575
4576 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4577 segments = op_reply_q->q_segments;
4578 for (i = 0; i < op_reply_q->num_segments; i++)
4579 memset(segments[i].segment, 0, size);
4580 }
4581
4582 /**
4583 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4584 * segments
4585 * @mrioc: Adapter instance reference
4586 * @qidx: Operational request queue index
4587 *
4588 * Return: Nothing.
4589 */
mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4590 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4591 {
4592 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4593 struct segments *segments;
4594 int i, size;
4595
4596 if (!op_req_q->q_segments)
4597 return;
4598
4599 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4600 segments = op_req_q->q_segments;
4601 for (i = 0; i < op_req_q->num_segments; i++)
4602 memset(segments[i].segment, 0, size);
4603 }
4604
4605 /**
4606 * mpi3mr_memset_buffers - memset memory for a controller
4607 * @mrioc: Adapter instance reference
4608 *
4609 * clear all the memory allocated for a controller, typically
4610 * called post reset to reuse the memory allocated during the
4611 * controller init.
4612 *
4613 * Return: Nothing.
4614 */
mpi3mr_memset_buffers(struct mpi3mr_ioc * mrioc)4615 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4616 {
4617 u16 i;
4618 struct mpi3mr_throttle_group_info *tg;
4619
4620 mrioc->change_count = 0;
4621 mrioc->active_poll_qcount = 0;
4622 mrioc->default_qcount = 0;
4623 if (mrioc->admin_req_base)
4624 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4625 if (mrioc->admin_reply_base)
4626 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4627 atomic_set(&mrioc->admin_reply_q_in_use, 0);
4628
4629 if (mrioc->init_cmds.reply) {
4630 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4631 memset(mrioc->bsg_cmds.reply, 0,
4632 sizeof(*mrioc->bsg_cmds.reply));
4633 memset(mrioc->host_tm_cmds.reply, 0,
4634 sizeof(*mrioc->host_tm_cmds.reply));
4635 memset(mrioc->pel_cmds.reply, 0,
4636 sizeof(*mrioc->pel_cmds.reply));
4637 memset(mrioc->pel_abort_cmd.reply, 0,
4638 sizeof(*mrioc->pel_abort_cmd.reply));
4639 memset(mrioc->transport_cmds.reply, 0,
4640 sizeof(*mrioc->transport_cmds.reply));
4641 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4642 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4643 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4644 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4645 memset(mrioc->evtack_cmds[i].reply, 0,
4646 sizeof(*mrioc->evtack_cmds[i].reply));
4647 bitmap_clear(mrioc->removepend_bitmap, 0,
4648 mrioc->dev_handle_bitmap_bits);
4649 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4650 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4651 MPI3MR_NUM_EVTACKCMD);
4652 }
4653
4654 for (i = 0; i < mrioc->num_queues; i++) {
4655 mrioc->op_reply_qinfo[i].qid = 0;
4656 mrioc->op_reply_qinfo[i].ci = 0;
4657 mrioc->op_reply_qinfo[i].num_replies = 0;
4658 mrioc->op_reply_qinfo[i].ephase = 0;
4659 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4660 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4661 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4662
4663 mrioc->req_qinfo[i].ci = 0;
4664 mrioc->req_qinfo[i].pi = 0;
4665 mrioc->req_qinfo[i].num_requests = 0;
4666 mrioc->req_qinfo[i].qid = 0;
4667 mrioc->req_qinfo[i].reply_qid = 0;
4668 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4669 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4670 }
4671
4672 atomic_set(&mrioc->pend_large_data_sz, 0);
4673 if (mrioc->throttle_groups) {
4674 tg = mrioc->throttle_groups;
4675 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4676 tg->id = 0;
4677 tg->fw_qd = 0;
4678 tg->modified_qd = 0;
4679 tg->io_divert = 0;
4680 tg->need_qd_reduction = 0;
4681 tg->high = 0;
4682 tg->low = 0;
4683 tg->qd_reduction = 0;
4684 atomic_set(&tg->pend_large_data_sz, 0);
4685 }
4686 }
4687 }
4688
4689 /**
4690 * mpi3mr_free_mem - Free memory allocated for a controller
4691 * @mrioc: Adapter instance reference
4692 *
4693 * Free all the memory allocated for a controller.
4694 *
4695 * Return: Nothing.
4696 */
mpi3mr_free_mem(struct mpi3mr_ioc * mrioc)4697 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4698 {
4699 u16 i;
4700 struct mpi3mr_intr_info *intr_info;
4701 struct diag_buffer_desc *diag_buffer;
4702
4703 mpi3mr_free_enclosure_list(mrioc);
4704 mpi3mr_free_ioctl_dma_memory(mrioc);
4705
4706 if (mrioc->sense_buf_pool) {
4707 if (mrioc->sense_buf)
4708 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4709 mrioc->sense_buf_dma);
4710 dma_pool_destroy(mrioc->sense_buf_pool);
4711 mrioc->sense_buf = NULL;
4712 mrioc->sense_buf_pool = NULL;
4713 }
4714 if (mrioc->sense_buf_q_pool) {
4715 if (mrioc->sense_buf_q)
4716 dma_pool_free(mrioc->sense_buf_q_pool,
4717 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4718 dma_pool_destroy(mrioc->sense_buf_q_pool);
4719 mrioc->sense_buf_q = NULL;
4720 mrioc->sense_buf_q_pool = NULL;
4721 }
4722
4723 if (mrioc->reply_buf_pool) {
4724 if (mrioc->reply_buf)
4725 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4726 mrioc->reply_buf_dma);
4727 dma_pool_destroy(mrioc->reply_buf_pool);
4728 mrioc->reply_buf = NULL;
4729 mrioc->reply_buf_pool = NULL;
4730 }
4731 if (mrioc->reply_free_q_pool) {
4732 if (mrioc->reply_free_q)
4733 dma_pool_free(mrioc->reply_free_q_pool,
4734 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4735 dma_pool_destroy(mrioc->reply_free_q_pool);
4736 mrioc->reply_free_q = NULL;
4737 mrioc->reply_free_q_pool = NULL;
4738 }
4739
4740 for (i = 0; i < mrioc->num_op_req_q; i++)
4741 mpi3mr_free_op_req_q_segments(mrioc, i);
4742
4743 for (i = 0; i < mrioc->num_op_reply_q; i++)
4744 mpi3mr_free_op_reply_q_segments(mrioc, i);
4745
4746 for (i = 0; i < mrioc->intr_info_count; i++) {
4747 intr_info = mrioc->intr_info + i;
4748 intr_info->op_reply_q = NULL;
4749 }
4750
4751 kfree(mrioc->req_qinfo);
4752 mrioc->req_qinfo = NULL;
4753 mrioc->num_op_req_q = 0;
4754
4755 kfree(mrioc->op_reply_qinfo);
4756 mrioc->op_reply_qinfo = NULL;
4757 mrioc->num_op_reply_q = 0;
4758
4759 kfree(mrioc->init_cmds.reply);
4760 mrioc->init_cmds.reply = NULL;
4761
4762 kfree(mrioc->bsg_cmds.reply);
4763 mrioc->bsg_cmds.reply = NULL;
4764
4765 kfree(mrioc->host_tm_cmds.reply);
4766 mrioc->host_tm_cmds.reply = NULL;
4767
4768 kfree(mrioc->pel_cmds.reply);
4769 mrioc->pel_cmds.reply = NULL;
4770
4771 kfree(mrioc->pel_abort_cmd.reply);
4772 mrioc->pel_abort_cmd.reply = NULL;
4773
4774 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4775 kfree(mrioc->evtack_cmds[i].reply);
4776 mrioc->evtack_cmds[i].reply = NULL;
4777 }
4778
4779 bitmap_free(mrioc->removepend_bitmap);
4780 mrioc->removepend_bitmap = NULL;
4781
4782 bitmap_free(mrioc->devrem_bitmap);
4783 mrioc->devrem_bitmap = NULL;
4784
4785 bitmap_free(mrioc->evtack_cmds_bitmap);
4786 mrioc->evtack_cmds_bitmap = NULL;
4787
4788 bitmap_free(mrioc->chain_bitmap);
4789 mrioc->chain_bitmap = NULL;
4790
4791 kfree(mrioc->transport_cmds.reply);
4792 mrioc->transport_cmds.reply = NULL;
4793
4794 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4795 kfree(mrioc->dev_rmhs_cmds[i].reply);
4796 mrioc->dev_rmhs_cmds[i].reply = NULL;
4797 }
4798
4799 if (mrioc->chain_buf_pool) {
4800 for (i = 0; i < mrioc->chain_buf_count; i++) {
4801 if (mrioc->chain_sgl_list[i].addr) {
4802 dma_pool_free(mrioc->chain_buf_pool,
4803 mrioc->chain_sgl_list[i].addr,
4804 mrioc->chain_sgl_list[i].dma_addr);
4805 mrioc->chain_sgl_list[i].addr = NULL;
4806 }
4807 }
4808 dma_pool_destroy(mrioc->chain_buf_pool);
4809 mrioc->chain_buf_pool = NULL;
4810 }
4811
4812 kfree(mrioc->chain_sgl_list);
4813 mrioc->chain_sgl_list = NULL;
4814
4815 if (mrioc->admin_reply_base) {
4816 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4817 mrioc->admin_reply_base, mrioc->admin_reply_dma);
4818 mrioc->admin_reply_base = NULL;
4819 }
4820 if (mrioc->admin_req_base) {
4821 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4822 mrioc->admin_req_base, mrioc->admin_req_dma);
4823 mrioc->admin_req_base = NULL;
4824 }
4825
4826 if (mrioc->pel_seqnum_virt) {
4827 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4828 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4829 mrioc->pel_seqnum_virt = NULL;
4830 }
4831
4832 for (i = 0; i < MPI3MR_MAX_NUM_HDB; i++) {
4833 diag_buffer = &mrioc->diag_buffers[i];
4834 if (diag_buffer->addr) {
4835 dma_free_coherent(&mrioc->pdev->dev,
4836 diag_buffer->size, diag_buffer->addr,
4837 diag_buffer->dma_addr);
4838 diag_buffer->addr = NULL;
4839 diag_buffer->size = 0;
4840 diag_buffer->type = 0;
4841 diag_buffer->status = 0;
4842 }
4843 }
4844
4845 kfree(mrioc->throttle_groups);
4846 mrioc->throttle_groups = NULL;
4847
4848 kfree(mrioc->logdata_buf);
4849 mrioc->logdata_buf = NULL;
4850
4851 }
4852
4853 /**
4854 * mpi3mr_issue_ioc_shutdown - shutdown controller
4855 * @mrioc: Adapter instance reference
4856 *
4857 * Send shutodwn notification to the controller and wait for the
4858 * shutdown_timeout for it to be completed.
4859 *
4860 * Return: Nothing.
4861 */
mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc * mrioc)4862 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4863 {
4864 u32 ioc_config, ioc_status;
4865 u8 retval = 1;
4866 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4867
4868 ioc_info(mrioc, "Issuing shutdown Notification\n");
4869 if (mrioc->unrecoverable) {
4870 ioc_warn(mrioc,
4871 "IOC is unrecoverable shutdown is not issued\n");
4872 return;
4873 }
4874 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4875 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4876 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4877 ioc_info(mrioc, "shutdown already in progress\n");
4878 return;
4879 }
4880
4881 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4882 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4883 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4884
4885 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4886
4887 if (mrioc->facts.shutdown_timeout)
4888 timeout = mrioc->facts.shutdown_timeout * 10;
4889
4890 do {
4891 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4892 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4893 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4894 retval = 0;
4895 break;
4896 }
4897 msleep(100);
4898 } while (--timeout);
4899
4900 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4901 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4902
4903 if (retval) {
4904 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4905 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4906 ioc_warn(mrioc,
4907 "shutdown still in progress after timeout\n");
4908 }
4909
4910 ioc_info(mrioc,
4911 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4912 (!retval) ? "successful" : "failed", ioc_status,
4913 ioc_config);
4914 }
4915
4916 /**
4917 * mpi3mr_cleanup_ioc - Cleanup controller
4918 * @mrioc: Adapter instance reference
4919 *
4920 * controller cleanup handler, Message unit reset or soft reset
4921 * and shutdown notification is issued to the controller.
4922 *
4923 * Return: Nothing.
4924 */
mpi3mr_cleanup_ioc(struct mpi3mr_ioc * mrioc)4925 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4926 {
4927 enum mpi3mr_iocstate ioc_state;
4928
4929 dprint_exit(mrioc, "cleaning up the controller\n");
4930 mpi3mr_ioc_disable_intr(mrioc);
4931
4932 ioc_state = mpi3mr_get_iocstate(mrioc);
4933
4934 if (!mrioc->unrecoverable && !mrioc->reset_in_progress &&
4935 !mrioc->pci_err_recovery &&
4936 (ioc_state == MRIOC_STATE_READY)) {
4937 if (mpi3mr_issue_and_process_mur(mrioc,
4938 MPI3MR_RESET_FROM_CTLR_CLEANUP))
4939 mpi3mr_issue_reset(mrioc,
4940 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4941 MPI3MR_RESET_FROM_MUR_FAILURE);
4942 mpi3mr_issue_ioc_shutdown(mrioc);
4943 }
4944 dprint_exit(mrioc, "controller cleanup completed\n");
4945 }
4946
4947 /**
4948 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4949 * @mrioc: Adapter instance reference
4950 * @cmdptr: Internal command tracker
4951 *
4952 * Complete an internal driver commands with state indicating it
4953 * is completed due to reset.
4954 *
4955 * Return: Nothing.
4956 */
mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * cmdptr)4957 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4958 struct mpi3mr_drv_cmd *cmdptr)
4959 {
4960 if (cmdptr->state & MPI3MR_CMD_PENDING) {
4961 cmdptr->state |= MPI3MR_CMD_RESET;
4962 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4963 if (cmdptr->is_waiting) {
4964 complete(&cmdptr->done);
4965 cmdptr->is_waiting = 0;
4966 } else if (cmdptr->callback)
4967 cmdptr->callback(mrioc, cmdptr);
4968 }
4969 }
4970
4971 /**
4972 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4973 * @mrioc: Adapter instance reference
4974 *
4975 * Flush all internal driver commands post reset
4976 *
4977 * Return: Nothing.
4978 */
mpi3mr_flush_drv_cmds(struct mpi3mr_ioc * mrioc)4979 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4980 {
4981 struct mpi3mr_drv_cmd *cmdptr;
4982 u8 i;
4983
4984 cmdptr = &mrioc->init_cmds;
4985 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4986
4987 cmdptr = &mrioc->cfg_cmds;
4988 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4989
4990 cmdptr = &mrioc->bsg_cmds;
4991 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4992 cmdptr = &mrioc->host_tm_cmds;
4993 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4994
4995 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4996 cmdptr = &mrioc->dev_rmhs_cmds[i];
4997 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4998 }
4999
5000 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
5001 cmdptr = &mrioc->evtack_cmds[i];
5002 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5003 }
5004
5005 cmdptr = &mrioc->pel_cmds;
5006 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5007
5008 cmdptr = &mrioc->pel_abort_cmd;
5009 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5010
5011 cmdptr = &mrioc->transport_cmds;
5012 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5013 }
5014
5015 /**
5016 * mpi3mr_pel_wait_post - Issue PEL Wait
5017 * @mrioc: Adapter instance reference
5018 * @drv_cmd: Internal command tracker
5019 *
5020 * Issue PEL Wait MPI request through admin queue and return.
5021 *
5022 * Return: Nothing.
5023 */
mpi3mr_pel_wait_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5024 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
5025 struct mpi3mr_drv_cmd *drv_cmd)
5026 {
5027 struct mpi3_pel_req_action_wait pel_wait;
5028
5029 mrioc->pel_abort_requested = false;
5030
5031 memset(&pel_wait, 0, sizeof(pel_wait));
5032 drv_cmd->state = MPI3MR_CMD_PENDING;
5033 drv_cmd->is_waiting = 0;
5034 drv_cmd->callback = mpi3mr_pel_wait_complete;
5035 drv_cmd->ioc_status = 0;
5036 drv_cmd->ioc_loginfo = 0;
5037 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5038 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5039 pel_wait.action = MPI3_PEL_ACTION_WAIT;
5040 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
5041 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
5042 pel_wait.class = cpu_to_le16(mrioc->pel_class);
5043 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
5044 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
5045 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
5046
5047 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
5048 dprint_bsg_err(mrioc,
5049 "Issuing PELWait: Admin post failed\n");
5050 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5051 drv_cmd->callback = NULL;
5052 drv_cmd->retry_count = 0;
5053 mrioc->pel_enabled = false;
5054 }
5055 }
5056
5057 /**
5058 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
5059 * @mrioc: Adapter instance reference
5060 * @drv_cmd: Internal command tracker
5061 *
5062 * Issue PEL get sequence number MPI request through admin queue
5063 * and return.
5064 *
5065 * Return: 0 on success, non-zero on failure.
5066 */
mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5067 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
5068 struct mpi3mr_drv_cmd *drv_cmd)
5069 {
5070 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
5071 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5072 int retval = 0;
5073
5074 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
5075 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
5076 mrioc->pel_cmds.is_waiting = 0;
5077 mrioc->pel_cmds.ioc_status = 0;
5078 mrioc->pel_cmds.ioc_loginfo = 0;
5079 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
5080 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5081 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5082 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
5083 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
5084 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
5085
5086 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
5087 sizeof(pel_getseq_req), 0);
5088 if (retval) {
5089 if (drv_cmd) {
5090 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5091 drv_cmd->callback = NULL;
5092 drv_cmd->retry_count = 0;
5093 }
5094 mrioc->pel_enabled = false;
5095 }
5096
5097 return retval;
5098 }
5099
5100 /**
5101 * mpi3mr_pel_wait_complete - PELWait Completion callback
5102 * @mrioc: Adapter instance reference
5103 * @drv_cmd: Internal command tracker
5104 *
5105 * This is a callback handler for the PELWait request and
5106 * firmware completes a PELWait request when it is aborted or a
5107 * new PEL entry is available. This sends AEN to the application
5108 * and if the PELwait completion is not due to PELAbort then
5109 * this will send a request for new PEL Sequence number
5110 *
5111 * Return: Nothing.
5112 */
mpi3mr_pel_wait_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5113 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
5114 struct mpi3mr_drv_cmd *drv_cmd)
5115 {
5116 struct mpi3_pel_reply *pel_reply = NULL;
5117 u16 ioc_status, pe_log_status;
5118 bool do_retry = false;
5119
5120 if (drv_cmd->state & MPI3MR_CMD_RESET)
5121 goto cleanup_drv_cmd;
5122
5123 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5124 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5125 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
5126 __func__, ioc_status, drv_cmd->ioc_loginfo);
5127 dprint_bsg_err(mrioc,
5128 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5129 ioc_status, drv_cmd->ioc_loginfo);
5130 do_retry = true;
5131 }
5132
5133 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5134 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5135
5136 if (!pel_reply) {
5137 dprint_bsg_err(mrioc,
5138 "pel_wait: failed due to no reply\n");
5139 goto out_failed;
5140 }
5141
5142 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
5143 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
5144 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
5145 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
5146 __func__, pe_log_status);
5147 dprint_bsg_err(mrioc,
5148 "pel_wait: failed due to pel_log_status(0x%04x)\n",
5149 pe_log_status);
5150 do_retry = true;
5151 }
5152
5153 if (do_retry) {
5154 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5155 drv_cmd->retry_count++;
5156 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
5157 drv_cmd->retry_count);
5158 mpi3mr_pel_wait_post(mrioc, drv_cmd);
5159 return;
5160 }
5161 dprint_bsg_err(mrioc,
5162 "pel_wait: failed after all retries(%d)\n",
5163 drv_cmd->retry_count);
5164 goto out_failed;
5165 }
5166 atomic64_inc(&event_counter);
5167 if (!mrioc->pel_abort_requested) {
5168 mrioc->pel_cmds.retry_count = 0;
5169 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
5170 }
5171
5172 return;
5173 out_failed:
5174 mrioc->pel_enabled = false;
5175 cleanup_drv_cmd:
5176 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5177 drv_cmd->callback = NULL;
5178 drv_cmd->retry_count = 0;
5179 }
5180
5181 /**
5182 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
5183 * @mrioc: Adapter instance reference
5184 * @drv_cmd: Internal command tracker
5185 *
5186 * This is a callback handler for the PEL get sequence number
5187 * request and a new PEL wait request will be issued to the
5188 * firmware from this
5189 *
5190 * Return: Nothing.
5191 */
mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5192 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
5193 struct mpi3mr_drv_cmd *drv_cmd)
5194 {
5195 struct mpi3_pel_reply *pel_reply = NULL;
5196 struct mpi3_pel_seq *pel_seqnum_virt;
5197 u16 ioc_status;
5198 bool do_retry = false;
5199
5200 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
5201
5202 if (drv_cmd->state & MPI3MR_CMD_RESET)
5203 goto cleanup_drv_cmd;
5204
5205 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5206 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5207 dprint_bsg_err(mrioc,
5208 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5209 ioc_status, drv_cmd->ioc_loginfo);
5210 do_retry = true;
5211 }
5212
5213 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5214 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5215 if (!pel_reply) {
5216 dprint_bsg_err(mrioc,
5217 "pel_get_seqnum: failed due to no reply\n");
5218 goto out_failed;
5219 }
5220
5221 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
5222 dprint_bsg_err(mrioc,
5223 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
5224 le16_to_cpu(pel_reply->pe_log_status));
5225 do_retry = true;
5226 }
5227
5228 if (do_retry) {
5229 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5230 drv_cmd->retry_count++;
5231 dprint_bsg_err(mrioc,
5232 "pel_get_seqnum: retrying(%d)\n",
5233 drv_cmd->retry_count);
5234 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
5235 return;
5236 }
5237
5238 dprint_bsg_err(mrioc,
5239 "pel_get_seqnum: failed after all retries(%d)\n",
5240 drv_cmd->retry_count);
5241 goto out_failed;
5242 }
5243 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
5244 drv_cmd->retry_count = 0;
5245 mpi3mr_pel_wait_post(mrioc, drv_cmd);
5246
5247 return;
5248 out_failed:
5249 mrioc->pel_enabled = false;
5250 cleanup_drv_cmd:
5251 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5252 drv_cmd->callback = NULL;
5253 drv_cmd->retry_count = 0;
5254 }
5255
5256 /**
5257 * mpi3mr_check_op_admin_proc -
5258 * @mrioc: Adapter instance reference
5259 *
5260 * Check if any of the operation reply queues
5261 * or the admin reply queue are currently in use.
5262 * If any queue is in use, this function waits for
5263 * a maximum of 10 seconds for them to become available.
5264 *
5265 * Return: 0 on success, non-zero on failure.
5266 */
mpi3mr_check_op_admin_proc(struct mpi3mr_ioc * mrioc)5267 static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc)
5268 {
5269
5270 u16 timeout = 10 * 10;
5271 u16 elapsed_time = 0;
5272 bool op_admin_in_use = false;
5273
5274 do {
5275 op_admin_in_use = false;
5276
5277 /* Check admin_reply queue first to exit early */
5278 if (atomic_read(&mrioc->admin_reply_q_in_use) == 1)
5279 op_admin_in_use = true;
5280 else {
5281 /* Check op_reply queues */
5282 int i;
5283
5284 for (i = 0; i < mrioc->num_queues; i++) {
5285 if (atomic_read(&mrioc->op_reply_qinfo[i].in_use) == 1) {
5286 op_admin_in_use = true;
5287 break;
5288 }
5289 }
5290 }
5291
5292 if (!op_admin_in_use)
5293 break;
5294
5295 msleep(100);
5296
5297 } while (++elapsed_time < timeout);
5298
5299 if (op_admin_in_use)
5300 return 1;
5301
5302 return 0;
5303 }
5304
5305 /**
5306 * mpi3mr_soft_reset_handler - Reset the controller
5307 * @mrioc: Adapter instance reference
5308 * @reset_reason: Reset reason code
5309 * @snapdump: Flag to generate snapdump in firmware or not
5310 *
5311 * This is an handler for recovering controller by issuing soft
5312 * reset are diag fault reset. This is a blocking function and
5313 * when one reset is executed if any other resets they will be
5314 * blocked. All BSG requests will be blocked during the reset. If
5315 * controller reset is successful then the controller will be
5316 * reinitalized, otherwise the controller will be marked as not
5317 * recoverable
5318 *
5319 * In snapdump bit is set, the controller is issued with diag
5320 * fault reset so that the firmware can create a snap dump and
5321 * post that the firmware will result in F000 fault and the
5322 * driver will issue soft reset to recover from that.
5323 *
5324 * Return: 0 on success, non-zero on failure.
5325 */
mpi3mr_soft_reset_handler(struct mpi3mr_ioc * mrioc,u16 reset_reason,u8 snapdump)5326 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
5327 u16 reset_reason, u8 snapdump)
5328 {
5329 int retval = 0, i;
5330 unsigned long flags;
5331 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
5332 union mpi3mr_trigger_data trigger_data;
5333
5334 /* Block the reset handler until diag save in progress*/
5335 dprint_reset(mrioc,
5336 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
5337 mrioc->diagsave_timeout);
5338 while (mrioc->diagsave_timeout)
5339 ssleep(1);
5340 /*
5341 * Block new resets until the currently executing one is finished and
5342 * return the status of the existing reset for all blocked resets
5343 */
5344 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
5345 if (!mutex_trylock(&mrioc->reset_mutex)) {
5346 ioc_info(mrioc,
5347 "controller reset triggered by %s is blocked due to another reset in progress\n",
5348 mpi3mr_reset_rc_name(reset_reason));
5349 do {
5350 ssleep(1);
5351 } while (mrioc->reset_in_progress == 1);
5352 ioc_info(mrioc,
5353 "returning previous reset result(%d) for the reset triggered by %s\n",
5354 mrioc->prev_reset_result,
5355 mpi3mr_reset_rc_name(reset_reason));
5356 return mrioc->prev_reset_result;
5357 }
5358 ioc_info(mrioc, "controller reset is triggered by %s\n",
5359 mpi3mr_reset_rc_name(reset_reason));
5360
5361 mrioc->device_refresh_on = 0;
5362 mrioc->reset_in_progress = 1;
5363 mrioc->stop_bsgs = 1;
5364 mrioc->prev_reset_result = -1;
5365 memset(&trigger_data, 0, sizeof(trigger_data));
5366
5367 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
5368 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
5369 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
5370 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5371 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5372 dprint_reset(mrioc,
5373 "soft_reset_handler: releasing host diagnostic buffers\n");
5374 mpi3mr_release_diag_bufs(mrioc, 0);
5375 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5376 mrioc->event_masks[i] = -1;
5377
5378 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
5379 mpi3mr_issue_event_notification(mrioc);
5380 }
5381
5382 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
5383
5384 mpi3mr_ioc_disable_intr(mrioc);
5385 mrioc->io_admin_reset_sync = 1;
5386
5387 if (snapdump) {
5388 mpi3mr_set_diagsave(mrioc);
5389 retval = mpi3mr_issue_reset(mrioc,
5390 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5391 if (!retval) {
5392 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
5393 MPI3_SYSIF_FAULT_CODE_MASK);
5394 do {
5395 host_diagnostic =
5396 readl(&mrioc->sysif_regs->host_diagnostic);
5397 if (!(host_diagnostic &
5398 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
5399 break;
5400 msleep(100);
5401 } while (--timeout);
5402 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5403 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
5404 }
5405 }
5406
5407 retval = mpi3mr_issue_reset(mrioc,
5408 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
5409 if (retval) {
5410 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
5411 goto out;
5412 }
5413
5414 retval = mpi3mr_check_op_admin_proc(mrioc);
5415 if (retval) {
5416 ioc_err(mrioc, "Soft reset failed due to an Admin or I/O queue polling\n"
5417 "thread still processing replies even after a 10 second\n"
5418 "timeout. Marking the controller as unrecoverable!\n");
5419
5420 goto out;
5421 }
5422
5423 if (mrioc->num_io_throttle_group !=
5424 mrioc->facts.max_io_throttle_group) {
5425 ioc_err(mrioc,
5426 "max io throttle group doesn't match old(%d), new(%d)\n",
5427 mrioc->num_io_throttle_group,
5428 mrioc->facts.max_io_throttle_group);
5429 retval = -EPERM;
5430 goto out;
5431 }
5432
5433 mpi3mr_flush_delayed_cmd_lists(mrioc);
5434 mpi3mr_flush_drv_cmds(mrioc);
5435 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
5436 bitmap_clear(mrioc->removepend_bitmap, 0,
5437 mrioc->dev_handle_bitmap_bits);
5438 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
5439 mpi3mr_flush_host_io(mrioc);
5440 mpi3mr_cleanup_fwevt_list(mrioc);
5441 mpi3mr_invalidate_devhandles(mrioc);
5442 mpi3mr_free_enclosure_list(mrioc);
5443
5444 if (mrioc->prepare_for_reset) {
5445 mrioc->prepare_for_reset = 0;
5446 mrioc->prepare_for_reset_timeout_counter = 0;
5447 }
5448 mpi3mr_memset_buffers(mrioc);
5449 mpi3mr_release_diag_bufs(mrioc, 1);
5450 mrioc->fw_release_trigger_active = false;
5451 mrioc->trace_release_trigger_active = false;
5452 mrioc->snapdump_trigger_active = false;
5453 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5454 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5455
5456 dprint_reset(mrioc,
5457 "soft_reset_handler: reinitializing the controller\n");
5458 retval = mpi3mr_reinit_ioc(mrioc, 0);
5459 if (retval) {
5460 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
5461 mrioc->name, reset_reason);
5462 goto out;
5463 }
5464 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
5465
5466 out:
5467 if (!retval) {
5468 mrioc->diagsave_timeout = 0;
5469 mrioc->reset_in_progress = 0;
5470 mrioc->pel_abort_requested = 0;
5471 if (mrioc->pel_enabled) {
5472 mrioc->pel_cmds.retry_count = 0;
5473 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
5474 }
5475
5476 mrioc->device_refresh_on = 0;
5477
5478 mrioc->ts_update_counter = 0;
5479 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
5480 if (mrioc->watchdog_work_q)
5481 queue_delayed_work(mrioc->watchdog_work_q,
5482 &mrioc->watchdog_work,
5483 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
5484 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
5485 mrioc->stop_bsgs = 0;
5486 if (mrioc->pel_enabled)
5487 atomic64_inc(&event_counter);
5488 } else {
5489 mpi3mr_issue_reset(mrioc,
5490 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5491 mrioc->device_refresh_on = 0;
5492 mrioc->unrecoverable = 1;
5493 mrioc->reset_in_progress = 0;
5494 mrioc->stop_bsgs = 0;
5495 retval = -1;
5496 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
5497 }
5498 mrioc->prev_reset_result = retval;
5499 mutex_unlock(&mrioc->reset_mutex);
5500 ioc_info(mrioc, "controller reset is %s\n",
5501 ((retval == 0) ? "successful" : "failed"));
5502 return retval;
5503 }
5504
5505 /**
5506 * mpi3mr_post_cfg_req - Issue config requests and wait
5507 * @mrioc: Adapter instance reference
5508 * @cfg_req: Configuration request
5509 * @timeout: Timeout in seconds
5510 * @ioc_status: Pointer to return ioc status
5511 *
5512 * A generic function for posting MPI3 configuration request to
5513 * the firmware. This blocks for the completion of request for
5514 * timeout seconds and if the request times out this function
5515 * faults the controller with proper reason code.
5516 *
5517 * On successful completion of the request this function returns
5518 * appropriate ioc status from the firmware back to the caller.
5519 *
5520 * Return: 0 on success, non-zero on failure.
5521 */
mpi3mr_post_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,int timeout,u16 * ioc_status)5522 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5523 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5524 {
5525 int retval = 0;
5526
5527 mutex_lock(&mrioc->cfg_cmds.mutex);
5528 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5529 retval = -1;
5530 ioc_err(mrioc, "sending config request failed due to command in use\n");
5531 mutex_unlock(&mrioc->cfg_cmds.mutex);
5532 goto out;
5533 }
5534 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5535 mrioc->cfg_cmds.is_waiting = 1;
5536 mrioc->cfg_cmds.callback = NULL;
5537 mrioc->cfg_cmds.ioc_status = 0;
5538 mrioc->cfg_cmds.ioc_loginfo = 0;
5539
5540 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5541 cfg_req->function = MPI3_FUNCTION_CONFIG;
5542
5543 init_completion(&mrioc->cfg_cmds.done);
5544 dprint_cfg_info(mrioc, "posting config request\n");
5545 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5546 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5547 "mpi3_cfg_req");
5548 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5549 if (retval) {
5550 ioc_err(mrioc, "posting config request failed\n");
5551 goto out_unlock;
5552 }
5553 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5554 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5555 mpi3mr_check_rh_fault_ioc(mrioc,
5556 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5557 ioc_err(mrioc, "config request timed out\n");
5558 retval = -1;
5559 goto out_unlock;
5560 }
5561 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5562 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5563 dprint_cfg_err(mrioc,
5564 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5565 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5566
5567 out_unlock:
5568 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5569 mutex_unlock(&mrioc->cfg_cmds.mutex);
5570
5571 out:
5572 return retval;
5573 }
5574
5575 /**
5576 * mpi3mr_process_cfg_req - config page request processor
5577 * @mrioc: Adapter instance reference
5578 * @cfg_req: Configuration request
5579 * @cfg_hdr: Configuration page header
5580 * @timeout: Timeout in seconds
5581 * @ioc_status: Pointer to return ioc status
5582 * @cfg_buf: Memory pointer to copy config page or header
5583 * @cfg_buf_sz: Size of the memory to get config page or header
5584 *
5585 * This is handler for config page read, write and config page
5586 * header read operations.
5587 *
5588 * This function expects the cfg_req to be populated with page
5589 * type, page number, action for the header read and with page
5590 * address for all other operations.
5591 *
5592 * The cfg_hdr can be passed as null for reading required header
5593 * details for read/write pages the cfg_hdr should point valid
5594 * configuration page header.
5595 *
5596 * This allocates dmaable memory based on the size of the config
5597 * buffer and set the SGE of the cfg_req.
5598 *
5599 * For write actions, the config page data has to be passed in
5600 * the cfg_buf and size of the data has to be mentioned in the
5601 * cfg_buf_sz.
5602 *
5603 * For read/header actions, on successful completion of the
5604 * request with successful ioc_status the data will be copied
5605 * into the cfg_buf limited to a minimum of actual page size and
5606 * cfg_buf_sz
5607 *
5608 *
5609 * Return: 0 on success, non-zero on failure.
5610 */
mpi3mr_process_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,struct mpi3_config_page_header * cfg_hdr,int timeout,u16 * ioc_status,void * cfg_buf,u32 cfg_buf_sz)5611 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5612 struct mpi3_config_request *cfg_req,
5613 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5614 void *cfg_buf, u32 cfg_buf_sz)
5615 {
5616 struct dma_memory_desc mem_desc;
5617 int retval = -1;
5618 u8 invalid_action = 0;
5619 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5620
5621 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5622
5623 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5624 mem_desc.size = sizeof(struct mpi3_config_page_header);
5625 else {
5626 if (!cfg_hdr) {
5627 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5628 cfg_req->action, cfg_req->page_type,
5629 cfg_req->page_number);
5630 goto out;
5631 }
5632 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5633 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5634 if (cfg_req->action
5635 != MPI3_CONFIG_ACTION_READ_CURRENT)
5636 invalid_action = 1;
5637 break;
5638 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5639 if ((cfg_req->action ==
5640 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5641 (cfg_req->action ==
5642 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5643 invalid_action = 1;
5644 break;
5645 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5646 default:
5647 break;
5648 }
5649 if (invalid_action) {
5650 ioc_err(mrioc,
5651 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5652 cfg_req->action, cfg_req->page_type,
5653 cfg_req->page_number, cfg_hdr->page_attribute);
5654 goto out;
5655 }
5656 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5657 cfg_req->page_length = cfg_hdr->page_length;
5658 cfg_req->page_version = cfg_hdr->page_version;
5659 }
5660
5661 mem_desc.addr = dma_alloc_coherent(&mrioc->pdev->dev,
5662 mem_desc.size, &mem_desc.dma_addr, GFP_KERNEL);
5663
5664 if (!mem_desc.addr)
5665 return retval;
5666
5667 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5668 mem_desc.dma_addr);
5669
5670 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5671 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5672 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5673 cfg_buf_sz));
5674 dprint_cfg_info(mrioc, "config buffer to be written\n");
5675 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5676 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5677 }
5678
5679 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5680 goto out;
5681
5682 retval = 0;
5683 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5684 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5685 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5686 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5687 cfg_buf_sz));
5688 dprint_cfg_info(mrioc, "config buffer read\n");
5689 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5690 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5691 }
5692
5693 out:
5694 if (mem_desc.addr) {
5695 dma_free_coherent(&mrioc->pdev->dev, mem_desc.size,
5696 mem_desc.addr, mem_desc.dma_addr);
5697 mem_desc.addr = NULL;
5698 }
5699
5700 return retval;
5701 }
5702
5703 /**
5704 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5705 * @mrioc: Adapter instance reference
5706 * @ioc_status: Pointer to return ioc status
5707 * @dev_pg0: Pointer to return device page 0
5708 * @pg_sz: Size of the memory allocated to the page pointer
5709 * @form: The form to be used for addressing the page
5710 * @form_spec: Form specific information like device handle
5711 *
5712 * This is handler for config page read for a specific device
5713 * page0. The ioc_status has the controller returned ioc_status.
5714 * This routine doesn't check ioc_status to decide whether the
5715 * page read is success or not and it is the callers
5716 * responsibility.
5717 *
5718 * Return: 0 on success, non-zero on failure.
5719 */
mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_device_page0 * dev_pg0,u16 pg_sz,u32 form,u32 form_spec)5720 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5721 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5722 {
5723 struct mpi3_config_page_header cfg_hdr;
5724 struct mpi3_config_request cfg_req;
5725 u32 page_address;
5726
5727 memset(dev_pg0, 0, pg_sz);
5728 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5729 memset(&cfg_req, 0, sizeof(cfg_req));
5730
5731 cfg_req.function = MPI3_FUNCTION_CONFIG;
5732 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5733 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5734 cfg_req.page_number = 0;
5735 cfg_req.page_address = 0;
5736
5737 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5738 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5739 ioc_err(mrioc, "device page0 header read failed\n");
5740 goto out_failed;
5741 }
5742 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5743 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5744 *ioc_status);
5745 goto out_failed;
5746 }
5747 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5748 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5749 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5750 cfg_req.page_address = cpu_to_le32(page_address);
5751 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5752 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5753 ioc_err(mrioc, "device page0 read failed\n");
5754 goto out_failed;
5755 }
5756 return 0;
5757 out_failed:
5758 return -1;
5759 }
5760
5761
5762 /**
5763 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5764 * @mrioc: Adapter instance reference
5765 * @ioc_status: Pointer to return ioc status
5766 * @phy_pg0: Pointer to return SAS Phy page 0
5767 * @pg_sz: Size of the memory allocated to the page pointer
5768 * @form: The form to be used for addressing the page
5769 * @form_spec: Form specific information like phy number
5770 *
5771 * This is handler for config page read for a specific SAS Phy
5772 * page0. The ioc_status has the controller returned ioc_status.
5773 * This routine doesn't check ioc_status to decide whether the
5774 * page read is success or not and it is the callers
5775 * responsibility.
5776 *
5777 * Return: 0 on success, non-zero on failure.
5778 */
mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page0 * phy_pg0,u16 pg_sz,u32 form,u32 form_spec)5779 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5780 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5781 u32 form_spec)
5782 {
5783 struct mpi3_config_page_header cfg_hdr;
5784 struct mpi3_config_request cfg_req;
5785 u32 page_address;
5786
5787 memset(phy_pg0, 0, pg_sz);
5788 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5789 memset(&cfg_req, 0, sizeof(cfg_req));
5790
5791 cfg_req.function = MPI3_FUNCTION_CONFIG;
5792 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5793 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5794 cfg_req.page_number = 0;
5795 cfg_req.page_address = 0;
5796
5797 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5798 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5799 ioc_err(mrioc, "sas phy page0 header read failed\n");
5800 goto out_failed;
5801 }
5802 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5803 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5804 *ioc_status);
5805 goto out_failed;
5806 }
5807 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5808 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5809 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5810 cfg_req.page_address = cpu_to_le32(page_address);
5811 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5812 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5813 ioc_err(mrioc, "sas phy page0 read failed\n");
5814 goto out_failed;
5815 }
5816 return 0;
5817 out_failed:
5818 return -1;
5819 }
5820
5821 /**
5822 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5823 * @mrioc: Adapter instance reference
5824 * @ioc_status: Pointer to return ioc status
5825 * @phy_pg1: Pointer to return SAS Phy page 1
5826 * @pg_sz: Size of the memory allocated to the page pointer
5827 * @form: The form to be used for addressing the page
5828 * @form_spec: Form specific information like phy number
5829 *
5830 * This is handler for config page read for a specific SAS Phy
5831 * page1. The ioc_status has the controller returned ioc_status.
5832 * This routine doesn't check ioc_status to decide whether the
5833 * page read is success or not and it is the callers
5834 * responsibility.
5835 *
5836 * Return: 0 on success, non-zero on failure.
5837 */
mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page1 * phy_pg1,u16 pg_sz,u32 form,u32 form_spec)5838 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5839 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5840 u32 form_spec)
5841 {
5842 struct mpi3_config_page_header cfg_hdr;
5843 struct mpi3_config_request cfg_req;
5844 u32 page_address;
5845
5846 memset(phy_pg1, 0, pg_sz);
5847 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5848 memset(&cfg_req, 0, sizeof(cfg_req));
5849
5850 cfg_req.function = MPI3_FUNCTION_CONFIG;
5851 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5852 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5853 cfg_req.page_number = 1;
5854 cfg_req.page_address = 0;
5855
5856 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5857 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5858 ioc_err(mrioc, "sas phy page1 header read failed\n");
5859 goto out_failed;
5860 }
5861 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5862 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5863 *ioc_status);
5864 goto out_failed;
5865 }
5866 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5867 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5868 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5869 cfg_req.page_address = cpu_to_le32(page_address);
5870 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5871 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5872 ioc_err(mrioc, "sas phy page1 read failed\n");
5873 goto out_failed;
5874 }
5875 return 0;
5876 out_failed:
5877 return -1;
5878 }
5879
5880
5881 /**
5882 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5883 * @mrioc: Adapter instance reference
5884 * @ioc_status: Pointer to return ioc status
5885 * @exp_pg0: Pointer to return SAS Expander page 0
5886 * @pg_sz: Size of the memory allocated to the page pointer
5887 * @form: The form to be used for addressing the page
5888 * @form_spec: Form specific information like device handle
5889 *
5890 * This is handler for config page read for a specific SAS
5891 * Expander page0. The ioc_status has the controller returned
5892 * ioc_status. This routine doesn't check ioc_status to decide
5893 * whether the page read is success or not and it is the callers
5894 * responsibility.
5895 *
5896 * Return: 0 on success, non-zero on failure.
5897 */
mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page0 * exp_pg0,u16 pg_sz,u32 form,u32 form_spec)5898 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5899 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5900 u32 form_spec)
5901 {
5902 struct mpi3_config_page_header cfg_hdr;
5903 struct mpi3_config_request cfg_req;
5904 u32 page_address;
5905
5906 memset(exp_pg0, 0, pg_sz);
5907 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5908 memset(&cfg_req, 0, sizeof(cfg_req));
5909
5910 cfg_req.function = MPI3_FUNCTION_CONFIG;
5911 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5912 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5913 cfg_req.page_number = 0;
5914 cfg_req.page_address = 0;
5915
5916 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5917 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5918 ioc_err(mrioc, "expander page0 header read failed\n");
5919 goto out_failed;
5920 }
5921 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5922 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5923 *ioc_status);
5924 goto out_failed;
5925 }
5926 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5927 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5928 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5929 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5930 cfg_req.page_address = cpu_to_le32(page_address);
5931 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5932 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5933 ioc_err(mrioc, "expander page0 read failed\n");
5934 goto out_failed;
5935 }
5936 return 0;
5937 out_failed:
5938 return -1;
5939 }
5940
5941 /**
5942 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5943 * @mrioc: Adapter instance reference
5944 * @ioc_status: Pointer to return ioc status
5945 * @exp_pg1: Pointer to return SAS Expander page 1
5946 * @pg_sz: Size of the memory allocated to the page pointer
5947 * @form: The form to be used for addressing the page
5948 * @form_spec: Form specific information like phy number
5949 *
5950 * This is handler for config page read for a specific SAS
5951 * Expander page1. The ioc_status has the controller returned
5952 * ioc_status. This routine doesn't check ioc_status to decide
5953 * whether the page read is success or not and it is the callers
5954 * responsibility.
5955 *
5956 * Return: 0 on success, non-zero on failure.
5957 */
mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page1 * exp_pg1,u16 pg_sz,u32 form,u32 form_spec)5958 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5959 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5960 u32 form_spec)
5961 {
5962 struct mpi3_config_page_header cfg_hdr;
5963 struct mpi3_config_request cfg_req;
5964 u32 page_address;
5965
5966 memset(exp_pg1, 0, pg_sz);
5967 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5968 memset(&cfg_req, 0, sizeof(cfg_req));
5969
5970 cfg_req.function = MPI3_FUNCTION_CONFIG;
5971 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5972 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5973 cfg_req.page_number = 1;
5974 cfg_req.page_address = 0;
5975
5976 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5977 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5978 ioc_err(mrioc, "expander page1 header read failed\n");
5979 goto out_failed;
5980 }
5981 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5982 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5983 *ioc_status);
5984 goto out_failed;
5985 }
5986 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5987 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5988 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5989 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5990 cfg_req.page_address = cpu_to_le32(page_address);
5991 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5992 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5993 ioc_err(mrioc, "expander page1 read failed\n");
5994 goto out_failed;
5995 }
5996 return 0;
5997 out_failed:
5998 return -1;
5999 }
6000
6001 /**
6002 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
6003 * @mrioc: Adapter instance reference
6004 * @ioc_status: Pointer to return ioc status
6005 * @encl_pg0: Pointer to return Enclosure page 0
6006 * @pg_sz: Size of the memory allocated to the page pointer
6007 * @form: The form to be used for addressing the page
6008 * @form_spec: Form specific information like device handle
6009 *
6010 * This is handler for config page read for a specific Enclosure
6011 * page0. The ioc_status has the controller returned ioc_status.
6012 * This routine doesn't check ioc_status to decide whether the
6013 * page read is success or not and it is the callers
6014 * responsibility.
6015 *
6016 * Return: 0 on success, non-zero on failure.
6017 */
mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_enclosure_page0 * encl_pg0,u16 pg_sz,u32 form,u32 form_spec)6018 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6019 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
6020 u32 form_spec)
6021 {
6022 struct mpi3_config_page_header cfg_hdr;
6023 struct mpi3_config_request cfg_req;
6024 u32 page_address;
6025
6026 memset(encl_pg0, 0, pg_sz);
6027 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6028 memset(&cfg_req, 0, sizeof(cfg_req));
6029
6030 cfg_req.function = MPI3_FUNCTION_CONFIG;
6031 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6032 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
6033 cfg_req.page_number = 0;
6034 cfg_req.page_address = 0;
6035
6036 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6037 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6038 ioc_err(mrioc, "enclosure page0 header read failed\n");
6039 goto out_failed;
6040 }
6041 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6042 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
6043 *ioc_status);
6044 goto out_failed;
6045 }
6046 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6047 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
6048 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
6049 cfg_req.page_address = cpu_to_le32(page_address);
6050 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6051 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
6052 ioc_err(mrioc, "enclosure page0 read failed\n");
6053 goto out_failed;
6054 }
6055 return 0;
6056 out_failed:
6057 return -1;
6058 }
6059
6060
6061 /**
6062 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
6063 * @mrioc: Adapter instance reference
6064 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
6065 * @pg_sz: Size of the memory allocated to the page pointer
6066 *
6067 * This is handler for config page read for the SAS IO Unit
6068 * page0. This routine checks ioc_status to decide whether the
6069 * page read is success or not.
6070 *
6071 * Return: 0 on success, non-zero on failure.
6072 */
mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page0 * sas_io_unit_pg0,u16 pg_sz)6073 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
6074 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
6075 {
6076 struct mpi3_config_page_header cfg_hdr;
6077 struct mpi3_config_request cfg_req;
6078 u16 ioc_status = 0;
6079
6080 memset(sas_io_unit_pg0, 0, pg_sz);
6081 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6082 memset(&cfg_req, 0, sizeof(cfg_req));
6083
6084 cfg_req.function = MPI3_FUNCTION_CONFIG;
6085 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6086 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6087 cfg_req.page_number = 0;
6088 cfg_req.page_address = 0;
6089
6090 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6091 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6092 ioc_err(mrioc, "sas io unit page0 header read failed\n");
6093 goto out_failed;
6094 }
6095 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6096 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
6097 ioc_status);
6098 goto out_failed;
6099 }
6100 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6101
6102 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6103 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
6104 ioc_err(mrioc, "sas io unit page0 read failed\n");
6105 goto out_failed;
6106 }
6107 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6108 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
6109 ioc_status);
6110 goto out_failed;
6111 }
6112 return 0;
6113 out_failed:
6114 return -1;
6115 }
6116
6117 /**
6118 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
6119 * @mrioc: Adapter instance reference
6120 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
6121 * @pg_sz: Size of the memory allocated to the page pointer
6122 *
6123 * This is handler for config page read for the SAS IO Unit
6124 * page1. This routine checks ioc_status to decide whether the
6125 * page read is success or not.
6126 *
6127 * Return: 0 on success, non-zero on failure.
6128 */
mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)6129 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6130 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6131 {
6132 struct mpi3_config_page_header cfg_hdr;
6133 struct mpi3_config_request cfg_req;
6134 u16 ioc_status = 0;
6135
6136 memset(sas_io_unit_pg1, 0, pg_sz);
6137 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6138 memset(&cfg_req, 0, sizeof(cfg_req));
6139
6140 cfg_req.function = MPI3_FUNCTION_CONFIG;
6141 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6142 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6143 cfg_req.page_number = 1;
6144 cfg_req.page_address = 0;
6145
6146 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6147 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6148 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6149 goto out_failed;
6150 }
6151 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6152 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6153 ioc_status);
6154 goto out_failed;
6155 }
6156 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6157
6158 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6159 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6160 ioc_err(mrioc, "sas io unit page1 read failed\n");
6161 goto out_failed;
6162 }
6163 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6164 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
6165 ioc_status);
6166 goto out_failed;
6167 }
6168 return 0;
6169 out_failed:
6170 return -1;
6171 }
6172
6173 /**
6174 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
6175 * @mrioc: Adapter instance reference
6176 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
6177 * @pg_sz: Size of the memory allocated to the page pointer
6178 *
6179 * This is handler for config page write for the SAS IO Unit
6180 * page1. This routine checks ioc_status to decide whether the
6181 * page read is success or not. This will modify both current
6182 * and persistent page.
6183 *
6184 * Return: 0 on success, non-zero on failure.
6185 */
mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)6186 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6187 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6188 {
6189 struct mpi3_config_page_header cfg_hdr;
6190 struct mpi3_config_request cfg_req;
6191 u16 ioc_status = 0;
6192
6193 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6194 memset(&cfg_req, 0, sizeof(cfg_req));
6195
6196 cfg_req.function = MPI3_FUNCTION_CONFIG;
6197 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6198 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6199 cfg_req.page_number = 1;
6200 cfg_req.page_address = 0;
6201
6202 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6203 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6204 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6205 goto out_failed;
6206 }
6207 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6208 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6209 ioc_status);
6210 goto out_failed;
6211 }
6212 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
6213
6214 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6215 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6216 ioc_err(mrioc, "sas io unit page1 write current failed\n");
6217 goto out_failed;
6218 }
6219 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6220 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
6221 ioc_status);
6222 goto out_failed;
6223 }
6224
6225 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
6226
6227 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6228 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6229 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
6230 goto out_failed;
6231 }
6232 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6233 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
6234 ioc_status);
6235 goto out_failed;
6236 }
6237 return 0;
6238 out_failed:
6239 return -1;
6240 }
6241
6242 /**
6243 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
6244 * @mrioc: Adapter instance reference
6245 * @driver_pg1: Pointer to return Driver page 1
6246 * @pg_sz: Size of the memory allocated to the page pointer
6247 *
6248 * This is handler for config page read for the Driver page1.
6249 * This routine checks ioc_status to decide whether the page
6250 * read is success or not.
6251 *
6252 * Return: 0 on success, non-zero on failure.
6253 */
mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page1 * driver_pg1,u16 pg_sz)6254 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
6255 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
6256 {
6257 struct mpi3_config_page_header cfg_hdr;
6258 struct mpi3_config_request cfg_req;
6259 u16 ioc_status = 0;
6260
6261 memset(driver_pg1, 0, pg_sz);
6262 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6263 memset(&cfg_req, 0, sizeof(cfg_req));
6264
6265 cfg_req.function = MPI3_FUNCTION_CONFIG;
6266 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6267 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6268 cfg_req.page_number = 1;
6269 cfg_req.page_address = 0;
6270
6271 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6272 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6273 ioc_err(mrioc, "driver page1 header read failed\n");
6274 goto out_failed;
6275 }
6276 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6277 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
6278 ioc_status);
6279 goto out_failed;
6280 }
6281 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6282
6283 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6284 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
6285 ioc_err(mrioc, "driver page1 read failed\n");
6286 goto out_failed;
6287 }
6288 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6289 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
6290 ioc_status);
6291 goto out_failed;
6292 }
6293 return 0;
6294 out_failed:
6295 return -1;
6296 }
6297
6298 /**
6299 * mpi3mr_cfg_get_driver_pg2 - Read current driver page2
6300 * @mrioc: Adapter instance reference
6301 * @driver_pg2: Pointer to return driver page 2
6302 * @pg_sz: Size of the memory allocated to the page pointer
6303 * @page_action: Page action
6304 *
6305 * This is handler for config page read for the driver page2.
6306 * This routine checks ioc_status to decide whether the page
6307 * read is success or not.
6308 *
6309 * Return: 0 on success, non-zero on failure.
6310 */
mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page2 * driver_pg2,u16 pg_sz,u8 page_action)6311 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
6312 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_action)
6313 {
6314 struct mpi3_config_page_header cfg_hdr;
6315 struct mpi3_config_request cfg_req;
6316 u16 ioc_status = 0;
6317
6318 memset(driver_pg2, 0, pg_sz);
6319 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6320 memset(&cfg_req, 0, sizeof(cfg_req));
6321
6322 cfg_req.function = MPI3_FUNCTION_CONFIG;
6323 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6324 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6325 cfg_req.page_number = 2;
6326 cfg_req.page_address = 0;
6327 cfg_req.page_version = MPI3_DRIVER2_PAGEVERSION;
6328
6329 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6330 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6331 ioc_err(mrioc, "driver page2 header read failed\n");
6332 goto out_failed;
6333 }
6334 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6335 ioc_err(mrioc, "driver page2 header read failed with\n"
6336 "ioc_status(0x%04x)\n",
6337 ioc_status);
6338 goto out_failed;
6339 }
6340 cfg_req.action = page_action;
6341
6342 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6343 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg2, pg_sz)) {
6344 ioc_err(mrioc, "driver page2 read failed\n");
6345 goto out_failed;
6346 }
6347 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6348 ioc_err(mrioc, "driver page2 read failed with\n"
6349 "ioc_status(0x%04x)\n",
6350 ioc_status);
6351 goto out_failed;
6352 }
6353 return 0;
6354 out_failed:
6355 return -1;
6356 }
6357
6358