1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: [email protected])
7 *
8 */
9
10 #ifndef MPI3MR_H_INCLUDED
11 #define MPI3MR_H_INCLUDED
12
13 #include <linux/blkdev.h>
14 #include <linux/blk-mq.h>
15 #include <linux/delay.h>
16 #include <linux/dmapool.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/miscdevice.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/aer.h>
26 #include <linux/poll.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
30 #include <linux/uaccess.h>
31 #include <linux/utsname.h>
32 #include <linux/workqueue.h>
33 #include <linux/unaligned.h>
34 #include <scsi/scsi.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <scsi/scsi_dbg.h>
37 #include <scsi/scsi_device.h>
38 #include <scsi/scsi_host.h>
39 #include <scsi/scsi_tcq.h>
40 #include <uapi/scsi/scsi_bsg_mpi3mr.h>
41 #include <scsi/scsi_transport_sas.h>
42
43 #include "mpi/mpi30_transport.h"
44 #include "mpi/mpi30_cnfg.h"
45 #include "mpi/mpi30_image.h"
46 #include "mpi/mpi30_init.h"
47 #include "mpi/mpi30_ioc.h"
48 #include "mpi/mpi30_sas.h"
49 #include "mpi/mpi30_pci.h"
50 #include "mpi/mpi30_tool.h"
51 #include "mpi3mr_debug.h"
52
53 /* Global list and lock for storing multiple adapters managed by the driver */
54 extern spinlock_t mrioc_list_lock;
55 extern struct list_head mrioc_list;
56 extern int prot_mask;
57 extern atomic64_t event_counter;
58
59 #define MPI3MR_DRIVER_VERSION "8.12.0.3.50"
60 #define MPI3MR_DRIVER_RELDATE "11-November-2024"
61
62 #define MPI3MR_DRIVER_NAME "mpi3mr"
63 #define MPI3MR_DRIVER_LICENSE "GPL"
64 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <[email protected]>"
65 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
66
67 #define MPI3MR_NAME_LENGTH 64
68 #define IOCNAME "%s: "
69
70 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024)
71
72 /* Definitions for internal SGL and Chain SGL buffers */
73 #define MPI3MR_PAGE_SIZE_4K 4096
74 #define MPI3MR_DEFAULT_SGL_ENTRIES 256
75 #define MPI3MR_MAX_SGL_ENTRIES 2048
76
77 /* Definitions for MAX values for shost */
78 #define MPI3MR_MAX_CMDS_LUN 128
79 #define MPI3MR_MAX_CDB_LENGTH 32
80
81 /* Admin queue management definitions */
82 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
83 #define MPI3MR_ADMIN_REPLY_Q_SIZE (8 * MPI3MR_PAGE_SIZE_4K)
84 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128
85 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
86
87 /* Operational queue management definitions */
88 #define MPI3MR_OP_REQ_Q_QD 512
89 #define MPI3MR_OP_REP_Q_QD 1024
90 #define MPI3MR_OP_REP_Q_QD2K 2048
91 #define MPI3MR_OP_REP_Q_QD4K 4096
92 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
93 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096
94 #define MPI3MR_MAX_SEG_LIST_SIZE 4096
95
96 /* Reserved Host Tag definitions */
97 #define MPI3MR_HOSTTAG_INVALID 0xFFFF
98 #define MPI3MR_HOSTTAG_INITCMDS 1
99 #define MPI3MR_HOSTTAG_BSG_CMDS 2
100 #define MPI3MR_HOSTTAG_PEL_ABORT 3
101 #define MPI3MR_HOSTTAG_PEL_WAIT 4
102 #define MPI3MR_HOSTTAG_BLK_TMS 5
103 #define MPI3MR_HOSTTAG_CFG_CMDS 6
104 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7
105
106 #define MPI3MR_NUM_DEVRMCMD 16
107 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1)
108 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
109 MPI3MR_NUM_DEVRMCMD - 1)
110
111 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
112 #define MPI3MR_NUM_EVTACKCMD 4
113 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
114 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
115 MPI3MR_NUM_EVTACKCMD - 1)
116
117 /* Reduced resource count definition for crash kernel */
118 #define MPI3MR_HOST_IOS_KDUMP 128
119
120 /* command/controller interaction timeout definitions in seconds */
121 #define MPI3MR_INTADMCMD_TIMEOUT 60
122 #define MPI3MR_PORTENABLE_TIMEOUT 300
123 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5
124 #define MPI3MR_ABORTTM_TIMEOUT 60
125 #define MPI3MR_RESETTM_TIMEOUT 60
126 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
127 #define MPI3MR_TSUPDATE_INTERVAL 900
128 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
129 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
130 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
131 #define MPI3MR_RESET_ACK_TIMEOUT 30
132 #define MPI3MR_MUR_TIMEOUT 120
133 #define MPI3MR_RESET_TIMEOUT 510
134
135 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
136
137 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10
138
139 #define MPI3MR_SCMD_TIMEOUT (60 * HZ)
140 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)
141
142 /* Internal admin command state definitions*/
143 #define MPI3MR_CMD_NOTUSED 0x8000
144 #define MPI3MR_CMD_COMPLETE 0x0001
145 #define MPI3MR_CMD_PENDING 0x0002
146 #define MPI3MR_CMD_REPLY_VALID 0x0004
147 #define MPI3MR_CMD_RESET 0x0008
148
149 /* Definitions for Event replies and sense buffer allocated per controller */
150 #define MPI3MR_NUM_EVT_REPLIES 64
151 #define MPI3MR_SENSE_BUF_SZ 256
152 #define MPI3MR_SENSEBUF_FACTOR 3
153 #define MPI3MR_CHAINBUF_FACTOR 3
154 #define MPI3MR_CHAINBUFDIX_FACTOR 2
155
156 /* Invalid target device handle */
157 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
158
159 /* Controller Reset related definitions */
160 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
161 #define MPI3MR_MAX_RESET_RETRY_COUNT 3
162
163 /* ResponseCode definitions */
164 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
165 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
166 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
167
168 #define MPI3MR_DEFAULT_MDTS (128 * 1024)
169 #define MPI3MR_DEFAULT_PGSZEXP (12)
170
171 /* Command retry count definitions */
172 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3
173 #define MPI3MR_PEL_RETRY_COUNT 3
174
175 /* Default target device queue depth */
176 #define MPI3MR_DEFAULT_SDEV_QD 32
177
178 /* Definitions for Threaded IRQ poll*/
179 #define MPI3MR_IRQ_POLL_SLEEP 20
180 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
181
182 /* Definitions for the controller security status*/
183 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
184 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
185
186 #define MPI3MR_INVALID_DEVICE 0x00
187 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04
188 #define MPI3MR_HARD_SECURE_DEVICE 0x08
189 #define MPI3MR_TAMPERED_DEVICE 0x0C
190
191 #define MPI3MR_DEFAULT_HDB_MAX_SZ (4 * 1024 * 1024)
192 #define MPI3MR_DEFAULT_HDB_DEC_SZ (1 * 1024 * 1024)
193 #define MPI3MR_DEFAULT_HDB_MIN_SZ (2 * 1024 * 1024)
194 #define MPI3MR_MAX_NUM_HDB 2
195
196 #define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0
197 #define MPI3MR_HDB_TRIGGER_TYPE_FAULT 1
198 #define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2
199 #define MPI3MR_HDB_TRIGGER_TYPE_GLOBAL 3
200 #define MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET 4
201 #define MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED 5
202
203 #define MPI3MR_HDB_REFRESH_TYPE_RESERVED 0
204 #define MPI3MR_HDB_REFRESH_TYPE_CURRENT 1
205 #define MPI3MR_HDB_REFRESH_TYPE_DEFAULT 2
206 #define MPI3MR_HDB_HDB_REFRESH_TYPE_PERSISTENT 3
207
208 #define MPI3MR_DEFAULT_HDB_SZ (4 * 1024 * 1024)
209 #define MPI3MR_MAX_NUM_HDB 2
210
211 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_INDEX 0
212 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_DATA 1
213
214 #define MPI3MR_THRESHOLD_REPLY_COUNT 100
215
216 /* SGE Flag definition */
217 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
218 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
219 MPI3_SGE_FLAGS_END_OF_LIST)
220
221 /* MSI Index from Reply Queue Index */
222 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
223
224 /*
225 * Maximum data transfer size definitions for management
226 * application commands
227 */
228 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024)
229 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512
230 /*
231 * 2048 sectors are for data buffers and additional 512 sectors for
232 * other buffers
233 */
234 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)
235
236 #define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256
237 #define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048
238
239 #define MPI3MR_DRIVER_EVENT_PROCESS_TRIGGER (0xFFFD)
240
241 /**
242 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe
243 * Encapsulated commands.
244 *
245 * @base_addr: Physical address
246 * @length: SGE length
247 * @rsvd: Reserved
248 * @rsvd1: Reserved
249 * @sub_type: sgl sub type
250 * @type: sgl type
251 */
252 struct mpi3mr_nvme_pt_sge {
253 __le64 base_addr;
254 __le32 length;
255 u16 rsvd;
256 u8 rsvd1;
257 u8 sub_type:4;
258 u8 type:4;
259 };
260
261 /**
262 * struct mpi3mr_buf_map - local structure to
263 * track kernel and user buffers associated with an BSG
264 * structure.
265 *
266 * @bsg_buf: BSG buffer virtual address
267 * @bsg_buf_len: BSG buffer length
268 * @kern_buf: Kernel buffer virtual address
269 * @kern_buf_len: Kernel buffer length
270 * @kern_buf_dma: Kernel buffer DMA address
271 * @data_dir: Data direction.
272 */
273 struct mpi3mr_buf_map {
274 void *bsg_buf;
275 u32 bsg_buf_len;
276 void *kern_buf;
277 u32 kern_buf_len;
278 dma_addr_t kern_buf_dma;
279 u8 data_dir;
280 u16 num_dma_desc;
281 struct dma_memory_desc *dma_desc;
282 };
283
284 /* IOC State definitions */
285 enum mpi3mr_iocstate {
286 MRIOC_STATE_READY = 1,
287 MRIOC_STATE_RESET,
288 MRIOC_STATE_FAULT,
289 MRIOC_STATE_BECOMING_READY,
290 MRIOC_STATE_RESET_REQUESTED,
291 MRIOC_STATE_UNRECOVERABLE,
292 };
293
294 /* Reset reason code definitions*/
295 enum mpi3mr_reset_reason {
296 MPI3MR_RESET_FROM_BRINGUP = 1,
297 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
298 MPI3MR_RESET_FROM_APP = 3,
299 MPI3MR_RESET_FROM_EH_HOS = 4,
300 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
301 MPI3MR_RESET_FROM_APP_TIMEOUT = 6,
302 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
303 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
304 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
305 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
306 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
307 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
308 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
309 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
310 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
311 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
312 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
313 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
314 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
315 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
316 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
317 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
318 MPI3MR_RESET_FROM_SYSFS = 23,
319 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
320 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25,
321 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT = 26,
322 MPI3MR_RESET_FROM_FIRMWARE = 27,
323 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29,
324 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,
325 MPI3MR_RESET_FROM_TRIGGER = 31,
326 };
327
328 #define MPI3MR_RESET_REASON_OSTYPE_LINUX 1
329 #define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28
330 #define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20
331
332
333 /* Queue type definitions */
334 enum queue_type {
335 MPI3MR_DEFAULT_QUEUE = 0,
336 MPI3MR_POLL_QUEUE,
337 };
338
339 /**
340 * struct mpi3mr_compimg_ver - replica of component image
341 * version defined in mpi30_image.h in host endianness
342 *
343 */
344 struct mpi3mr_compimg_ver {
345 u16 build_num;
346 u16 cust_id;
347 u8 ph_minor;
348 u8 ph_major;
349 u8 gen_minor;
350 u8 gen_major;
351 };
352
353 /**
354 * struct mpi3mr_ioc_facs - replica of component image version
355 * defined in mpi30_ioc.h in host endianness
356 *
357 */
358 struct mpi3mr_ioc_facts {
359 u32 ioc_capabilities;
360 struct mpi3mr_compimg_ver fw_ver;
361 u32 mpi_version;
362 u32 diag_trace_sz;
363 u32 diag_fw_sz;
364 u32 diag_drvr_sz;
365 u16 max_reqs;
366 u16 product_id;
367 u16 op_req_sz;
368 u16 reply_sz;
369 u16 exceptions;
370 u16 max_perids;
371 u16 max_pds;
372 u16 max_sasexpanders;
373 u32 max_data_length;
374 u16 max_sasinitiators;
375 u16 max_enclosures;
376 u16 max_pcie_switches;
377 u16 max_nvme;
378 u16 max_vds;
379 u16 max_hpds;
380 u16 max_advhpds;
381 u16 max_raid_pds;
382 u16 min_devhandle;
383 u16 max_devhandle;
384 u16 max_op_req_q;
385 u16 max_op_reply_q;
386 u16 shutdown_timeout;
387 u8 ioc_num;
388 u8 who_init;
389 u16 max_msix_vectors;
390 u8 personality;
391 u8 dma_mask;
392 bool max_req_limit;
393 u8 protocol_flags;
394 u8 sge_mod_mask;
395 u8 sge_mod_value;
396 u8 sge_mod_shift;
397 u8 max_dev_per_tg;
398 u16 max_io_throttle_group;
399 u16 io_throttle_data_length;
400 u16 io_throttle_low;
401 u16 io_throttle_high;
402
403 };
404
405 /**
406 * struct segments - memory descriptor structure to store
407 * virtual and dma addresses for operational queue segments.
408 *
409 * @segment: virtual address
410 * @segment_dma: dma address
411 */
412 struct segments {
413 void *segment;
414 dma_addr_t segment_dma;
415 };
416
417 /**
418 * struct op_req_qinfo - Operational Request Queue Information
419 *
420 * @ci: consumer index
421 * @pi: producer index
422 * @num_request: Maximum number of entries in the queue
423 * @qid: Queue Id starting from 1
424 * @reply_qid: Associated reply queue Id
425 * @num_segments: Number of discontiguous memory segments
426 * @segment_qd: Depth of each segments
427 * @q_lock: Concurrent queue access lock
428 * @q_segments: Segment descriptor pointer
429 * @q_segment_list: Segment list base virtual address
430 * @q_segment_list_dma: Segment list base DMA address
431 */
432 struct op_req_qinfo {
433 u16 ci;
434 u16 pi;
435 u16 num_requests;
436 u16 qid;
437 u16 reply_qid;
438 u16 num_segments;
439 u16 segment_qd;
440 spinlock_t q_lock;
441 struct segments *q_segments;
442 void *q_segment_list;
443 dma_addr_t q_segment_list_dma;
444 };
445
446 /**
447 * struct op_reply_qinfo - Operational Reply Queue Information
448 *
449 * @ci: consumer index
450 * @qid: Queue Id starting from 1
451 * @num_replies: Maximum number of entries in the queue
452 * @num_segments: Number of discontiguous memory segments
453 * @segment_qd: Depth of each segments
454 * @q_segments: Segment descriptor pointer
455 * @q_segment_list: Segment list base virtual address
456 * @q_segment_list_dma: Segment list base DMA address
457 * @ephase: Expected phased identifier for the reply queue
458 * @pend_ios: Number of IOs pending in HW for this queue
459 * @enable_irq_poll: Flag to indicate polling is enabled
460 * @in_use: Queue is handled by poll/ISR
461 * @qtype: Type of queue (types defined in enum queue_type)
462 * @qfull_watermark: Watermark defined in reply queue to avoid
463 * reply queue full
464 */
465 struct op_reply_qinfo {
466 u16 ci;
467 u16 qid;
468 u16 num_replies;
469 u16 num_segments;
470 u16 segment_qd;
471 struct segments *q_segments;
472 void *q_segment_list;
473 dma_addr_t q_segment_list_dma;
474 u8 ephase;
475 atomic_t pend_ios;
476 bool enable_irq_poll;
477 atomic_t in_use;
478 enum queue_type qtype;
479 u16 qfull_watermark;
480 };
481
482 /**
483 * struct mpi3mr_intr_info - Interrupt cookie information
484 *
485 * @mrioc: Adapter instance reference
486 * @os_irq: irq number
487 * @msix_index: MSIx index
488 * @op_reply_q: Associated operational reply queue
489 * @name: Dev name for the irq claiming device
490 */
491 struct mpi3mr_intr_info {
492 struct mpi3mr_ioc *mrioc;
493 int os_irq;
494 u16 msix_index;
495 struct op_reply_qinfo *op_reply_q;
496 char name[MPI3MR_NAME_LENGTH];
497 };
498
499 /**
500 * struct mpi3mr_throttle_group_info - Throttle group info
501 *
502 * @io_divert: Flag indicates io divert is on or off for the TG
503 * @need_qd_reduction: Flag to indicate QD reduction is needed
504 * @qd_reduction: Queue Depth reduction in units of 10%
505 * @fw_qd: QueueDepth value reported by the firmware
506 * @modified_qd: Modified QueueDepth value due to throttling
507 * @id: Throttle Group ID.
508 * @high: High limit to turn on throttling in 512 byte blocks
509 * @low: Low limit to turn off throttling in 512 byte blocks
510 * @pend_large_data_sz: Counter to track pending large data
511 */
512 struct mpi3mr_throttle_group_info {
513 u8 io_divert;
514 u8 need_qd_reduction;
515 u8 qd_reduction;
516 u16 fw_qd;
517 u16 modified_qd;
518 u16 id;
519 u32 high;
520 u32 low;
521 atomic_t pend_large_data_sz;
522 };
523
524 /* HBA port flags */
525 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01
526 #define MPI3MR_HBA_PORT_FLAG_NEW 0x02
527
528 /* IOCTL data transfer sge*/
529 #define MPI3MR_NUM_IOCTL_SGE 256
530 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024)
531
532 /**
533 * struct mpi3mr_hba_port - HBA's port information
534 * @port_id: Port number
535 * @flags: HBA port flags
536 */
537 struct mpi3mr_hba_port {
538 struct list_head list;
539 u8 port_id;
540 u8 flags;
541 };
542
543 /**
544 * struct mpi3mr_sas_port - Internal SAS port information
545 * @port_list: List of ports belonging to a SAS node
546 * @num_phys: Number of phys associated with port
547 * @marked_responding: used while refresing the sas ports
548 * @lowest_phy: lowest phy ID of current sas port, valid for controller port
549 * @phy_mask: phy_mask of current sas port, valid for controller port
550 * @hba_port: HBA port entry
551 * @remote_identify: Attached device identification
552 * @rphy: SAS transport layer rphy object
553 * @port: SAS transport layer port object
554 * @phy_list: mpi3mr_sas_phy objects belonging to this port
555 */
556 struct mpi3mr_sas_port {
557 struct list_head port_list;
558 u8 num_phys;
559 u8 marked_responding;
560 int lowest_phy;
561 u64 phy_mask;
562 struct mpi3mr_hba_port *hba_port;
563 struct sas_identify remote_identify;
564 struct sas_rphy *rphy;
565 struct sas_port *port;
566 struct list_head phy_list;
567 };
568
569 /**
570 * struct mpi3mr_sas_phy - Internal SAS Phy information
571 * @port_siblings: List of phys belonging to a port
572 * @identify: Phy identification
573 * @remote_identify: Attached device identification
574 * @phy: SAS transport layer Phy object
575 * @phy_id: Unique phy id within a port
576 * @handle: Firmware device handle for this phy
577 * @attached_handle: Firmware device handle for attached device
578 * @phy_belongs_to_port: Flag to indicate phy belongs to port
579 @hba_port: HBA port entry
580 */
581 struct mpi3mr_sas_phy {
582 struct list_head port_siblings;
583 struct sas_identify identify;
584 struct sas_identify remote_identify;
585 struct sas_phy *phy;
586 u8 phy_id;
587 u16 handle;
588 u16 attached_handle;
589 u8 phy_belongs_to_port;
590 struct mpi3mr_hba_port *hba_port;
591 };
592
593 /**
594 * struct mpi3mr_sas_node - SAS host/expander information
595 * @list: List of sas nodes in a controller
596 * @parent_dev: Parent device class
597 * @num_phys: Number phys belonging to sas_node
598 * @sas_address: SAS address of sas_node
599 * @handle: Firmware device handle for this sas_host/expander
600 * @sas_address_parent: SAS address of parent expander or host
601 * @enclosure_handle: Firmware handle of enclosure of this node
602 * @device_info: Capabilities of this sas_host/expander
603 * @non_responding: used to refresh the expander devices during reset
604 * @host_node: Flag to indicate this is a host_node
605 * @hba_port: HBA port entry
606 * @phy: A list of phys that make up this sas_host/expander
607 * @sas_port_list: List of internal ports of this node
608 * @rphy: sas_rphy object of this expander node
609 */
610 struct mpi3mr_sas_node {
611 struct list_head list;
612 struct device *parent_dev;
613 u8 num_phys;
614 u64 sas_address;
615 u16 handle;
616 u64 sas_address_parent;
617 u16 enclosure_handle;
618 u64 enclosure_logical_id;
619 u8 non_responding;
620 u8 host_node;
621 struct mpi3mr_hba_port *hba_port;
622 struct mpi3mr_sas_phy *phy;
623 struct list_head sas_port_list;
624 struct sas_rphy *rphy;
625 };
626
627 /**
628 * struct mpi3mr_enclosure_node - enclosure information
629 * @list: List of enclosures
630 * @pg0: Enclosure page 0;
631 */
632 struct mpi3mr_enclosure_node {
633 struct list_head list;
634 struct mpi3_enclosure_page0 pg0;
635 };
636
637 /**
638 * struct tgt_dev_sas_sata - SAS/SATA device specific
639 * information cached from firmware given data
640 *
641 * @sas_address: World wide unique SAS address
642 * @sas_address_parent: Sas address of parent expander or host
643 * @dev_info: Device information bits
644 * @phy_id: Phy identifier provided in device page 0
645 * @attached_phy_id: Attached phy identifier provided in device page 0
646 * @sas_transport_attached: Is this device exposed to transport
647 * @pend_sas_rphy_add: Flag to check device is in process of add
648 * @hba_port: HBA port entry
649 * @rphy: SAS transport layer rphy object
650 */
651 struct tgt_dev_sas_sata {
652 u64 sas_address;
653 u64 sas_address_parent;
654 u16 dev_info;
655 u8 phy_id;
656 u8 attached_phy_id;
657 u8 sas_transport_attached;
658 u8 pend_sas_rphy_add;
659 struct mpi3mr_hba_port *hba_port;
660 struct sas_rphy *rphy;
661 };
662
663 /**
664 * struct tgt_dev_pcie - PCIe device specific information cached
665 * from firmware given data
666 *
667 * @mdts: Maximum data transfer size
668 * @capb: Device capabilities
669 * @pgsz: Device page size
670 * @abort_to: Timeout for abort TM
671 * @reset_to: Timeout for Target/LUN reset TM
672 * @dev_info: Device information bits
673 */
674 struct tgt_dev_pcie {
675 u32 mdts;
676 u16 capb;
677 u8 pgsz;
678 u8 abort_to;
679 u8 reset_to;
680 u16 dev_info;
681 };
682
683 /**
684 * struct tgt_dev_vd - virtual device specific information
685 * cached from firmware given data
686 *
687 * @state: State of the VD
688 * @tg_qd_reduction: Queue Depth reduction in units of 10%
689 * @tg_id: VDs throttle group ID
690 * @high: High limit to turn on throttling in 512 byte blocks
691 * @low: Low limit to turn off throttling in 512 byte blocks
692 * @tg: Pointer to throttle group info
693 */
694 struct tgt_dev_vd {
695 u8 state;
696 u8 tg_qd_reduction;
697 u16 tg_id;
698 u32 tg_high;
699 u32 tg_low;
700 struct mpi3mr_throttle_group_info *tg;
701 };
702
703
704 /**
705 * union _form_spec_inf - union of device specific information
706 */
707 union _form_spec_inf {
708 struct tgt_dev_sas_sata sas_sata_inf;
709 struct tgt_dev_pcie pcie_inf;
710 struct tgt_dev_vd vd_inf;
711 };
712
713 enum mpi3mr_dev_state {
714 MPI3MR_DEV_CREATED = 1,
715 MPI3MR_DEV_REMOVE_HS_STARTED = 2,
716 MPI3MR_DEV_DELETED = 3,
717 };
718
719 /**
720 * struct mpi3mr_tgt_dev - target device data structure
721 *
722 * @list: List pointer
723 * @starget: Scsi_target pointer
724 * @dev_handle: FW device handle
725 * @parent_handle: FW parent device handle
726 * @slot: Slot number
727 * @encl_handle: FW enclosure handle
728 * @perst_id: FW assigned Persistent ID
729 * @devpg0_flag: Device Page0 flag
730 * @dev_type: SAS/SATA/PCIE device type
731 * @is_hidden: Should be exposed to upper layers or not
732 * @host_exposed: Already exposed to host or not
733 * @io_unit_port: IO Unit port ID
734 * @non_stl: Is this device not to be attached with SAS TL
735 * @io_throttle_enabled: I/O throttling needed or not
736 * @wslen: Write same max length
737 * @q_depth: Device specific Queue Depth
738 * @wwid: World wide ID
739 * @enclosure_logical_id: Enclosure logical identifier
740 * @dev_spec: Device type specific information
741 * @ref_count: Reference count
742 * @state: device state
743 */
744 struct mpi3mr_tgt_dev {
745 struct list_head list;
746 struct scsi_target *starget;
747 u16 dev_handle;
748 u16 parent_handle;
749 u16 slot;
750 u16 encl_handle;
751 u16 perst_id;
752 u16 devpg0_flag;
753 u8 dev_type;
754 u8 is_hidden;
755 u8 host_exposed;
756 u8 io_unit_port;
757 u8 non_stl;
758 u8 io_throttle_enabled;
759 u16 wslen;
760 u16 q_depth;
761 u64 wwid;
762 u64 enclosure_logical_id;
763 union _form_spec_inf dev_spec;
764 struct kref ref_count;
765 enum mpi3mr_dev_state state;
766 };
767
768 /**
769 * mpi3mr_tgtdev_get - k reference incrementor
770 * @s: Target device reference
771 *
772 * Increment target device reference count.
773 */
mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev * s)774 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
775 {
776 kref_get(&s->ref_count);
777 }
778
779 /**
780 * mpi3mr_free_tgtdev - target device memory dealloctor
781 * @r: k reference pointer of the target device
782 *
783 * Free target device memory when no reference.
784 */
mpi3mr_free_tgtdev(struct kref * r)785 static inline void mpi3mr_free_tgtdev(struct kref *r)
786 {
787 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
788 }
789
790 /**
791 * mpi3mr_tgtdev_put - k reference decrementor
792 * @s: Target device reference
793 *
794 * Decrement target device reference count.
795 */
mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev * s)796 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
797 {
798 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
799 }
800
801
802 /**
803 * struct mpi3mr_stgt_priv_data - SCSI target private structure
804 *
805 * @starget: Scsi_target pointer
806 * @dev_handle: FW device handle
807 * @perst_id: FW assigned Persistent ID
808 * @num_luns: Number of Logical Units
809 * @block_io: I/O blocked to the device or not
810 * @dev_removed: Device removed in the Firmware
811 * @dev_removedelay: Device is waiting to be removed in FW
812 * @dev_type: Device type
813 * @dev_nvme_dif: Device is NVMe DIF enabled
814 * @wslen: Write same max length
815 * @io_throttle_enabled: I/O throttling needed or not
816 * @io_divert: Flag indicates io divert is on or off for the dev
817 * @throttle_group: Pointer to throttle group info
818 * @tgt_dev: Internal target device pointer
819 * @pend_count: Counter to track pending I/Os during error
820 * handling
821 */
822 struct mpi3mr_stgt_priv_data {
823 struct scsi_target *starget;
824 u16 dev_handle;
825 u16 perst_id;
826 u32 num_luns;
827 atomic_t block_io;
828 u8 dev_removed;
829 u8 dev_removedelay;
830 u8 dev_type;
831 u8 dev_nvme_dif;
832 u16 wslen;
833 u8 io_throttle_enabled;
834 u8 io_divert;
835 struct mpi3mr_throttle_group_info *throttle_group;
836 struct mpi3mr_tgt_dev *tgt_dev;
837 u32 pend_count;
838 };
839
840 /**
841 * struct mpi3mr_stgt_priv_data - SCSI device private structure
842 *
843 * @tgt_priv_data: Scsi_target private data pointer
844 * @lun_id: LUN ID of the device
845 * @ncq_prio_enable: NCQ priority enable for SATA device
846 * @pend_count: Counter to track pending I/Os during error
847 * handling
848 * @wslen: Write same max length
849 */
850 struct mpi3mr_sdev_priv_data {
851 struct mpi3mr_stgt_priv_data *tgt_priv_data;
852 u32 lun_id;
853 u8 ncq_prio_enable;
854 u32 pend_count;
855 u16 wslen;
856 };
857
858 /**
859 * struct mpi3mr_drv_cmd - Internal command tracker
860 *
861 * @mutex: Command mutex
862 * @done: Completeor for wakeup
863 * @reply: Firmware reply for internal commands
864 * @sensebuf: Sensebuf for SCSI IO commands
865 * @iou_rc: IO Unit control reason code
866 * @state: Command State
867 * @dev_handle: Firmware handle for device specific commands
868 * @ioc_status: IOC status from the firmware
869 * @ioc_loginfo:IOC log info from the firmware
870 * @is_waiting: Is the command issued in block mode
871 * @is_sense: Is Sense data present
872 * @retry_count: Retry count for retriable commands
873 * @host_tag: Host tag used by the command
874 * @callback: Callback for non blocking commands
875 */
876 struct mpi3mr_drv_cmd {
877 struct mutex mutex;
878 struct completion done;
879 void *reply;
880 u8 *sensebuf;
881 u8 iou_rc;
882 u16 state;
883 u16 dev_handle;
884 u16 ioc_status;
885 u32 ioc_loginfo;
886 u8 is_waiting;
887 u8 is_sense;
888 u8 retry_count;
889 u16 host_tag;
890
891 void (*callback)(struct mpi3mr_ioc *mrioc,
892 struct mpi3mr_drv_cmd *drv_cmd);
893 };
894
895 /**
896 * union mpi3mr_trigger_data - Trigger data information
897 * @fault: Fault code
898 * @global: Global trigger data
899 * @element: element trigger data
900 */
901 union mpi3mr_trigger_data {
902 u16 fault;
903 u64 global;
904 union mpi3_driver2_trigger_element element;
905 };
906
907 /**
908 * struct trigger_event_data - store trigger related
909 * information.
910 *
911 * @trace_hdb: Trace diag buffer descriptor reference
912 * @fw_hdb: FW diag buffer descriptor reference
913 * @trigger_type: Trigger type
914 * @trigger_specific_data: Trigger specific data
915 * @snapdump: Snapdump enable or disable flag
916 */
917 struct trigger_event_data {
918 struct diag_buffer_desc *trace_hdb;
919 struct diag_buffer_desc *fw_hdb;
920 u8 trigger_type;
921 union mpi3mr_trigger_data trigger_specific_data;
922 bool snapdump;
923 };
924
925 /**
926 * struct diag_buffer_desc - memory descriptor structure to
927 * store virtual, dma addresses, size, buffer status for host
928 * diagnostic buffers.
929 *
930 * @type: Buffer type
931 * @trigger_data: Trigger data
932 * @trigger_type: Trigger type
933 * @status: Buffer status
934 * @size: Buffer size
935 * @addr: Virtual address
936 * @dma_addr: Buffer DMA address
937 */
938 struct diag_buffer_desc {
939 u8 type;
940 union mpi3mr_trigger_data trigger_data;
941 u8 trigger_type;
942 u8 status;
943 u32 size;
944 void *addr;
945 dma_addr_t dma_addr;
946 };
947
948 /**
949 * struct dma_memory_desc - memory descriptor structure to store
950 * virtual address, dma address and size for any generic dma
951 * memory allocations in the driver.
952 *
953 * @size: buffer size
954 * @addr: virtual address
955 * @dma_addr: dma address
956 */
957 struct dma_memory_desc {
958 u32 size;
959 void *addr;
960 dma_addr_t dma_addr;
961 };
962
963
964 /**
965 * struct chain_element - memory descriptor structure to store
966 * virtual and dma addresses for chain elements.
967 *
968 * @addr: virtual address
969 * @dma_addr: dma address
970 */
971 struct chain_element {
972 void *addr;
973 dma_addr_t dma_addr;
974 };
975
976 /**
977 * struct scmd_priv - SCSI command private data
978 *
979 * @host_tag: Host tag specific to operational queue
980 * @in_lld_scope: Command in LLD scope or not
981 * @meta_sg_valid: DIX command with meta data SGL or not
982 * @scmd: SCSI Command pointer
983 * @req_q_idx: Operational request queue index
984 * @chain_idx: Chain frame index
985 * @meta_chain_idx: Chain frame index of meta data SGL
986 * @mpi3mr_scsiio_req: MPI SCSI IO request
987 */
988 struct scmd_priv {
989 u16 host_tag;
990 u8 in_lld_scope;
991 u8 meta_sg_valid;
992 struct scsi_cmnd *scmd;
993 u16 req_q_idx;
994 int chain_idx;
995 int meta_chain_idx;
996 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
997 };
998
999 /**
1000 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
1001 * private data
1002 *
1003 * @list: List pointer
1004 * @pdev: PCI device pointer
1005 * @shost: Scsi_Host pointer
1006 * @id: Controller ID
1007 * @cpu_count: Number of online CPUs
1008 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
1009 * @name: Controller ASCII name
1010 * @driver_name: Driver ASCII name
1011 * @sysif_regs: System interface registers virtual address
1012 * @sysif_regs_phys: System interface registers physical address
1013 * @bars: PCI BARS
1014 * @dma_mask: DMA mask
1015 * @msix_count: Number of MSIX vectors used
1016 * @intr_enabled: Is interrupts enabled
1017 * @num_admin_req: Number of admin requests
1018 * @admin_req_q_sz: Admin request queue size
1019 * @admin_req_pi: Admin request queue producer index
1020 * @admin_req_ci: Admin request queue consumer index
1021 * @admin_req_base: Admin request queue base virtual address
1022 * @admin_req_dma: Admin request queue base dma address
1023 * @admin_req_lock: Admin queue access lock
1024 * @num_admin_replies: Number of admin replies
1025 * @admin_reply_q_sz: Admin reply queue size
1026 * @admin_reply_ci: Admin reply queue consumer index
1027 * @admin_reply_ephase:Admin reply queue expected phase
1028 * @admin_reply_base: Admin reply queue base virtual address
1029 * @admin_reply_dma: Admin reply queue base dma address
1030 * @admin_reply_q_in_use: Queue is handled by poll/ISR
1031 * @ready_timeout: Controller ready timeout
1032 * @intr_info: Interrupt cookie pointer
1033 * @intr_info_count: Number of interrupt cookies
1034 * @is_intr_info_set: Flag to indicate intr info is setup
1035 * @num_queues: Number of operational queues
1036 * @num_op_req_q: Number of operational request queues
1037 * @req_qinfo: Operational request queue info pointer
1038 * @num_op_reply_q: Number of operational reply queues
1039 * @op_reply_qinfo: Operational reply queue info pointer
1040 * @init_cmds: Command tracker for initialization commands
1041 * @cfg_cmds: Command tracker for configuration requests
1042 * @facts: Cached IOC facts data
1043 * @op_reply_desc_sz: Operational reply descriptor size
1044 * @num_reply_bufs: Number of reply buffers allocated
1045 * @reply_buf_pool: Reply buffer pool
1046 * @reply_buf: Reply buffer base virtual address
1047 * @reply_buf_dma: Reply buffer DMA address
1048 * @reply_buf_dma_max_address: Reply DMA address max limit
1049 * @reply_free_qsz: Reply free queue size
1050 * @reply_free_q_pool: Reply free queue pool
1051 * @reply_free_q: Reply free queue base virtual address
1052 * @reply_free_q_dma: Reply free queue base DMA address
1053 * @reply_free_queue_lock: Reply free queue lock
1054 * @reply_free_queue_host_index: Reply free queue host index
1055 * @num_sense_bufs: Number of sense buffers
1056 * @sense_buf_pool: Sense buffer pool
1057 * @sense_buf: Sense buffer base virtual address
1058 * @sense_buf_dma: Sense buffer base DMA address
1059 * @sense_buf_q_sz: Sense buffer queue size
1060 * @sense_buf_q_pool: Sense buffer queue pool
1061 * @sense_buf_q: Sense buffer queue virtual address
1062 * @sense_buf_q_dma: Sense buffer queue DMA address
1063 * @sbq_lock: Sense buffer queue lock
1064 * @sbq_host_index: Sense buffer queuehost index
1065 * @event_masks: Event mask bitmap
1066 * @fwevt_worker_thread: Firmware event worker thread
1067 * @fwevt_lock: Firmware event lock
1068 * @fwevt_list: Firmware event list
1069 * @watchdog_work_q_name: Fault watchdog worker thread name
1070 * @watchdog_work_q: Fault watchdog worker thread
1071 * @watchdog_work: Fault watchdog work
1072 * @watchdog_lock: Fault watchdog lock
1073 * @is_driver_loading: Is driver still loading
1074 * @scan_started: Async scan started
1075 * @scan_failed: Asycn scan failed
1076 * @stop_drv_processing: Stop all command processing
1077 * @device_refresh_on: Don't process the events until devices are refreshed
1078 * @max_host_ios: Maximum host I/O count
1079 * @max_sgl_entries: Max SGL entries per I/O
1080 * @chain_buf_count: Chain buffer count
1081 * @chain_buf_pool: Chain buffer pool
1082 * @chain_sgl_list: Chain SGL list
1083 * @chain_bitmap: Chain buffer allocator bitmap
1084 * @chain_buf_lock: Chain buffer list lock
1085 * @bsg_cmds: Command tracker for BSG command
1086 * @host_tm_cmds: Command tracker for task management commands
1087 * @dev_rmhs_cmds: Command tracker for device removal commands
1088 * @evtack_cmds: Command tracker for event ack commands
1089 * @devrem_bitmap: Device removal bitmap
1090 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap
1091 * @removepend_bitmap: Remove pending bitmap
1092 * @delayed_rmhs_list: Delayed device removal list
1093 * @evtack_cmds_bitmap: Event Ack bitmap
1094 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
1095 * @ts_update_counter: Timestamp update counter
1096 * @ts_update_interval: Timestamp update interval
1097 * @reset_in_progress: Reset in progress flag
1098 * @unrecoverable: Controller unrecoverable flag
1099 * @io_admin_reset_sync: Manage state of I/O ops during an admin reset process
1100 * @prev_reset_result: Result of previous reset
1101 * @reset_mutex: Controller reset mutex
1102 * @reset_waitq: Controller reset wait queue
1103 * @prepare_for_reset: Prepare for reset event received
1104 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
1105 * @prp_list_virt: NVMe encapsulated PRP list virtual base
1106 * @prp_list_dma: NVMe encapsulated PRP list DMA
1107 * @prp_sz: NVME encapsulated PRP list size
1108 * @diagsave_timeout: Diagnostic information save timeout
1109 * @logging_level: Controller debug logging level
1110 * @flush_io_count: I/O count to flush after reset
1111 * @current_event: Firmware event currently in process
1112 * @driver_info: Driver, Kernel, OS information to firmware
1113 * @change_count: Topology change count
1114 * @pel_enabled: Persistent Event Log(PEL) enabled or not
1115 * @pel_abort_requested: PEL abort is requested or not
1116 * @pel_class: PEL Class identifier
1117 * @pel_locale: PEL Locale identifier
1118 * @pel_cmds: Command tracker for PEL wait command
1119 * @pel_abort_cmd: Command tracker for PEL abort command
1120 * @pel_newest_seqnum: Newest PEL sequenece number
1121 * @pel_seqnum_virt: PEL sequence number virtual address
1122 * @pel_seqnum_dma: PEL sequence number DMA address
1123 * @pel_seqnum_sz: PEL sequenece number size
1124 * @op_reply_q_offset: Operational reply queue offset with MSIx
1125 * @default_qcount: Total Default queues
1126 * @active_poll_qcount: Currently active poll queue count
1127 * @requested_poll_qcount: User requested poll queue count
1128 * @bsg_dev: BSG device structure
1129 * @bsg_queue: Request queue for BSG device
1130 * @stop_bsgs: Stop BSG request flag
1131 * @logdata_buf: Circular buffer to store log data entries
1132 * @logdata_buf_idx: Index of entry in buffer to store
1133 * @logdata_entry_sz: log data entry size
1134 * @pend_large_data_sz: Counter to track pending large data
1135 * @io_throttle_data_length: I/O size to track in 512b blocks
1136 * @io_throttle_high: I/O size to start throttle in 512b blocks
1137 * @io_throttle_low: I/O size to stop throttle in 512b blocks
1138 * @num_io_throttle_group: Maximum number of throttle groups
1139 * @throttle_groups: Pointer to throttle group info structures
1140 * @sas_transport_enabled: SAS transport enabled or not
1141 * @scsi_device_channel: Channel ID for SCSI devices
1142 * @transport_cmds: Command tracker for SAS transport commands
1143 * @sas_hba: SAS node for the controller
1144 * @sas_expander_list: SAS node list of expanders
1145 * @sas_node_lock: Lock to protect SAS node list
1146 * @hba_port_table_list: List of HBA Ports
1147 * @enclosure_list: List of Enclosure objects
1148 * @diag_buffers: Host diagnostic buffers
1149 * @driver_pg2: Driver page 2 pointer
1150 * @reply_trigger_present: Reply trigger present flag
1151 * @event_trigger_present: Event trigger present flag
1152 * @scsisense_trigger_present: Scsi sense trigger present flag
1153 * @ioctl_dma_pool: DMA pool for IOCTL data buffers
1154 * @ioctl_sge: DMA buffer descriptors for IOCTL data
1155 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain
1156 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response
1157 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not
1158 * @trace_release_trigger_active: Trace trigger active flag
1159 * @fw_release_trigger_active: Fw release trigger active flag
1160 * @snapdump_trigger_active: Snapdump trigger active flag
1161 * @pci_err_recovery: PCI error recovery in progress
1162 * @block_on_pci_err: Block IO during PCI error recovery
1163 * @reply_qfull_count: Occurences of reply queue full avoidance kicking-in
1164 * @prevent_reply_qfull: Enable reply queue prevention
1165 */
1166 struct mpi3mr_ioc {
1167 struct list_head list;
1168 struct pci_dev *pdev;
1169 struct Scsi_Host *shost;
1170 u8 id;
1171 int cpu_count;
1172 bool enable_segqueue;
1173 u32 irqpoll_sleep;
1174
1175 char name[MPI3MR_NAME_LENGTH];
1176 char driver_name[MPI3MR_NAME_LENGTH];
1177
1178 volatile struct mpi3_sysif_registers __iomem *sysif_regs;
1179 resource_size_t sysif_regs_phys;
1180 int bars;
1181 u64 dma_mask;
1182
1183 u16 msix_count;
1184 u8 intr_enabled;
1185
1186 u16 num_admin_req;
1187 u32 admin_req_q_sz;
1188 u16 admin_req_pi;
1189 u16 admin_req_ci;
1190 void *admin_req_base;
1191 dma_addr_t admin_req_dma;
1192 spinlock_t admin_req_lock;
1193
1194 u16 num_admin_replies;
1195 u32 admin_reply_q_sz;
1196 u16 admin_reply_ci;
1197 u8 admin_reply_ephase;
1198 void *admin_reply_base;
1199 dma_addr_t admin_reply_dma;
1200 atomic_t admin_reply_q_in_use;
1201
1202 u32 ready_timeout;
1203
1204 struct mpi3mr_intr_info *intr_info;
1205 u16 intr_info_count;
1206 bool is_intr_info_set;
1207
1208 u16 num_queues;
1209 u16 num_op_req_q;
1210 struct op_req_qinfo *req_qinfo;
1211
1212 u16 num_op_reply_q;
1213 struct op_reply_qinfo *op_reply_qinfo;
1214
1215 struct mpi3mr_drv_cmd init_cmds;
1216 struct mpi3mr_drv_cmd cfg_cmds;
1217 struct mpi3mr_ioc_facts facts;
1218 u16 op_reply_desc_sz;
1219
1220 u32 num_reply_bufs;
1221 struct dma_pool *reply_buf_pool;
1222 u8 *reply_buf;
1223 dma_addr_t reply_buf_dma;
1224 dma_addr_t reply_buf_dma_max_address;
1225
1226 u16 reply_free_qsz;
1227 u16 reply_sz;
1228 struct dma_pool *reply_free_q_pool;
1229 __le64 *reply_free_q;
1230 dma_addr_t reply_free_q_dma;
1231 spinlock_t reply_free_queue_lock;
1232 u32 reply_free_queue_host_index;
1233
1234 u32 num_sense_bufs;
1235 struct dma_pool *sense_buf_pool;
1236 u8 *sense_buf;
1237 dma_addr_t sense_buf_dma;
1238
1239 u16 sense_buf_q_sz;
1240 struct dma_pool *sense_buf_q_pool;
1241 __le64 *sense_buf_q;
1242 dma_addr_t sense_buf_q_dma;
1243 spinlock_t sbq_lock;
1244 u32 sbq_host_index;
1245 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
1246
1247 struct workqueue_struct *fwevt_worker_thread;
1248 spinlock_t fwevt_lock;
1249 struct list_head fwevt_list;
1250
1251 char watchdog_work_q_name[50];
1252 struct workqueue_struct *watchdog_work_q;
1253 struct delayed_work watchdog_work;
1254 spinlock_t watchdog_lock;
1255
1256 u8 is_driver_loading;
1257 u8 scan_started;
1258 u16 scan_failed;
1259 u8 stop_drv_processing;
1260 u8 device_refresh_on;
1261
1262 u16 max_host_ios;
1263 spinlock_t tgtdev_lock;
1264 struct list_head tgtdev_list;
1265 u16 max_sgl_entries;
1266
1267 u32 chain_buf_count;
1268 struct dma_pool *chain_buf_pool;
1269 struct chain_element *chain_sgl_list;
1270 unsigned long *chain_bitmap;
1271 spinlock_t chain_buf_lock;
1272
1273 struct mpi3mr_drv_cmd bsg_cmds;
1274 struct mpi3mr_drv_cmd host_tm_cmds;
1275 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
1276 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
1277 unsigned long *devrem_bitmap;
1278 u16 dev_handle_bitmap_bits;
1279 unsigned long *removepend_bitmap;
1280 struct list_head delayed_rmhs_list;
1281 unsigned long *evtack_cmds_bitmap;
1282 struct list_head delayed_evtack_cmds_list;
1283
1284 u16 ts_update_counter;
1285 u16 ts_update_interval;
1286 u8 reset_in_progress;
1287 u8 unrecoverable;
1288 u8 io_admin_reset_sync;
1289 int prev_reset_result;
1290 struct mutex reset_mutex;
1291 wait_queue_head_t reset_waitq;
1292
1293 u8 prepare_for_reset;
1294 u16 prepare_for_reset_timeout_counter;
1295
1296 void *prp_list_virt;
1297 dma_addr_t prp_list_dma;
1298 u32 prp_sz;
1299
1300 u16 diagsave_timeout;
1301 int logging_level;
1302 u16 flush_io_count;
1303
1304 struct mpi3mr_fwevt *current_event;
1305 struct mpi3_driver_info_layout driver_info;
1306 u16 change_count;
1307
1308 u8 pel_enabled;
1309 u8 pel_abort_requested;
1310 u8 pel_class;
1311 u16 pel_locale;
1312 struct mpi3mr_drv_cmd pel_cmds;
1313 struct mpi3mr_drv_cmd pel_abort_cmd;
1314
1315 u32 pel_newest_seqnum;
1316 void *pel_seqnum_virt;
1317 dma_addr_t pel_seqnum_dma;
1318 u32 pel_seqnum_sz;
1319
1320 u16 op_reply_q_offset;
1321 u16 default_qcount;
1322 u16 active_poll_qcount;
1323 u16 requested_poll_qcount;
1324
1325 struct device bsg_dev;
1326 struct request_queue *bsg_queue;
1327 u8 stop_bsgs;
1328 u8 *logdata_buf;
1329 u16 logdata_buf_idx;
1330 u16 logdata_entry_sz;
1331
1332 atomic_t pend_large_data_sz;
1333 u32 io_throttle_data_length;
1334 u32 io_throttle_high;
1335 u32 io_throttle_low;
1336 u16 num_io_throttle_group;
1337 struct mpi3mr_throttle_group_info *throttle_groups;
1338
1339 u8 sas_transport_enabled;
1340 u8 scsi_device_channel;
1341 struct mpi3mr_drv_cmd transport_cmds;
1342 struct mpi3mr_sas_node sas_hba;
1343 struct list_head sas_expander_list;
1344 spinlock_t sas_node_lock;
1345 struct list_head hba_port_table_list;
1346 struct list_head enclosure_list;
1347
1348 struct dma_pool *ioctl_dma_pool;
1349 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE];
1350 struct dma_memory_desc ioctl_chain_sge;
1351 struct dma_memory_desc ioctl_resp_sge;
1352 bool ioctl_sges_allocated;
1353 bool reply_trigger_present;
1354 bool event_trigger_present;
1355 bool scsisense_trigger_present;
1356 struct diag_buffer_desc diag_buffers[MPI3MR_MAX_NUM_HDB];
1357 struct mpi3_driver_page2 *driver_pg2;
1358 spinlock_t trigger_lock;
1359 bool snapdump_trigger_active;
1360 bool trace_release_trigger_active;
1361 bool fw_release_trigger_active;
1362 bool pci_err_recovery;
1363 bool block_on_pci_err;
1364 atomic_t reply_qfull_count;
1365 bool prevent_reply_qfull;
1366 };
1367
1368 /**
1369 * struct mpi3mr_fwevt - Firmware event structure.
1370 *
1371 * @list: list head
1372 * @work: Work structure
1373 * @mrioc: Adapter instance reference
1374 * @event_id: MPI3 firmware event ID
1375 * @send_ack: Event acknowledgment required or not
1376 * @process_evt: Bottomhalf processing required or not
1377 * @evt_ctx: Event context to send in Ack
1378 * @event_data_size: size of the event data in bytes
1379 * @pending_at_sml: waiting for device add/remove API to complete
1380 * @discard: discard this event
1381 * @ref_count: kref count
1382 * @event_data: Actual MPI3 event data
1383 */
1384 struct mpi3mr_fwevt {
1385 struct list_head list;
1386 struct work_struct work;
1387 struct mpi3mr_ioc *mrioc;
1388 u16 event_id;
1389 bool send_ack;
1390 bool process_evt;
1391 u32 evt_ctx;
1392 u16 event_data_size;
1393 bool pending_at_sml;
1394 bool discard;
1395 struct kref ref_count;
1396 char event_data[] __aligned(4);
1397 };
1398
1399
1400 /**
1401 * struct delayed_dev_rmhs_node - Delayed device removal node
1402 *
1403 * @list: list head
1404 * @handle: Device handle
1405 * @iou_rc: IO Unit Control Reason Code
1406 */
1407 struct delayed_dev_rmhs_node {
1408 struct list_head list;
1409 u16 handle;
1410 u8 iou_rc;
1411 };
1412
1413 /**
1414 * struct delayed_evt_ack_node - Delayed event ack node
1415 * @list: list head
1416 * @event: MPI3 event ID
1417 * @event_ctx: event context
1418 */
1419 struct delayed_evt_ack_node {
1420 struct list_head list;
1421 u8 event;
1422 u32 event_ctx;
1423 };
1424
1425 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
1426 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
1427 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
1428 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
1429 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
1430 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
1431 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1432 u16 admin_req_sz, u8 ignore_reset);
1433 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1434 struct op_req_qinfo *opreqq, u8 *req);
1435 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
1436 dma_addr_t dma_addr);
1437 void mpi3mr_build_zero_len_sge(void *paddr);
1438 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
1439 dma_addr_t phys_addr);
1440 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
1441 dma_addr_t phys_addr);
1442 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
1443 u64 sense_buf_dma);
1444
1445 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
1446 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
1447 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
1448 struct mpi3_event_notification_reply *event_reply);
1449 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
1450 struct mpi3_default_reply_descriptor *reply_desc,
1451 u64 *reply_dma, u16 qidx);
1452 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
1453 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
1454
1455 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
1456 u16 reset_reason, u8 snapdump);
1457 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
1458 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
1459
1460 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
1461 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
1462 u32 event_ctx);
1463
1464 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
1465 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
1466 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
1467 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
1468 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
1469 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1470 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
1471 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1472 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
1473 struct op_reply_qinfo *op_reply_q);
1474 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1475 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);
1476 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);
1477 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
1478 u16 handle, uint lun, u16 htag, ulong timeout,
1479 struct mpi3mr_drv_cmd *drv_cmd,
1480 u8 *resp_code, struct scsi_cmnd *scmd);
1481 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
1482 struct mpi3mr_ioc *mrioc, u16 handle);
1483 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
1484 struct mpi3mr_drv_cmd *drv_cmd);
1485 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
1486 struct mpi3mr_drv_cmd *drv_cmd);
1487 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data,
1488 u16 event_data_size);
1489 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle(
1490 struct mpi3mr_ioc *mrioc, u16 handle);
1491 extern const struct attribute_group *mpi3mr_host_groups[];
1492 extern const struct attribute_group *mpi3mr_dev_groups[];
1493
1494 extern struct sas_function_template mpi3mr_transport_functions;
1495 extern struct scsi_transport_template *mpi3mr_transport_template;
1496
1497 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1498 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec);
1499 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1500 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
1501 u32 form_spec);
1502 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1503 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
1504 u32 form_spec);
1505 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1506 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
1507 u32 form_spec);
1508 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1509 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
1510 u32 form_spec);
1511 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1512 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
1513 u32 form_spec);
1514 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
1515 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz);
1516 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1517 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1518 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1519 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1520 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
1521 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz);
1522 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
1523 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type);
1524
1525 u8 mpi3mr_is_expander_device(u16 device_info);
1526 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle);
1527 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address,
1528 struct mpi3mr_hba_port *hba_port);
1529 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc
1530 *mrioc, u16 handle);
1531 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc,
1532 u8 port_id);
1533 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc);
1534 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc);
1535 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc,
1536 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate,
1537 struct mpi3mr_hba_port *hba_port);
1538 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc,
1539 struct mpi3mr_tgt_dev *tgtdev);
1540 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc,
1541 struct mpi3mr_tgt_dev *tgtdev);
1542 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc,
1543 struct mpi3mr_tgt_dev *tgtdev);
1544 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy(
1545 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy);
1546 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc,
1547 bool device_add);
1548 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc);
1549 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc);
1550 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc);
1551 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc);
1552 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc);
1553 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc);
1554 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc);
1555 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc,
1556 struct mpi3mr_sas_node *sas_expander);
1557 void mpi3mr_alloc_diag_bufs(struct mpi3mr_ioc *mrioc);
1558 int mpi3mr_post_diag_bufs(struct mpi3mr_ioc *mrioc);
1559 int mpi3mr_issue_diag_buf_release(struct mpi3mr_ioc *mrioc,
1560 struct diag_buffer_desc *diag_buffer);
1561 void mpi3mr_release_diag_bufs(struct mpi3mr_ioc *mrioc, u8 skip_rel_action);
1562 void mpi3mr_set_trigger_data_in_hdb(struct diag_buffer_desc *hdb,
1563 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1564 int mpi3mr_refresh_trigger(struct mpi3mr_ioc *mrioc, u8 page_type);
1565 struct diag_buffer_desc *mpi3mr_diag_buffer_for_type(struct mpi3mr_ioc *mrioc,
1566 u8 buf_type);
1567 int mpi3mr_issue_diag_buf_post(struct mpi3mr_ioc *mrioc,
1568 struct diag_buffer_desc *diag_buffer);
1569 void mpi3mr_set_trigger_data_in_all_hdb(struct mpi3mr_ioc *mrioc,
1570 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1571 void mpi3mr_reply_trigger(struct mpi3mr_ioc *mrioc, u16 iocstatus,
1572 u32 iocloginfo);
1573 void mpi3mr_hdb_trigger_data_event(struct mpi3mr_ioc *mrioc,
1574 struct trigger_event_data *event_data);
1575 void mpi3mr_scsisense_trigger(struct mpi3mr_ioc *mrioc, u8 senseky, u8 asc,
1576 u8 ascq);
1577 void mpi3mr_event_trigger(struct mpi3mr_ioc *mrioc, u8 event);
1578 void mpi3mr_global_trigger(struct mpi3mr_ioc *mrioc, u64 trigger_data);
1579 void mpi3mr_hdbstatuschg_evt_th(struct mpi3mr_ioc *mrioc,
1580 struct mpi3_event_notification_reply *event_reply);
1581 #endif /*MPI3MR_H_INCLUDED*/
1582