1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/G2L Pin Control and GPIO driver core
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/seq_file.h>
21 #include <linux/spinlock.h>
22
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28
29 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
30 #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
31 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
32
33 #include "../core.h"
34 #include "../pinconf.h"
35 #include "../pinmux.h"
36
37 #define DRV_NAME "pinctrl-rzg2l"
38
39 /*
40 * Use 16 lower bits [15:0] for pin identifier
41 * Use 16 higher bits [31:16] for pin mux function
42 */
43 #define MUX_PIN_ID_MASK GENMASK(15, 0)
44 #define MUX_FUNC_MASK GENMASK(31, 16)
45
46 /* PIN capabilities */
47 #define PIN_CFG_IOLH_A BIT(0)
48 #define PIN_CFG_IOLH_B BIT(1)
49 #define PIN_CFG_SR BIT(2)
50 #define PIN_CFG_IEN BIT(3)
51 #define PIN_CFG_PUPD BIT(4)
52 #define PIN_CFG_IO_VMC_SD0 BIT(5)
53 #define PIN_CFG_IO_VMC_SD1 BIT(6)
54 #define PIN_CFG_IO_VMC_QSPI BIT(7)
55 #define PIN_CFG_IO_VMC_ETH0 BIT(8)
56 #define PIN_CFG_IO_VMC_ETH1 BIT(9)
57 #define PIN_CFG_NF BIT(10) /* Digital noise filter */
58 #define PIN_CFG_IOLH_C BIT(11)
59 #define PIN_CFG_SOFT_PS BIT(12)
60 #define PIN_CFG_OEN BIT(13)
61 #define PIN_CFG_NOGPIO_INT BIT(14)
62 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
63 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
64 #define PIN_CFG_ELC BIT(17)
65 #define PIN_CFG_IOLH_RZV2H BIT(18)
66
67 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
68 #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
69
70 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
71 (PIN_CFG_IOLH_##group | \
72 PIN_CFG_PUPD | \
73 PIN_CFG_NF)
74
75 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
76 PIN_CFG_SR)
77
78 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
79 PIN_CFG_SOFT_PS)
80
81 #define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \
82 PIN_CFG_NOD | \
83 PIN_CFG_SR | \
84 PIN_CFG_SMT)
85
86 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
87
88 #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
89 #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
90 #define PIN_CFG_MASK GENMASK_ULL(31, 0)
91
92 /*
93 * m indicates the bitmap of supported pins, a is the register index
94 * and f is pin configuration capabilities supported.
95 */
96 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
97 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
98 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
99 #define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \
100 (RZG2L_VARIABLE_CFG | \
101 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))
102
103 /*
104 * n indicates number of pins in the port, a is the register index
105 * and f is pin configuration capabilities supported.
106 */
107 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
108 #define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \
109 RZG2L_GPIO_PORT_PACK(n, a, 0))
110
111 #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
112 #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
113 /*
114 * p is the register index while referencing to SR/IEN/IOLH/FILxx
115 * registers, b is the register bits (b * 8) and f is the pin
116 * configuration capabilities supported.
117 */
118 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
119 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
120 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
121 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
122
123 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \
124 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
125 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
126
127 #define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)
128 #define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)
129 #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \
130 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
131 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
132 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
133
134 #define P(off) (0x0000 + (off))
135 #define PM(off) (0x0100 + (off) * 2)
136 #define PMC(off) (0x0200 + (off))
137 #define PFC(off) (0x0400 + (off) * 4)
138 #define PIN(off) (0x0800 + (off))
139 #define IOLH(off) (0x1000 + (off) * 8)
140 #define SR(off) (0x1400 + (off) * 8)
141 #define IEN(off) (0x1800 + (off) * 8)
142 #define PUPD(off) (0x1C00 + (off) * 8)
143 #define ISEL(off) (0x2C00 + (off) * 8)
144 #define NOD(off) (0x3000 + (off) * 8)
145 #define SMT(off) (0x3400 + (off) * 8)
146 #define SD_CH(off, ch) ((off) + (ch) * 4)
147 #define ETH_POC(off, ch) ((off) + (ch) * 4)
148 #define QSPI (0x3008)
149 #define ETH_MODE (0x3018)
150 #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
151
152 #define PVDD_2500 2 /* I/O domain voltage 2.5V */
153 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
154 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
155
156 #define PWPR_B0WI BIT(7) /* Bit Write Disable */
157 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
158 #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */
159 #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
160
161 #define PM_MASK 0x03
162 #define PFC_MASK 0x0f
163 #define IEN_MASK 0x01
164 #define IOLH_MASK 0x03
165 #define SR_MASK 0x01
166 #define PUPD_MASK 0x03
167 #define NOD_MASK 0x01
168 #define SMT_MASK 0x01
169
170 #define PM_INPUT 0x1
171 #define PM_OUTPUT 0x2
172
173 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
174 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
175
176 #define RZG2L_TINT_MAX_INTERRUPT 32
177 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
178
179 /* Custom pinconf parameters */
180 #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)
181
182 static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {
183 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
184 };
185
186 #ifdef CONFIG_DEBUG_FS
187 static const struct pin_config_item renesas_rzv2h_conf_items[] = {
188 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
189 };
190 #endif
191
192 /* Read/write 8 bits register */
193 #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
194 do { \
195 if (_read) \
196 _val = readb(_addr); \
197 else \
198 writeb(_val, _addr); \
199 } while (0)
200
201 /* Read/write 16 bits register */
202 #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \
203 do { \
204 if (_read) \
205 _val = readw(_addr); \
206 else \
207 writew(_val, _addr); \
208 } while (0)
209
210 /* Read/write 32 bits register */
211 #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \
212 do { \
213 if (_read) \
214 _val = readl(_addr); \
215 else \
216 writel(_val, _addr); \
217 } while (0)
218
219 /**
220 * struct rzg2l_register_offsets - specific register offsets
221 * @pwpr: PWPR register offset
222 * @sd_ch: SD_CH register offset
223 * @eth_poc: ETH_POC register offset
224 */
225 struct rzg2l_register_offsets {
226 u16 pwpr;
227 u16 sd_ch;
228 u16 eth_poc;
229 };
230
231 /**
232 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
233 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
234 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source
235 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
236 * @RZG2L_IOLH_IDX_MAX: maximum index
237 */
238 enum rzg2l_iolh_index {
239 RZG2L_IOLH_IDX_1V8 = 0,
240 RZG2L_IOLH_IDX_2V5 = 4,
241 RZG2L_IOLH_IDX_3V3 = 8,
242 RZG2L_IOLH_IDX_MAX = 12,
243 };
244
245 /* Maximum number of driver strength entries per power source. */
246 #define RZG2L_IOLH_MAX_DS_ENTRIES (4)
247
248 /**
249 * struct rzg2l_hwcfg - hardware configuration data structure
250 * @regs: hardware specific register offsets
251 * @iolh_groupa_ua: IOLH group A uA specific values
252 * @iolh_groupb_ua: IOLH group B uA specific values
253 * @iolh_groupc_ua: IOLH group C uA specific values
254 * @iolh_groupb_oi: IOLH group B output impedance specific values
255 * @tint_start_index: the start index for the TINT interrupts
256 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
257 * @func_base: base number for port function (see register PFC)
258 * @oen_max_pin: the maximum pin number supporting output enable
259 * @oen_max_port: the maximum port number supporting output enable
260 */
261 struct rzg2l_hwcfg {
262 const struct rzg2l_register_offsets regs;
263 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
264 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
265 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
266 u16 iolh_groupb_oi[4];
267 u16 tint_start_index;
268 bool drive_strength_ua;
269 u8 func_base;
270 u8 oen_max_pin;
271 u8 oen_max_port;
272 };
273
274 struct rzg2l_dedicated_configs {
275 const char *name;
276 u64 config;
277 };
278
279 struct rzg2l_pinctrl;
280
281 struct rzg2l_pinctrl_data {
282 const char * const *port_pins;
283 const u64 *port_pin_configs;
284 unsigned int n_ports;
285 const struct rzg2l_dedicated_configs *dedicated_pins;
286 unsigned int n_port_pins;
287 unsigned int n_dedicated_pins;
288 const struct rzg2l_hwcfg *hwcfg;
289 const u64 *variable_pin_cfg;
290 unsigned int n_variable_pin_cfg;
291 unsigned int num_custom_params;
292 const struct pinconf_generic_params *custom_params;
293 #ifdef CONFIG_DEBUG_FS
294 const struct pin_config_item *custom_conf_items;
295 #endif
296 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
297 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
298 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
299 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
300 int (*hw_to_bias_param)(unsigned int val);
301 int (*bias_param_to_hw)(enum pin_config_param param);
302 };
303
304 /**
305 * struct rzg2l_pinctrl_pin_settings - pin data
306 * @power_source: power source
307 * @drive_strength_ua: drive strength (in micro amps)
308 */
309 struct rzg2l_pinctrl_pin_settings {
310 u16 power_source;
311 u16 drive_strength_ua;
312 };
313
314 /**
315 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)
316 * @p: P registers cache
317 * @pm: PM registers cache
318 * @pmc: PMC registers cache
319 * @pfc: PFC registers cache
320 * @iolh: IOLH registers cache
321 * @ien: IEN registers cache
322 * @sd_ch: SD_CH registers cache
323 * @eth_poc: ET_POC registers cache
324 * @eth_mode: ETH_MODE register cache
325 * @qspi: QSPI registers cache
326 */
327 struct rzg2l_pinctrl_reg_cache {
328 u8 *p;
329 u16 *pm;
330 u8 *pmc;
331 u32 *pfc;
332 u32 *iolh[2];
333 u32 *ien[2];
334 u8 sd_ch[2];
335 u8 eth_poc[2];
336 u8 eth_mode;
337 u8 qspi;
338 };
339
340 struct rzg2l_pinctrl {
341 struct pinctrl_dev *pctl;
342 struct pinctrl_desc desc;
343 struct pinctrl_pin_desc *pins;
344
345 const struct rzg2l_pinctrl_data *data;
346 void __iomem *base;
347 struct device *dev;
348
349 struct clk *clk;
350
351 struct gpio_chip gpio_chip;
352 struct pinctrl_gpio_range gpio_range;
353 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
354 spinlock_t bitmap_lock; /* protect tint_slot bitmap */
355 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT];
356
357 spinlock_t lock; /* lock read/write registers */
358 struct mutex mutex; /* serialize adding groups and functions */
359
360 struct rzg2l_pinctrl_pin_settings *settings;
361 struct rzg2l_pinctrl_reg_cache *cache;
362 struct rzg2l_pinctrl_reg_cache *dedicated_cache;
363 atomic_t wakeup_path;
364 };
365
366 static const u16 available_ps[] = { 1800, 2500, 3300 };
367
rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl * pctrl,u64 pincfg,unsigned int port,u8 pin)368 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
369 u64 pincfg,
370 unsigned int port,
371 u8 pin)
372 {
373 unsigned int i;
374
375 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {
376 u64 cfg = pctrl->data->variable_pin_cfg[i];
377
378 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
379 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
380 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);
381 }
382
383 return 0;
384 }
385
386 static const u64 r9a09g047_variable_pin_cfg[] = {
387 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
388 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
389 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),
390 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),
391 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),
392 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
393 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
394 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
395 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
396 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
397 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
398 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),
399 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),
400 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
401 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
402 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
403 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
404 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
405 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
406 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
407 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
408 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
409 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),
410 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),
411 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),
412 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
413 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
414 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
415 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
416 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
417 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
418 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),
419 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
420 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
421 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
422 };
423
424 static const u64 r9a09g057_variable_pin_cfg[] = {
425 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
426 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
427 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
428 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
429 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
430 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
431 };
432
433 #ifdef CONFIG_RISCV
434 static const u64 r9a07g043f_variable_pin_cfg[] = {
435 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
436 PIN_CFG_NF |
437 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
438 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
439 PIN_CFG_NF |
440 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
441 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
442 PIN_CFG_NF |
443 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
444 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
445 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
446 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
447 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
448 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
449 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
450 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
451 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
452 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
453 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
454 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
455 PIN_CFG_NOGPIO_INT),
456 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
457 PIN_CFG_NOGPIO_INT),
458 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
459 PIN_CFG_NOGPIO_INT),
460 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
461 PIN_CFG_NOGPIO_INT),
462 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
463 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
464 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
465 PIN_CFG_NOGPIO_INT),
466 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
467 PIN_CFG_NOGPIO_INT),
468 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
469 PIN_CFG_NOGPIO_INT),
470 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
471 PIN_CFG_NOGPIO_INT),
472 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
473 PIN_CFG_NF |
474 PIN_CFG_NOGPIO_INT),
475 };
476 #endif
477
rzg2l_pmc_writeb(struct rzg2l_pinctrl * pctrl,u8 val,u16 offset)478 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
479 {
480 writeb(val, pctrl->base + offset);
481 }
482
rzv2h_pmc_writeb(struct rzg2l_pinctrl * pctrl,u8 val,u16 offset)483 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
484 {
485 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
486 u8 pwpr;
487
488 pwpr = readb(pctrl->base + regs->pwpr);
489 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr);
490 writeb(val, pctrl->base + offset);
491 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
492 }
493
rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl * pctrl,u8 pin,u8 off,u8 func)494 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
495 u8 pin, u8 off, u8 func)
496 {
497 unsigned long flags;
498 u32 reg;
499
500 spin_lock_irqsave(&pctrl->lock, flags);
501
502 /* Set pin to 'Non-use (Hi-Z input protection)' */
503 reg = readw(pctrl->base + PM(off));
504 reg &= ~(PM_MASK << (pin * 2));
505 writew(reg, pctrl->base + PM(off));
506
507 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
508
509 /* Temporarily switch to GPIO mode with PMC register */
510 reg = readb(pctrl->base + PMC(off));
511 writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
512
513 /* Select Pin function mode with PFC register */
514 reg = readl(pctrl->base + PFC(off));
515 reg &= ~(PFC_MASK << (pin * 4));
516 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
517
518 /* Switch to Peripheral pin function with PMC register */
519 reg = readb(pctrl->base + PMC(off));
520 writeb(reg | BIT(pin), pctrl->base + PMC(off));
521
522 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
523
524 spin_unlock_irqrestore(&pctrl->lock, flags);
525 };
526
rzg2l_pinctrl_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)527 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
528 unsigned int func_selector,
529 unsigned int group_selector)
530 {
531 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
532 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
533 struct function_desc *func;
534 unsigned int i, *psel_val;
535 struct group_desc *group;
536 const unsigned int *pins;
537
538 func = pinmux_generic_get_function(pctldev, func_selector);
539 if (!func)
540 return -EINVAL;
541 group = pinctrl_generic_get_group(pctldev, group_selector);
542 if (!group)
543 return -EINVAL;
544
545 psel_val = func->data;
546 pins = group->grp.pins;
547
548 for (i = 0; i < group->grp.npins; i++) {
549 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;
550 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
551 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
552
553 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
554 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
555
556 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);
557 }
558
559 return 0;
560 };
561
rzg2l_map_add_config(struct pinctrl_map * map,const char * group_or_pin,enum pinctrl_map_type type,unsigned long * configs,unsigned int num_configs)562 static int rzg2l_map_add_config(struct pinctrl_map *map,
563 const char *group_or_pin,
564 enum pinctrl_map_type type,
565 unsigned long *configs,
566 unsigned int num_configs)
567 {
568 unsigned long *cfgs;
569
570 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
571 if (!cfgs)
572 return -ENOMEM;
573
574 map->type = type;
575 map->data.configs.group_or_pin = group_or_pin;
576 map->data.configs.configs = cfgs;
577 map->data.configs.num_configs = num_configs;
578
579 return 0;
580 }
581
rzg2l_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct device_node * parent,struct pinctrl_map ** map,unsigned int * num_maps,unsigned int * index)582 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
583 struct device_node *np,
584 struct device_node *parent,
585 struct pinctrl_map **map,
586 unsigned int *num_maps,
587 unsigned int *index)
588 {
589 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
590 struct pinctrl_map *maps = *map;
591 unsigned int nmaps = *num_maps;
592 unsigned long *configs = NULL;
593 unsigned int *pins, *psel_val;
594 unsigned int num_pinmux = 0;
595 unsigned int idx = *index;
596 unsigned int num_pins, i;
597 unsigned int num_configs;
598 struct property *pinmux;
599 struct property *prop;
600 int ret, gsel, fsel;
601 const char **pin_fn;
602 const char *name;
603 const char *pin;
604
605 pinmux = of_find_property(np, "pinmux", NULL);
606 if (pinmux)
607 num_pinmux = pinmux->length / sizeof(u32);
608
609 ret = of_property_count_strings(np, "pins");
610 if (ret == -EINVAL) {
611 num_pins = 0;
612 } else if (ret < 0) {
613 dev_err(pctrl->dev, "Invalid pins list in DT\n");
614 return ret;
615 } else {
616 num_pins = ret;
617 }
618
619 if (!num_pinmux && !num_pins)
620 return 0;
621
622 if (num_pinmux && num_pins) {
623 dev_err(pctrl->dev,
624 "DT node must contain either a pinmux or pins and not both\n");
625 return -EINVAL;
626 }
627
628 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
629 if (ret < 0)
630 return ret;
631
632 if (num_pins && !num_configs) {
633 dev_err(pctrl->dev, "DT node must contain a config\n");
634 ret = -ENODEV;
635 goto done;
636 }
637
638 if (num_pinmux) {
639 nmaps += 1;
640 if (num_configs)
641 nmaps += 1;
642 }
643
644 if (num_pins)
645 nmaps += num_pins;
646
647 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
648 if (!maps) {
649 ret = -ENOMEM;
650 goto done;
651 }
652
653 *map = maps;
654 *num_maps = nmaps;
655 if (num_pins) {
656 of_property_for_each_string(np, "pins", prop, pin) {
657 ret = rzg2l_map_add_config(&maps[idx], pin,
658 PIN_MAP_TYPE_CONFIGS_PIN,
659 configs, num_configs);
660 if (ret < 0)
661 goto done;
662
663 idx++;
664 }
665 ret = 0;
666 goto done;
667 }
668
669 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
670 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
671 GFP_KERNEL);
672 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
673 if (!pins || !psel_val || !pin_fn) {
674 ret = -ENOMEM;
675 goto done;
676 }
677
678 /* Collect pin locations and mux settings from DT properties */
679 for (i = 0; i < num_pinmux; ++i) {
680 u32 value;
681
682 ret = of_property_read_u32_index(np, "pinmux", i, &value);
683 if (ret)
684 goto done;
685 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);
686 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);
687 }
688
689 if (parent) {
690 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
691 parent, np);
692 if (!name) {
693 ret = -ENOMEM;
694 goto done;
695 }
696 } else {
697 name = np->name;
698 }
699
700 if (num_configs) {
701 ret = rzg2l_map_add_config(&maps[idx], name,
702 PIN_MAP_TYPE_CONFIGS_GROUP,
703 configs, num_configs);
704 if (ret < 0)
705 goto done;
706
707 idx++;
708 }
709
710 mutex_lock(&pctrl->mutex);
711
712 /* Register a single pin group listing all the pins we read from DT */
713 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
714 if (gsel < 0) {
715 ret = gsel;
716 goto unlock;
717 }
718
719 /*
720 * Register a single group function where the 'data' is an array PSEL
721 * register values read from DT.
722 */
723 pin_fn[0] = name;
724 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
725 if (fsel < 0) {
726 ret = fsel;
727 goto remove_group;
728 }
729
730 mutex_unlock(&pctrl->mutex);
731
732 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
733 maps[idx].data.mux.group = name;
734 maps[idx].data.mux.function = name;
735 idx++;
736
737 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
738 ret = 0;
739 goto done;
740
741 remove_group:
742 pinctrl_generic_remove_group(pctldev, gsel);
743 unlock:
744 mutex_unlock(&pctrl->mutex);
745 done:
746 *index = idx;
747 kfree(configs);
748 return ret;
749 }
750
rzg2l_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned int num_maps)751 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
752 struct pinctrl_map *map,
753 unsigned int num_maps)
754 {
755 unsigned int i;
756
757 if (!map)
758 return;
759
760 for (i = 0; i < num_maps; ++i) {
761 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
762 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
763 kfree(map[i].data.configs.configs);
764 }
765 kfree(map);
766 }
767
rzg2l_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)768 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
769 struct device_node *np,
770 struct pinctrl_map **map,
771 unsigned int *num_maps)
772 {
773 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
774 unsigned int index;
775 int ret;
776
777 *map = NULL;
778 *num_maps = 0;
779 index = 0;
780
781 for_each_child_of_node_scoped(np, child) {
782 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
783 num_maps, &index);
784 if (ret < 0)
785 goto done;
786 }
787
788 if (*num_maps == 0) {
789 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
790 num_maps, &index);
791 if (ret < 0)
792 goto done;
793 }
794
795 if (*num_maps)
796 return 0;
797
798 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
799 ret = -EINVAL;
800
801 done:
802 rzg2l_dt_free_map(pctldev, *map, *num_maps);
803
804 return ret;
805 }
806
rzg2l_validate_gpio_pin(struct rzg2l_pinctrl * pctrl,u64 cfg,u32 port,u8 bit)807 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
808 u64 cfg, u32 port, u8 bit)
809 {
810 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
811 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
812 u64 data;
813
814 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
815 return -EINVAL;
816
817 data = pctrl->data->port_pin_configs[port];
818 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
819 return -EINVAL;
820
821 return 0;
822 }
823
rzg2l_read_pin_config(struct rzg2l_pinctrl * pctrl,u32 offset,u8 bit,u32 mask)824 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
825 u8 bit, u32 mask)
826 {
827 void __iomem *addr = pctrl->base + offset;
828
829 /* handle _L/_H for 32-bit register read/write */
830 if (bit >= 4) {
831 bit -= 4;
832 addr += 4;
833 }
834
835 return (readl(addr) >> (bit * 8)) & mask;
836 }
837
rzg2l_rmw_pin_config(struct rzg2l_pinctrl * pctrl,u32 offset,u8 bit,u32 mask,u32 val)838 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
839 u8 bit, u32 mask, u32 val)
840 {
841 void __iomem *addr = pctrl->base + offset;
842 unsigned long flags;
843 u32 reg;
844
845 /* handle _L/_H for 32-bit register read/write */
846 if (bit >= 4) {
847 bit -= 4;
848 addr += 4;
849 }
850
851 spin_lock_irqsave(&pctrl->lock, flags);
852 reg = readl(addr) & ~(mask << (bit * 8));
853 writel(reg | (val << (bit * 8)), addr);
854 spin_unlock_irqrestore(&pctrl->lock, flags);
855 }
856
rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets * regs,u32 caps)857 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)
858 {
859 if (caps & PIN_CFG_IO_VMC_SD0)
860 return SD_CH(regs->sd_ch, 0);
861 if (caps & PIN_CFG_IO_VMC_SD1)
862 return SD_CH(regs->sd_ch, 1);
863 if (caps & PIN_CFG_IO_VMC_ETH0)
864 return ETH_POC(regs->eth_poc, 0);
865 if (caps & PIN_CFG_IO_VMC_ETH1)
866 return ETH_POC(regs->eth_poc, 1);
867 if (caps & PIN_CFG_IO_VMC_QSPI)
868 return QSPI;
869
870 return -EINVAL;
871 }
872
rzg2l_get_power_source(struct rzg2l_pinctrl * pctrl,u32 pin,u32 caps)873 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)
874 {
875 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
876 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
877 int pwr_reg;
878 u8 val;
879
880 if (caps & PIN_CFG_SOFT_PS)
881 return pctrl->settings[pin].power_source;
882
883 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
884 if (pwr_reg < 0)
885 return pwr_reg;
886
887 val = readb(pctrl->base + pwr_reg);
888 switch (val) {
889 case PVDD_1800:
890 return 1800;
891 case PVDD_2500:
892 return 2500;
893 case PVDD_3300:
894 return 3300;
895 default:
896 /* Should not happen. */
897 return -EINVAL;
898 }
899 }
900
rzg2l_set_power_source(struct rzg2l_pinctrl * pctrl,u32 pin,u32 caps,u32 ps)901 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
902 {
903 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
904 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
905 int pwr_reg;
906 u8 val;
907
908 if (caps & PIN_CFG_SOFT_PS) {
909 pctrl->settings[pin].power_source = ps;
910 return 0;
911 }
912
913 switch (ps) {
914 case 1800:
915 val = PVDD_1800;
916 break;
917 case 2500:
918 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
919 return -EINVAL;
920 val = PVDD_2500;
921 break;
922 case 3300:
923 val = PVDD_3300;
924 break;
925 default:
926 return -EINVAL;
927 }
928
929 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
930 if (pwr_reg < 0)
931 return pwr_reg;
932
933 writeb(val, pctrl->base + pwr_reg);
934 pctrl->settings[pin].power_source = ps;
935
936 return 0;
937 }
938
rzg2l_ps_is_supported(u16 ps)939 static bool rzg2l_ps_is_supported(u16 ps)
940 {
941 unsigned int i;
942
943 for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
944 if (available_ps[i] == ps)
945 return true;
946 }
947
948 return false;
949 }
950
rzg2l_ps_to_iolh_idx(u16 ps)951 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)
952 {
953 unsigned int i;
954
955 for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
956 if (available_ps[i] == ps)
957 break;
958 }
959
960 /*
961 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have
962 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source
963 */
964 return i * RZG2L_IOLH_MAX_DS_ENTRIES;
965 }
966
rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg * hwcfg,u32 caps,u8 val)967 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)
968 {
969 if (caps & PIN_CFG_IOLH_A)
970 return hwcfg->iolh_groupa_ua[val];
971
972 if (caps & PIN_CFG_IOLH_B)
973 return hwcfg->iolh_groupb_ua[val];
974
975 if (caps & PIN_CFG_IOLH_C)
976 return hwcfg->iolh_groupc_ua[val];
977
978 /* Should not happen. */
979 return 0;
980 }
981
rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg * hwcfg,u32 caps,enum rzg2l_iolh_index ps_index,u16 ua)982 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,
983 enum rzg2l_iolh_index ps_index, u16 ua)
984 {
985 const u16 *array = NULL;
986 unsigned int i;
987
988 if (caps & PIN_CFG_IOLH_A)
989 array = &hwcfg->iolh_groupa_ua[ps_index];
990
991 if (caps & PIN_CFG_IOLH_B)
992 array = &hwcfg->iolh_groupb_ua[ps_index];
993
994 if (caps & PIN_CFG_IOLH_C)
995 array = &hwcfg->iolh_groupc_ua[ps_index];
996
997 if (!array)
998 return -EINVAL;
999
1000 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
1001 if (array[i] == ua)
1002 return i;
1003 }
1004
1005 return -EINVAL;
1006 }
1007
rzg2l_ds_is_supported(struct rzg2l_pinctrl * pctrl,u32 caps,enum rzg2l_iolh_index iolh_idx,u16 ds)1008 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
1009 enum rzg2l_iolh_index iolh_idx,
1010 u16 ds)
1011 {
1012 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1013 const u16 *array = NULL;
1014 unsigned int i;
1015
1016 if (caps & PIN_CFG_IOLH_A)
1017 array = hwcfg->iolh_groupa_ua;
1018
1019 if (caps & PIN_CFG_IOLH_B)
1020 array = hwcfg->iolh_groupb_ua;
1021
1022 if (caps & PIN_CFG_IOLH_C)
1023 array = hwcfg->iolh_groupc_ua;
1024
1025 /* Should not happen. */
1026 if (!array)
1027 return false;
1028
1029 if (!array[iolh_idx])
1030 return false;
1031
1032 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
1033 if (array[iolh_idx + i] == ds)
1034 return true;
1035 }
1036
1037 return false;
1038 }
1039
rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1040 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1041 {
1042 u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1043 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
1044 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1045
1046 if (pin > pctrl->data->hwcfg->oen_max_pin)
1047 return -EINVAL;
1048
1049 /*
1050 * We can determine which Ethernet interface we're dealing with from
1051 * the caps.
1052 */
1053 if (caps & PIN_CFG_IO_VMC_ETH0)
1054 return 0;
1055 if (caps & PIN_CFG_IO_VMC_ETH1)
1056 return 1;
1057
1058 return -EINVAL;
1059 }
1060
rzg2l_read_oen(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1061 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1062 {
1063 int bit;
1064
1065 bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1066 if (bit < 0)
1067 return 0;
1068
1069 return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1070 }
1071
rzg2l_write_oen(struct rzg2l_pinctrl * pctrl,unsigned int _pin,u8 oen)1072 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1073 {
1074 unsigned long flags;
1075 int bit;
1076 u8 val;
1077
1078 bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1079 if (bit < 0)
1080 return bit;
1081
1082 spin_lock_irqsave(&pctrl->lock, flags);
1083 val = readb(pctrl->base + ETH_MODE);
1084 if (oen)
1085 val &= ~BIT(bit);
1086 else
1087 val |= BIT(bit);
1088 writeb(val, pctrl->base + ETH_MODE);
1089 spin_unlock_irqrestore(&pctrl->lock, flags);
1090
1091 return 0;
1092 }
1093
rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1094 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1095 {
1096 u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1097 u8 port, pin, bit;
1098
1099 if (*pin_data & RZG2L_SINGLE_PIN)
1100 return -EINVAL;
1101
1102 port = RZG2L_PIN_ID_TO_PORT(_pin);
1103 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1104 if (pin > pctrl->data->hwcfg->oen_max_pin)
1105 return -EINVAL;
1106
1107 bit = pin * 2;
1108 if (port == pctrl->data->hwcfg->oen_max_port)
1109 bit += 1;
1110
1111 return bit;
1112 }
1113
rzg3s_oen_read(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1114 static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1115 {
1116 int bit;
1117
1118 bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1119 if (bit < 0)
1120 return bit;
1121
1122 return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1123 }
1124
rzg3s_oen_write(struct rzg2l_pinctrl * pctrl,unsigned int _pin,u8 oen)1125 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1126 {
1127 unsigned long flags;
1128 int bit;
1129 u8 val;
1130
1131 bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1132 if (bit < 0)
1133 return bit;
1134
1135 spin_lock_irqsave(&pctrl->lock, flags);
1136 val = readb(pctrl->base + ETH_MODE);
1137 if (oen)
1138 val &= ~BIT(bit);
1139 else
1140 val |= BIT(bit);
1141 writeb(val, pctrl->base + ETH_MODE);
1142 spin_unlock_irqrestore(&pctrl->lock, flags);
1143
1144 return 0;
1145 }
1146
rzg2l_hw_to_bias_param(unsigned int bias)1147 static int rzg2l_hw_to_bias_param(unsigned int bias)
1148 {
1149 switch (bias) {
1150 case 0:
1151 return PIN_CONFIG_BIAS_DISABLE;
1152 case 1:
1153 return PIN_CONFIG_BIAS_PULL_UP;
1154 case 2:
1155 return PIN_CONFIG_BIAS_PULL_DOWN;
1156 default:
1157 break;
1158 }
1159
1160 return -EINVAL;
1161 }
1162
rzg2l_bias_param_to_hw(enum pin_config_param param)1163 static int rzg2l_bias_param_to_hw(enum pin_config_param param)
1164 {
1165 switch (param) {
1166 case PIN_CONFIG_BIAS_DISABLE:
1167 return 0;
1168 case PIN_CONFIG_BIAS_PULL_UP:
1169 return 1;
1170 case PIN_CONFIG_BIAS_PULL_DOWN:
1171 return 2;
1172 default:
1173 break;
1174 }
1175
1176 return -EINVAL;
1177 }
1178
rzv2h_hw_to_bias_param(unsigned int bias)1179 static int rzv2h_hw_to_bias_param(unsigned int bias)
1180 {
1181 switch (bias) {
1182 case 0:
1183 case 1:
1184 return PIN_CONFIG_BIAS_DISABLE;
1185 case 2:
1186 return PIN_CONFIG_BIAS_PULL_DOWN;
1187 case 3:
1188 return PIN_CONFIG_BIAS_PULL_UP;
1189 default:
1190 break;
1191 }
1192
1193 return -EINVAL;
1194 }
1195
rzv2h_bias_param_to_hw(enum pin_config_param param)1196 static int rzv2h_bias_param_to_hw(enum pin_config_param param)
1197 {
1198 switch (param) {
1199 case PIN_CONFIG_BIAS_DISABLE:
1200 return 0;
1201 case PIN_CONFIG_BIAS_PULL_DOWN:
1202 return 2;
1203 case PIN_CONFIG_BIAS_PULL_UP:
1204 return 3;
1205 default:
1206 break;
1207 }
1208
1209 return -EINVAL;
1210 }
1211
rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1212 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1213 {
1214 static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
1215 "XSPI0_RESET0N", "XSPI0_CS0N",
1216 "XSPI0_CKN", "XSPI0_CKP" };
1217 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
1218 unsigned int i;
1219
1220 for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
1221 if (!strcmp(pin_desc->name, pin_names[i]))
1222 return i;
1223 }
1224
1225 /* Should not happen. */
1226 return 0;
1227 }
1228
rzv2h_oen_read(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1229 static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1230 {
1231 u8 bit;
1232
1233 bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1234
1235 return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
1236 }
1237
rzv2h_oen_write(struct rzg2l_pinctrl * pctrl,unsigned int _pin,u8 oen)1238 static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1239 {
1240 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1241 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
1242 unsigned long flags;
1243 u8 val, bit;
1244 u8 pwpr;
1245
1246 bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1247 spin_lock_irqsave(&pctrl->lock, flags);
1248 val = readb(pctrl->base + PFC_OEN);
1249 if (oen)
1250 val &= ~BIT(bit);
1251 else
1252 val |= BIT(bit);
1253
1254 pwpr = readb(pctrl->base + regs->pwpr);
1255 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
1256 writeb(val, pctrl->base + PFC_OEN);
1257 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
1258 spin_unlock_irqrestore(&pctrl->lock, flags);
1259
1260 return 0;
1261 }
1262
rzg2l_pinctrl_pinconf_get(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * config)1263 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
1264 unsigned int _pin,
1265 unsigned long *config)
1266 {
1267 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1268 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1269 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1270 u32 param = pinconf_to_config_param(*config);
1271 u64 *pin_data = pin->drv_data;
1272 unsigned int arg = 0;
1273 u32 off;
1274 u32 cfg;
1275 int ret;
1276 u8 bit;
1277
1278 if (!pin_data)
1279 return -EINVAL;
1280
1281 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1282 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1283 if (*pin_data & RZG2L_SINGLE_PIN) {
1284 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1285 } else {
1286 bit = RZG2L_PIN_ID_TO_PIN(_pin);
1287
1288 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1289 return -EINVAL;
1290 }
1291
1292 switch (param) {
1293 case PIN_CONFIG_INPUT_ENABLE:
1294 if (!(cfg & PIN_CFG_IEN))
1295 return -EINVAL;
1296 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);
1297 if (!arg)
1298 return -EINVAL;
1299 break;
1300
1301 case PIN_CONFIG_OUTPUT_ENABLE:
1302 if (!(cfg & PIN_CFG_OEN))
1303 return -EINVAL;
1304 if (!pctrl->data->oen_read)
1305 return -EOPNOTSUPP;
1306 arg = pctrl->data->oen_read(pctrl, _pin);
1307 if (!arg)
1308 return -EINVAL;
1309 break;
1310
1311 case PIN_CONFIG_POWER_SOURCE:
1312 ret = rzg2l_get_power_source(pctrl, _pin, cfg);
1313 if (ret < 0)
1314 return ret;
1315 arg = ret;
1316 break;
1317
1318 case PIN_CONFIG_SLEW_RATE:
1319 if (!(cfg & PIN_CFG_SR))
1320 return -EINVAL;
1321
1322 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
1323 break;
1324
1325 case PIN_CONFIG_BIAS_DISABLE:
1326 case PIN_CONFIG_BIAS_PULL_UP:
1327 case PIN_CONFIG_BIAS_PULL_DOWN:
1328 if (!(cfg & PIN_CFG_PUPD))
1329 return -EINVAL;
1330
1331 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK);
1332 ret = pctrl->data->hw_to_bias_param(arg);
1333 if (ret < 0)
1334 return ret;
1335
1336 if (ret != param)
1337 return -EINVAL;
1338 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
1339 arg = 1;
1340 break;
1341
1342 case PIN_CONFIG_DRIVE_STRENGTH: {
1343 unsigned int index;
1344
1345 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1346 return -EINVAL;
1347
1348 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1349 /*
1350 * Drive strenght mA is supported only by group A and only
1351 * for 3V3 port source.
1352 */
1353 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;
1354 break;
1355 }
1356
1357 case PIN_CONFIG_DRIVE_STRENGTH_UA: {
1358 enum rzg2l_iolh_index iolh_idx;
1359 u8 val;
1360
1361 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1362 !hwcfg->drive_strength_ua)
1363 return -EINVAL;
1364
1365 ret = rzg2l_get_power_source(pctrl, _pin, cfg);
1366 if (ret < 0)
1367 return ret;
1368 iolh_idx = rzg2l_ps_to_iolh_idx(ret);
1369 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1370 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val);
1371 break;
1372 }
1373
1374 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
1375 unsigned int index;
1376
1377 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1378 return -EINVAL;
1379
1380 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1381 arg = hwcfg->iolh_groupb_oi[index];
1382 break;
1383 }
1384
1385 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1386 case PIN_CONFIG_DRIVE_PUSH_PULL:
1387 if (!(cfg & PIN_CFG_NOD))
1388 return -EINVAL;
1389
1390 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK);
1391 if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL)
1392 return -EINVAL;
1393 if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN)
1394 return -EINVAL;
1395 break;
1396
1397 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1398 if (!(cfg & PIN_CFG_SMT))
1399 return -EINVAL;
1400
1401 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK);
1402 if (!arg)
1403 return -EINVAL;
1404 break;
1405
1406 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1407 if (!(cfg & PIN_CFG_IOLH_RZV2H))
1408 return -EINVAL;
1409
1410 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1411 break;
1412
1413 default:
1414 return -ENOTSUPP;
1415 }
1416
1417 *config = pinconf_to_config_packed(param, arg);
1418
1419 return 0;
1420 };
1421
rzg2l_pinctrl_pinconf_set(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * _configs,unsigned int num_configs)1422 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
1423 unsigned int _pin,
1424 unsigned long *_configs,
1425 unsigned int num_configs)
1426 {
1427 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1428 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1429 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1430 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
1431 u64 *pin_data = pin->drv_data;
1432 unsigned int i, arg, index;
1433 u32 off, param;
1434 u32 cfg;
1435 int ret;
1436 u8 bit;
1437
1438 if (!pin_data)
1439 return -EINVAL;
1440
1441 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1442 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1443 if (*pin_data & RZG2L_SINGLE_PIN) {
1444 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1445 } else {
1446 bit = RZG2L_PIN_ID_TO_PIN(_pin);
1447
1448 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1449 return -EINVAL;
1450 }
1451
1452 for (i = 0; i < num_configs; i++) {
1453 param = pinconf_to_config_param(_configs[i]);
1454 arg = pinconf_to_config_argument(_configs[i]);
1455 switch (param) {
1456 case PIN_CONFIG_INPUT_ENABLE:
1457
1458 if (!(cfg & PIN_CFG_IEN))
1459 return -EINVAL;
1460
1461 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg);
1462 break;
1463
1464 case PIN_CONFIG_OUTPUT_ENABLE:
1465 if (!(cfg & PIN_CFG_OEN))
1466 return -EINVAL;
1467 if (!pctrl->data->oen_write)
1468 return -EOPNOTSUPP;
1469 ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
1470 if (ret)
1471 return ret;
1472 break;
1473
1474 case PIN_CONFIG_POWER_SOURCE:
1475 settings.power_source = arg;
1476 break;
1477
1478 case PIN_CONFIG_SLEW_RATE:
1479 if (!(cfg & PIN_CFG_SR) || arg > 1)
1480 return -EINVAL;
1481
1482 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);
1483 break;
1484
1485 case PIN_CONFIG_BIAS_DISABLE:
1486 case PIN_CONFIG_BIAS_PULL_UP:
1487 case PIN_CONFIG_BIAS_PULL_DOWN:
1488 if (!(cfg & PIN_CFG_PUPD))
1489 return -EINVAL;
1490
1491 ret = pctrl->data->bias_param_to_hw(param);
1492 if (ret < 0)
1493 return ret;
1494
1495 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret);
1496 break;
1497
1498 case PIN_CONFIG_DRIVE_STRENGTH:
1499 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1500 return -EINVAL;
1501
1502 for (index = RZG2L_IOLH_IDX_3V3;
1503 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {
1504 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))
1505 break;
1506 }
1507 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))
1508 return -EINVAL;
1509
1510 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1511 break;
1512
1513 case PIN_CONFIG_DRIVE_STRENGTH_UA:
1514 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1515 !hwcfg->drive_strength_ua)
1516 return -EINVAL;
1517
1518 settings.drive_strength_ua = arg;
1519 break;
1520
1521 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
1522 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1523 return -EINVAL;
1524
1525 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {
1526 if (arg == hwcfg->iolh_groupb_oi[index])
1527 break;
1528 }
1529 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))
1530 return -EINVAL;
1531
1532 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1533 break;
1534
1535 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1536 case PIN_CONFIG_DRIVE_PUSH_PULL:
1537 if (!(cfg & PIN_CFG_NOD))
1538 return -EINVAL;
1539
1540 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK,
1541 param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0);
1542 break;
1543
1544 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1545 if (!(cfg & PIN_CFG_SMT))
1546 return -EINVAL;
1547
1548 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg);
1549 break;
1550
1551 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1552 if (!(cfg & PIN_CFG_IOLH_RZV2H))
1553 return -EINVAL;
1554
1555 if (arg > 3)
1556 return -EINVAL;
1557 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
1558 break;
1559
1560 default:
1561 return -EOPNOTSUPP;
1562 }
1563 }
1564
1565 /* Apply power source. */
1566 if (settings.power_source != pctrl->settings[_pin].power_source) {
1567 ret = rzg2l_ps_is_supported(settings.power_source);
1568 if (!ret)
1569 return -EINVAL;
1570
1571 /* Apply power source. */
1572 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source);
1573 if (ret)
1574 return ret;
1575 }
1576
1577 /* Apply drive strength. */
1578 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {
1579 enum rzg2l_iolh_index iolh_idx;
1580 int val;
1581
1582 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source);
1583 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx,
1584 settings.drive_strength_ua);
1585 if (!ret)
1586 return -EINVAL;
1587
1588 /* Get register value for this PS/DS tuple. */
1589 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua);
1590 if (val < 0)
1591 return val;
1592
1593 /* Apply drive strength. */
1594 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);
1595 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;
1596 }
1597
1598 return 0;
1599 }
1600
rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)1601 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
1602 unsigned int group,
1603 unsigned long *configs,
1604 unsigned int num_configs)
1605 {
1606 const unsigned int *pins;
1607 unsigned int i, npins;
1608 int ret;
1609
1610 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1611 if (ret)
1612 return ret;
1613
1614 for (i = 0; i < npins; i++) {
1615 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs,
1616 num_configs);
1617 if (ret)
1618 return ret;
1619 }
1620
1621 return 0;
1622 };
1623
rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)1624 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
1625 unsigned int group,
1626 unsigned long *config)
1627 {
1628 const unsigned int *pins;
1629 unsigned int i, npins, prev_config = 0;
1630 int ret;
1631
1632 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1633 if (ret)
1634 return ret;
1635
1636 for (i = 0; i < npins; i++) {
1637 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config);
1638 if (ret)
1639 return ret;
1640
1641 /* Check config matching between to pin */
1642 if (i && prev_config != *config)
1643 return -EOPNOTSUPP;
1644
1645 prev_config = *config;
1646 }
1647
1648 return 0;
1649 };
1650
1651 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
1652 .get_groups_count = pinctrl_generic_get_group_count,
1653 .get_group_name = pinctrl_generic_get_group_name,
1654 .get_group_pins = pinctrl_generic_get_group_pins,
1655 .dt_node_to_map = rzg2l_dt_node_to_map,
1656 .dt_free_map = rzg2l_dt_free_map,
1657 };
1658
1659 static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
1660 .get_functions_count = pinmux_generic_get_function_count,
1661 .get_function_name = pinmux_generic_get_function_name,
1662 .get_function_groups = pinmux_generic_get_function_groups,
1663 .set_mux = rzg2l_pinctrl_set_mux,
1664 .strict = true,
1665 };
1666
1667 static const struct pinconf_ops rzg2l_pinctrl_confops = {
1668 .is_generic = true,
1669 .pin_config_get = rzg2l_pinctrl_pinconf_get,
1670 .pin_config_set = rzg2l_pinctrl_pinconf_set,
1671 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
1672 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
1673 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1674 };
1675
rzg2l_gpio_request(struct gpio_chip * chip,unsigned int offset)1676 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
1677 {
1678 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1679 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1680 u64 *pin_data = pin_desc->drv_data;
1681 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1682 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
1683 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1684 unsigned long flags;
1685 u8 reg8;
1686 int ret;
1687
1688 ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
1689 if (ret)
1690 return ret;
1691
1692 ret = pinctrl_gpio_request(chip, offset);
1693 if (ret)
1694 return ret;
1695
1696 spin_lock_irqsave(&pctrl->lock, flags);
1697
1698 /* Select GPIO mode in PMC Register */
1699 reg8 = readb(pctrl->base + PMC(off));
1700 reg8 &= ~BIT(bit);
1701 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
1702
1703 spin_unlock_irqrestore(&pctrl->lock, flags);
1704
1705 return 0;
1706 }
1707
rzg2l_gpio_set_direction(struct rzg2l_pinctrl * pctrl,u32 offset,bool output)1708 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,
1709 bool output)
1710 {
1711 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1712 u64 *pin_data = pin_desc->drv_data;
1713 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1714 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1715 unsigned long flags;
1716 u16 reg16;
1717
1718 spin_lock_irqsave(&pctrl->lock, flags);
1719
1720 reg16 = readw(pctrl->base + PM(off));
1721 reg16 &= ~(PM_MASK << (bit * 2));
1722
1723 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
1724 writew(reg16, pctrl->base + PM(off));
1725
1726 spin_unlock_irqrestore(&pctrl->lock, flags);
1727 }
1728
rzg2l_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1729 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1730 {
1731 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1732 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1733 u64 *pin_data = pin_desc->drv_data;
1734 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1735 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1736
1737 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {
1738 u16 reg16;
1739
1740 reg16 = readw(pctrl->base + PM(off));
1741 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1742 if (reg16 == PM_OUTPUT)
1743 return GPIO_LINE_DIRECTION_OUT;
1744 }
1745
1746 return GPIO_LINE_DIRECTION_IN;
1747 }
1748
rzg2l_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1749 static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
1750 unsigned int offset)
1751 {
1752 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1753
1754 rzg2l_gpio_set_direction(pctrl, offset, false);
1755
1756 return 0;
1757 }
1758
rzg2l_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1759 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
1760 int value)
1761 {
1762 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1763 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1764 u64 *pin_data = pin_desc->drv_data;
1765 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1766 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1767 unsigned long flags;
1768 u8 reg8;
1769
1770 spin_lock_irqsave(&pctrl->lock, flags);
1771
1772 reg8 = readb(pctrl->base + P(off));
1773
1774 if (value)
1775 writeb(reg8 | BIT(bit), pctrl->base + P(off));
1776 else
1777 writeb(reg8 & ~BIT(bit), pctrl->base + P(off));
1778
1779 spin_unlock_irqrestore(&pctrl->lock, flags);
1780 }
1781
rzg2l_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1782 static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
1783 unsigned int offset, int value)
1784 {
1785 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1786
1787 rzg2l_gpio_set(chip, offset, value);
1788 rzg2l_gpio_set_direction(pctrl, offset, true);
1789
1790 return 0;
1791 }
1792
rzg2l_gpio_get(struct gpio_chip * chip,unsigned int offset)1793 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
1794 {
1795 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1796 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1797 u64 *pin_data = pin_desc->drv_data;
1798 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1799 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1800 u16 reg16;
1801
1802 reg16 = readw(pctrl->base + PM(off));
1803 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1804
1805 if (reg16 == PM_INPUT)
1806 return !!(readb(pctrl->base + PIN(off)) & BIT(bit));
1807 else if (reg16 == PM_OUTPUT)
1808 return !!(readb(pctrl->base + P(off)) & BIT(bit));
1809 else
1810 return -EINVAL;
1811 }
1812
rzg2l_gpio_free(struct gpio_chip * chip,unsigned int offset)1813 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
1814 {
1815 unsigned int virq;
1816
1817 pinctrl_gpio_free(chip, offset);
1818
1819 virq = irq_find_mapping(chip->irq.domain, offset);
1820 if (virq)
1821 irq_dispose_mapping(virq);
1822
1823 /*
1824 * Set the GPIO as an input to ensure that the next GPIO request won't
1825 * drive the GPIO pin as an output.
1826 */
1827 rzg2l_gpio_direction_input(chip, offset);
1828 }
1829
1830 static const char * const rzg2l_gpio_names[] = {
1831 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
1832 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
1833 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
1834 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
1835 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
1836 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
1837 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
1838 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
1839 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
1840 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
1841 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
1842 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
1843 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
1844 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
1845 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
1846 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
1847 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
1848 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
1849 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
1850 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
1851 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
1852 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
1853 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
1854 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
1855 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
1856 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
1857 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
1858 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
1859 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
1860 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
1861 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
1862 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
1863 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
1864 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
1865 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
1866 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
1867 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
1868 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
1869 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
1870 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
1871 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
1872 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
1873 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
1874 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
1875 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
1876 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
1877 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
1878 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
1879 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
1880 };
1881
1882 static const u64 r9a07g044_gpio_configs[] = {
1883 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
1884 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
1885 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
1886 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
1887 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
1888 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
1889 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
1890 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
1891 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
1892 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
1893 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
1894 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1895 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1896 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1897 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1898 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1899 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1900 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
1901 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
1902 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1903 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1904 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1905 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1906 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1907 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1908 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1909 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1910 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1911 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1912 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1913 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1914 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1915 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1916 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1917 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1918 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1919 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1920 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1921 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
1922 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
1923 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
1924 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
1925 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
1926 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
1927 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
1928 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
1929 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
1930 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
1931 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
1932 };
1933
1934 static const u64 r9a07g043_gpio_configs[] = {
1935 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1936 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1937 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1938 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1939 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1940 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1941 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1942 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1943 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1944 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1945 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1946 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1947 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1948 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1949 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1950 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1951 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1952 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
1953 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
1954 #ifdef CONFIG_RISCV
1955 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
1956 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1957 PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
1958 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
1959 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1960 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
1961 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1962 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
1963 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
1964 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
1965 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |
1966 PIN_CFG_NOGPIO_INT), /* P25 */
1967 0x0, /* P26 */
1968 0x0, /* P27 */
1969 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */
1970 #endif
1971 };
1972
1973 static const u64 r9a08g045_gpio_configs[] = {
1974 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
1975 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1976 PIN_CFG_IO_VMC_ETH0)) |
1977 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */
1978 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1979 PIN_CFG_IO_VMC_ETH0)), /* P2 */
1980 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1981 PIN_CFG_IO_VMC_ETH0)), /* P3 */
1982 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1983 PIN_CFG_IO_VMC_ETH0)), /* P4 */
1984 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
1985 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
1986 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1987 PIN_CFG_IO_VMC_ETH1)) |
1988 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */
1989 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1990 PIN_CFG_IO_VMC_ETH1)), /* P8 */
1991 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1992 PIN_CFG_IO_VMC_ETH1)), /* P9 */
1993 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1994 PIN_CFG_IO_VMC_ETH1)), /* P10 */
1995 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
1996 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
1997 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
1998 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
1999 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
2000 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
2001 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
2002 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
2003 };
2004
2005 static const char * const rzg3e_gpio_names[] = {
2006 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2007 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
2008 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2009 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2010 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
2011 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2012 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2013 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2014 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2015 "", "", "", "", "", "", "", "",
2016 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2017 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2018 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
2019 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
2020 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
2021 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
2022 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
2023 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
2024 "", "", "", "", "", "", "", "",
2025 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
2026 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
2027 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
2028 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
2029 "", "", "", "", "", "", "", "",
2030 "", "", "", "", "", "", "", "",
2031 "", "", "", "", "", "", "", "",
2032 "", "", "", "", "", "", "", "",
2033 "", "", "", "", "", "", "", "",
2034 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
2035 };
2036
2037 static const u64 r9a09g047_gpio_configs[] = {
2038 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
2039 RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |
2040 PIN_CFG_ELC), /* P1 */
2041 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
2042 PIN_CFG_NOD), /* P2 */
2043 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
2044 RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
2045 RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
2046 RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */
2047 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |
2048 PIN_CFG_ELC), /* P7 */
2049 RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
2050 0x0,
2051 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
2052 RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
2053 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
2054 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
2055 RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
2056 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
2057 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
2058 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
2059 0x0,
2060 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
2061 RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
2062 RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
2063 RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
2064 0x0,
2065 0x0,
2066 0x0,
2067 0x0,
2068 0x0,
2069 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
2070 };
2071
2072 static const char * const rzv2h_gpio_names[] = {
2073 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2074 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
2075 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2076 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2077 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
2078 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2079 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2080 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2081 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2082 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",
2083 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2084 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2085 };
2086
2087 static const u64 r9a09g057_gpio_configs[] = {
2088 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
2089 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */
2090 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
2091 PIN_CFG_NOD), /* P2 */
2092 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
2093 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
2094 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
2095 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS |
2096 PIN_CFG_ELC), /* P6 */
2097 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */
2098 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS |
2099 PIN_CFG_ELC), /* P8 */
2100 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */
2101 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */
2102 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */
2103 };
2104
2105 static const struct {
2106 struct rzg2l_dedicated_configs common[35];
2107 struct rzg2l_dedicated_configs rzg2l_pins[7];
2108 } rzg2l_dedicated_pins = {
2109 .common = {
2110 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2111 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
2112 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
2113 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
2114 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
2115 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
2116 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
2117 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2118 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
2119 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2120 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2121 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
2122 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
2123 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
2124 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2125 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
2126 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2127 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
2128 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2129 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
2130 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2131 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
2132 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2133 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
2134 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2135 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
2136 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2137 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
2138 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2139 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
2140 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
2141 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
2142 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2143 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
2144 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2145 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2146 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2147 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
2148 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2149 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
2150 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2151 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
2152 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2153 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
2154 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2155 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
2156 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2157 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
2158 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2159 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
2160 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2161 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
2162 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2163 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
2164 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2165 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
2166 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2167 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
2168 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
2169 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
2170 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
2171 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
2172 },
2173 .rzg2l_pins = {
2174 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2175 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
2176 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2177 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
2178 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2179 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
2180 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2181 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
2182 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2183 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
2184 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2185 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
2186 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2187 }
2188 };
2189
2190 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
2191 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) },
2192 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
2193 PIN_CFG_SOFT_PS)) },
2194 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
2195 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
2196 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
2197 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
2198 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
2199 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2200 PIN_CFG_IO_VMC_SD0)) },
2201 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
2202 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2203 PIN_CFG_IO_VMC_SD0)) },
2204 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2205 PIN_CFG_IO_VMC_SD0)) },
2206 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2207 PIN_CFG_IO_VMC_SD0)) },
2208 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2209 PIN_CFG_IO_VMC_SD0)) },
2210 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2211 PIN_CFG_IO_VMC_SD0)) },
2212 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2213 PIN_CFG_IO_VMC_SD0)) },
2214 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2215 PIN_CFG_IO_VMC_SD0)) },
2216 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2217 PIN_CFG_IO_VMC_SD0)) },
2218 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
2219 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2220 PIN_CFG_IO_VMC_SD1)) },
2221 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2222 PIN_CFG_IO_VMC_SD1)) },
2223 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2224 PIN_CFG_IO_VMC_SD1)) },
2225 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2226 PIN_CFG_IO_VMC_SD1)) },
2227 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2228 PIN_CFG_IO_VMC_SD1)) },
2229 };
2230
2231 static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
2232 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2233 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2234 PIN_CFG_IEN)) },
2235 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2236 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2237 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2238 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2239 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2240 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2241 PIN_CFG_PUPD)) },
2242 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2243 PIN_CFG_PUPD)) },
2244 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2245 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2246 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2247 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2248 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2249 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2250 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2251 PIN_CFG_PUPD)) },
2252 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2253 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2254 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
2255 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
2256 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
2257 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2258 PIN_CFG_PUPD)) },
2259 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2260 PIN_CFG_PUPD)) },
2261 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2262 PIN_CFG_PUPD)) },
2263 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2264 PIN_CFG_PUPD)) },
2265 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2266 PIN_CFG_PUPD)) },
2267 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2268 PIN_CFG_PUPD)) },
2269 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2270 PIN_CFG_PUPD)) },
2271 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2272 PIN_CFG_PUPD)) },
2273 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2274 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2275 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2276 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2277 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2278 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2279 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2280 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2281 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2282 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2283 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2284 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2285 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2286 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2287 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2288 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2289 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2290 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2291 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2292 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2293 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2294 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2295 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2296 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2297 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2298 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2299 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2300 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2301 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2302 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2303 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2304 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2305 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2306 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2307 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2308 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2309 PIN_CFG_PUPD)) },
2310 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
2311 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2312 PIN_CFG_PUPD)) },
2313 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2314 PIN_CFG_PUPD)) },
2315 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
2316 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
2317 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2318 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2319 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
2320 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
2321 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2322 PIN_CFG_PUPD)) },
2323 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2324 PIN_CFG_PUPD)) },
2325 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2326 PIN_CFG_PUPD)) },
2327 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2328 PIN_CFG_PUPD)) },
2329 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
2330 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
2331 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
2332 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
2333 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2334 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2335 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2336 PIN_CFG_PUPD)) },
2337 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
2338 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2339 PIN_CFG_PUPD)) },
2340 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2341 PIN_CFG_PUPD)) },
2342 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
2343 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
2344 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2345 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2346 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
2347 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
2348 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2349 PIN_CFG_PUPD)) },
2350 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2351 PIN_CFG_PUPD)) },
2352 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2353 PIN_CFG_PUPD)) },
2354 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2355 PIN_CFG_PUPD)) },
2356 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
2357 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
2358 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
2359 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
2360 };
2361
2362 static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
2363 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,
2364 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2365 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,
2366 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2367 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2368 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2369 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2370 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2371 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,
2372 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2373 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2374 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2375 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,
2376 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2377 { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,
2378 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2379 { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,
2380 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2381 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,
2382 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2383 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,
2384 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2385 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,
2386 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2387 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,
2388 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2389 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,
2390 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2391 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,
2392 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2393 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,
2394 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2395 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,
2396 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2397 };
2398
rzg2l_gpio_get_gpioint(unsigned int virq,struct rzg2l_pinctrl * pctrl)2399 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
2400 {
2401 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
2402 const struct rzg2l_pinctrl_data *data = pctrl->data;
2403 u64 *pin_data = pin_desc->drv_data;
2404 unsigned int gpioint;
2405 unsigned int i;
2406 u32 port, bit;
2407
2408 if (*pin_data & PIN_CFG_NOGPIO_INT)
2409 return -EINVAL;
2410
2411 port = virq / 8;
2412 bit = virq % 8;
2413
2414 if (port >= data->n_ports ||
2415 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))
2416 return -EINVAL;
2417
2418 gpioint = bit;
2419 for (i = 0; i < port; i++)
2420 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i]));
2421
2422 return gpioint;
2423 }
2424
rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl * pctrl,unsigned int hwirq,bool enable)2425 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl,
2426 unsigned int hwirq, bool enable)
2427 {
2428 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
2429 u64 *pin_data = pin_desc->drv_data;
2430 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
2431 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
2432 unsigned long flags;
2433 void __iomem *addr;
2434
2435 addr = pctrl->base + ISEL(off);
2436 if (bit >= 4) {
2437 bit -= 4;
2438 addr += 4;
2439 }
2440
2441 spin_lock_irqsave(&pctrl->lock, flags);
2442 if (enable)
2443 writel(readl(addr) | BIT(bit * 8), addr);
2444 else
2445 writel(readl(addr) & ~BIT(bit * 8), addr);
2446 spin_unlock_irqrestore(&pctrl->lock, flags);
2447 }
2448
rzg2l_gpio_irq_disable(struct irq_data * d)2449 static void rzg2l_gpio_irq_disable(struct irq_data *d)
2450 {
2451 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2452 unsigned int hwirq = irqd_to_hwirq(d);
2453
2454 irq_chip_disable_parent(d);
2455 gpiochip_disable_irq(gc, hwirq);
2456 }
2457
rzg2l_gpio_irq_enable(struct irq_data * d)2458 static void rzg2l_gpio_irq_enable(struct irq_data *d)
2459 {
2460 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2461 unsigned int hwirq = irqd_to_hwirq(d);
2462
2463 gpiochip_enable_irq(gc, hwirq);
2464 irq_chip_enable_parent(d);
2465 }
2466
rzg2l_gpio_irq_set_type(struct irq_data * d,unsigned int type)2467 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2468 {
2469 return irq_chip_set_type_parent(d, type);
2470 }
2471
rzg2l_gpio_irqc_eoi(struct irq_data * d)2472 static void rzg2l_gpio_irqc_eoi(struct irq_data *d)
2473 {
2474 irq_chip_eoi_parent(d);
2475 }
2476
rzg2l_gpio_irq_print_chip(struct irq_data * data,struct seq_file * p)2477 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
2478 {
2479 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
2480
2481 seq_puts(p, dev_name(gc->parent));
2482 }
2483
rzg2l_gpio_irq_set_wake(struct irq_data * data,unsigned int on)2484 static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
2485 {
2486 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
2487 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
2488 int ret;
2489
2490 /* It should not happen. */
2491 if (!data->parent_data)
2492 return -EOPNOTSUPP;
2493
2494 ret = irq_chip_set_wake_parent(data, on);
2495 if (ret)
2496 return ret;
2497
2498 if (on)
2499 atomic_inc(&pctrl->wakeup_path);
2500 else
2501 atomic_dec(&pctrl->wakeup_path);
2502
2503 return 0;
2504 }
2505
2506 static const struct irq_chip rzg2l_gpio_irqchip = {
2507 .name = "rzg2l-gpio",
2508 .irq_disable = rzg2l_gpio_irq_disable,
2509 .irq_enable = rzg2l_gpio_irq_enable,
2510 .irq_mask = irq_chip_mask_parent,
2511 .irq_unmask = irq_chip_unmask_parent,
2512 .irq_set_type = rzg2l_gpio_irq_set_type,
2513 .irq_eoi = rzg2l_gpio_irqc_eoi,
2514 .irq_print_chip = rzg2l_gpio_irq_print_chip,
2515 .irq_set_affinity = irq_chip_set_affinity_parent,
2516 .irq_set_wake = rzg2l_gpio_irq_set_wake,
2517 .flags = IRQCHIP_IMMUTABLE,
2518 GPIOCHIP_IRQ_RESOURCE_HELPERS,
2519 };
2520
rzg2l_gpio_interrupt_input_mode(struct gpio_chip * chip,unsigned int offset)2521 static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset)
2522 {
2523 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
2524 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
2525 u64 *pin_data = pin_desc->drv_data;
2526 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
2527 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
2528 u8 reg8;
2529 int ret;
2530
2531 reg8 = readb(pctrl->base + PMC(off));
2532 if (reg8 & BIT(bit)) {
2533 ret = rzg2l_gpio_request(chip, offset);
2534 if (ret)
2535 return ret;
2536 }
2537
2538 return rzg2l_gpio_direction_input(chip, offset);
2539 }
2540
rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip * gc,unsigned int child,unsigned int child_type,unsigned int * parent,unsigned int * parent_type)2541 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
2542 unsigned int child,
2543 unsigned int child_type,
2544 unsigned int *parent,
2545 unsigned int *parent_type)
2546 {
2547 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
2548 unsigned long flags;
2549 int gpioint, irq;
2550 int ret;
2551
2552 gpioint = rzg2l_gpio_get_gpioint(child, pctrl);
2553 if (gpioint < 0)
2554 return gpioint;
2555
2556 ret = rzg2l_gpio_interrupt_input_mode(gc, child);
2557 if (ret)
2558 return ret;
2559
2560 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2561 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));
2562 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
2563 if (irq < 0) {
2564 ret = -ENOSPC;
2565 goto err;
2566 }
2567
2568 rzg2l_gpio_irq_endisable(pctrl, child, true);
2569 pctrl->hwirq[irq] = child;
2570 irq += pctrl->data->hwcfg->tint_start_index;
2571
2572 /* All these interrupts are level high in the CPU */
2573 *parent_type = IRQ_TYPE_LEVEL_HIGH;
2574 *parent = RZG2L_PACK_HWIRQ(gpioint, irq);
2575 return 0;
2576
2577 err:
2578 rzg2l_gpio_free(gc, child);
2579 return ret;
2580 }
2581
rzg2l_gpio_irq_restore(struct rzg2l_pinctrl * pctrl)2582 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
2583 {
2584 struct irq_domain *domain = pctrl->gpio_chip.irq.domain;
2585
2586 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2587 struct irq_data *data;
2588 unsigned long flags;
2589 unsigned int virq;
2590 int ret;
2591
2592 if (!pctrl->hwirq[i])
2593 continue;
2594
2595 virq = irq_find_mapping(domain, pctrl->hwirq[i]);
2596 if (!virq) {
2597 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n",
2598 pctrl->hwirq[i]);
2599 continue;
2600 }
2601
2602 data = irq_domain_get_irq_data(domain, virq);
2603 if (!data) {
2604 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq);
2605 continue;
2606 }
2607
2608 /*
2609 * This has to be atomically executed to protect against a concurrent
2610 * interrupt.
2611 */
2612 spin_lock_irqsave(&pctrl->lock, flags);
2613 ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data));
2614 if (!ret && !irqd_irq_disabled(data))
2615 rzg2l_gpio_irq_enable(data);
2616 spin_unlock_irqrestore(&pctrl->lock, flags);
2617
2618 if (ret)
2619 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq);
2620 }
2621 }
2622
rzg2l_gpio_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)2623 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2624 unsigned int nr_irqs)
2625 {
2626 struct irq_data *d;
2627
2628 d = irq_domain_get_irq_data(domain, virq);
2629 if (d) {
2630 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2631 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
2632 irq_hw_number_t hwirq = irqd_to_hwirq(d);
2633 unsigned long flags;
2634 unsigned int i;
2635
2636 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2637 if (pctrl->hwirq[i] == hwirq) {
2638 rzg2l_gpio_irq_endisable(pctrl, hwirq, false);
2639 rzg2l_gpio_free(gc, hwirq);
2640 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2641 bitmap_release_region(pctrl->tint_slot, i, get_order(1));
2642 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
2643 pctrl->hwirq[i] = 0;
2644 break;
2645 }
2646 }
2647 }
2648 irq_domain_free_irqs_common(domain, virq, nr_irqs);
2649 }
2650
rzg2l_init_irq_valid_mask(struct gpio_chip * gc,unsigned long * valid_mask,unsigned int ngpios)2651 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
2652 unsigned long *valid_mask,
2653 unsigned int ngpios)
2654 {
2655 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
2656 struct gpio_chip *chip = &pctrl->gpio_chip;
2657 unsigned int offset;
2658
2659 /* Forbid unused lines to be mapped as IRQs */
2660 for (offset = 0; offset < chip->ngpio; offset++) {
2661 u32 port, bit;
2662
2663 port = offset / 8;
2664 bit = offset % 8;
2665
2666 if (port >= pctrl->data->n_ports ||
2667 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK,
2668 pctrl->data->port_pin_configs[port])))
2669 clear_bit(offset, valid_mask);
2670 }
2671 }
2672
rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl * pctrl)2673 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
2674 {
2675 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2676 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache;
2677
2678 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL);
2679 if (!cache)
2680 return -ENOMEM;
2681
2682 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL);
2683 if (!dedicated_cache)
2684 return -ENOMEM;
2685
2686 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL);
2687 if (!cache->p)
2688 return -ENOMEM;
2689
2690 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL);
2691 if (!cache->pm)
2692 return -ENOMEM;
2693
2694 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL);
2695 if (!cache->pmc)
2696 return -ENOMEM;
2697
2698 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL);
2699 if (!cache->pfc)
2700 return -ENOMEM;
2701
2702 for (u8 i = 0; i < 2; i++) {
2703 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
2704
2705 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]),
2706 GFP_KERNEL);
2707 if (!cache->iolh[i])
2708 return -ENOMEM;
2709
2710 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]),
2711 GFP_KERNEL);
2712 if (!cache->ien[i])
2713 return -ENOMEM;
2714
2715 /* Allocate dedicated cache. */
2716 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
2717 sizeof(*dedicated_cache->iolh[i]),
2718 GFP_KERNEL);
2719 if (!dedicated_cache->iolh[i])
2720 return -ENOMEM;
2721
2722 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
2723 sizeof(*dedicated_cache->ien[i]),
2724 GFP_KERNEL);
2725 if (!dedicated_cache->ien[i])
2726 return -ENOMEM;
2727 }
2728
2729 pctrl->cache = cache;
2730 pctrl->dedicated_cache = dedicated_cache;
2731
2732 return 0;
2733 }
2734
rzg2l_gpio_register(struct rzg2l_pinctrl * pctrl)2735 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
2736 {
2737 struct device_node *np = pctrl->dev->of_node;
2738 struct gpio_chip *chip = &pctrl->gpio_chip;
2739 const char *name = dev_name(pctrl->dev);
2740 struct irq_domain *parent_domain;
2741 struct of_phandle_args of_args;
2742 struct device_node *parent_np;
2743 struct gpio_irq_chip *girq;
2744 int ret;
2745
2746 parent_np = of_irq_find_parent(np);
2747 if (!parent_np)
2748 return -ENXIO;
2749
2750 parent_domain = irq_find_host(parent_np);
2751 of_node_put(parent_np);
2752 if (!parent_domain)
2753 return -EPROBE_DEFER;
2754
2755 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
2756 if (ret)
2757 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n");
2758
2759 of_node_put(of_args.np);
2760
2761 if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
2762 of_args.args[2] != pctrl->data->n_port_pins)
2763 return dev_err_probe(pctrl->dev, -EINVAL,
2764 "gpio-ranges does not match selected SOC\n");
2765
2766 chip->names = pctrl->data->port_pins;
2767 chip->request = rzg2l_gpio_request;
2768 chip->free = rzg2l_gpio_free;
2769 chip->get_direction = rzg2l_gpio_get_direction;
2770 chip->direction_input = rzg2l_gpio_direction_input;
2771 chip->direction_output = rzg2l_gpio_direction_output;
2772 chip->get = rzg2l_gpio_get;
2773 chip->set = rzg2l_gpio_set;
2774 chip->label = name;
2775 chip->parent = pctrl->dev;
2776 chip->owner = THIS_MODULE;
2777 chip->base = -1;
2778 chip->ngpio = of_args.args[2];
2779
2780 girq = &chip->irq;
2781 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
2782 girq->fwnode = dev_fwnode(pctrl->dev);
2783 girq->parent_domain = parent_domain;
2784 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
2785 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
2786 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
2787 girq->init_valid_mask = rzg2l_init_irq_valid_mask;
2788
2789 pctrl->gpio_range.id = 0;
2790 pctrl->gpio_range.pin_base = 0;
2791 pctrl->gpio_range.base = 0;
2792 pctrl->gpio_range.npins = chip->ngpio;
2793 pctrl->gpio_range.name = chip->label;
2794 pctrl->gpio_range.gc = chip;
2795 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
2796 if (ret)
2797 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n");
2798
2799 dev_dbg(pctrl->dev, "Registered gpio controller\n");
2800
2801 return 0;
2802 }
2803
rzg2l_pinctrl_register(struct rzg2l_pinctrl * pctrl)2804 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
2805 {
2806 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2807 struct pinctrl_pin_desc *pins;
2808 unsigned int i, j;
2809 u64 *pin_data;
2810 int ret;
2811
2812 pctrl->desc.name = DRV_NAME;
2813 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
2814 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
2815 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
2816 pctrl->desc.confops = &rzg2l_pinctrl_confops;
2817 pctrl->desc.owner = THIS_MODULE;
2818 if (pctrl->data->num_custom_params) {
2819 pctrl->desc.num_custom_params = pctrl->data->num_custom_params;
2820 pctrl->desc.custom_params = pctrl->data->custom_params;
2821 #ifdef CONFIG_DEBUG_FS
2822 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items;
2823 #endif
2824 }
2825
2826 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
2827 if (!pins)
2828 return -ENOMEM;
2829
2830 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
2831 sizeof(*pin_data), GFP_KERNEL);
2832 if (!pin_data)
2833 return -ENOMEM;
2834
2835 pctrl->pins = pins;
2836 pctrl->desc.pins = pins;
2837
2838 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
2839 pins[i].number = i;
2840 pins[i].name = pctrl->data->port_pins[i];
2841 if (i && !(i % RZG2L_PINS_PER_PORT))
2842 j++;
2843 pin_data[i] = pctrl->data->port_pin_configs[j];
2844 if (pin_data[i] & RZG2L_VARIABLE_CFG)
2845 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
2846 pin_data[i],
2847 j,
2848 i % RZG2L_PINS_PER_PORT);
2849 pins[i].drv_data = &pin_data[i];
2850 }
2851
2852 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
2853 unsigned int index = pctrl->data->n_port_pins + i;
2854
2855 pins[index].number = index;
2856 pins[index].name = pctrl->data->dedicated_pins[i].name;
2857 pin_data[index] = pctrl->data->dedicated_pins[i].config;
2858 pins[index].drv_data = &pin_data[index];
2859 }
2860
2861 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings),
2862 GFP_KERNEL);
2863 if (!pctrl->settings)
2864 return -ENOMEM;
2865
2866 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {
2867 if (pin_data[i] & PIN_CFG_SOFT_PS) {
2868 pctrl->settings[i].power_source = 3300;
2869 } else {
2870 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]);
2871 if (ret < 0)
2872 continue;
2873 pctrl->settings[i].power_source = ret;
2874 }
2875 }
2876
2877 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl);
2878 if (ret)
2879 return ret;
2880
2881 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
2882 &pctrl->pctl);
2883 if (ret)
2884 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n");
2885
2886 ret = pinctrl_enable(pctrl->pctl);
2887 if (ret)
2888 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");
2889
2890 ret = rzg2l_gpio_register(pctrl);
2891 if (ret)
2892 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n");
2893
2894 return 0;
2895 }
2896
rzg2l_pinctrl_probe(struct platform_device * pdev)2897 static int rzg2l_pinctrl_probe(struct platform_device *pdev)
2898 {
2899 struct rzg2l_pinctrl *pctrl;
2900 int ret;
2901
2902 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >
2903 ARRAY_SIZE(rzg2l_gpio_names));
2904
2905 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
2906 ARRAY_SIZE(rzg2l_gpio_names));
2907
2908 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
2909 ARRAY_SIZE(rzg2l_gpio_names));
2910
2911 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
2912 ARRAY_SIZE(rzg3e_gpio_names));
2913
2914 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
2915 ARRAY_SIZE(rzv2h_gpio_names));
2916
2917 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
2918 if (!pctrl)
2919 return -ENOMEM;
2920
2921 pctrl->dev = &pdev->dev;
2922
2923 pctrl->data = of_device_get_match_data(&pdev->dev);
2924 if (!pctrl->data)
2925 return -EINVAL;
2926
2927 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
2928 if (IS_ERR(pctrl->base))
2929 return PTR_ERR(pctrl->base);
2930
2931 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL);
2932 if (IS_ERR(pctrl->clk)) {
2933 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk),
2934 "failed to enable GPIO clk\n");
2935 }
2936
2937 spin_lock_init(&pctrl->lock);
2938 spin_lock_init(&pctrl->bitmap_lock);
2939 mutex_init(&pctrl->mutex);
2940 atomic_set(&pctrl->wakeup_path, 0);
2941
2942 platform_set_drvdata(pdev, pctrl);
2943
2944 ret = rzg2l_pinctrl_register(pctrl);
2945 if (ret)
2946 return ret;
2947
2948 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
2949 return 0;
2950 }
2951
rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl * pctrl,bool suspend)2952 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
2953 {
2954 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2955 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2956
2957 for (u32 port = 0; port < nports; port++) {
2958 bool has_iolh, has_ien;
2959 u32 off, caps;
2960 u8 pincnt;
2961 u64 cfg;
2962
2963 cfg = pctrl->data->port_pin_configs[port];
2964 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
2965 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg));
2966
2967 caps = FIELD_GET(PIN_CFG_MASK, cfg);
2968 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
2969 has_ien = !!(caps & PIN_CFG_IEN);
2970
2971 if (suspend)
2972 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
2973
2974 /*
2975 * Now cache the registers or set them in the order suggested by
2976 * HW manual (section "Operation for GPIO Function").
2977 */
2978 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]);
2979 if (has_iolh) {
2980 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
2981 cache->iolh[0][port]);
2982 if (pincnt >= 4) {
2983 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4,
2984 cache->iolh[1][port]);
2985 }
2986 }
2987
2988 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);
2989 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);
2990
2991 if (has_ien) {
2992 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
2993 cache->ien[0][port]);
2994 if (pincnt >= 4) {
2995 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4,
2996 cache->ien[1][port]);
2997 }
2998 }
2999 }
3000 }
3001
rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl * pctrl,bool suspend)3002 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
3003 {
3004 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
3005 u32 caps;
3006 u32 i;
3007
3008 /*
3009 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same
3010 * port offset are close together.
3011 */
3012 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
3013 bool has_iolh, has_ien;
3014 u32 off, next_off = 0;
3015 u64 cfg, next_cfg;
3016 u8 pincnt;
3017
3018 cfg = pctrl->data->dedicated_pins[i].config;
3019 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
3020 if (i + 1 < pctrl->data->n_dedicated_pins) {
3021 next_cfg = pctrl->data->dedicated_pins[i + 1].config;
3022 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg);
3023 }
3024
3025 if (off == next_off) {
3026 /* Gather caps of all port pins. */
3027 caps |= FIELD_GET(PIN_CFG_MASK, cfg);
3028 continue;
3029 }
3030
3031 /* And apply them in a single shot. */
3032 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
3033 has_ien = !!(caps & PIN_CFG_IEN);
3034 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));
3035
3036 if (has_iolh) {
3037 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
3038 cache->iolh[0][i]);
3039 }
3040 if (has_ien) {
3041 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
3042 cache->ien[0][i]);
3043 }
3044
3045 if (pincnt >= 4) {
3046 if (has_iolh) {
3047 RZG2L_PCTRL_REG_ACCESS32(suspend,
3048 pctrl->base + IOLH(off) + 4,
3049 cache->iolh[1][i]);
3050 }
3051 if (has_ien) {
3052 RZG2L_PCTRL_REG_ACCESS32(suspend,
3053 pctrl->base + IEN(off) + 4,
3054 cache->ien[1][i]);
3055 }
3056 }
3057 caps = 0;
3058 }
3059 }
3060
rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl * pctrl)3061 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
3062 {
3063 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
3064 unsigned long flags;
3065
3066 spin_lock_irqsave(&pctrl->lock, flags);
3067 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
3068
3069 /* Restore port registers. */
3070 for (u32 port = 0; port < nports; port++) {
3071 unsigned long pinmap;
3072 u8 pmc = 0, max_pin;
3073 u32 off, pfc = 0;
3074 u64 cfg;
3075 u16 pm;
3076 u8 pin;
3077
3078 cfg = pctrl->data->port_pin_configs[port];
3079 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
3080 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
3081 max_pin = fls(pinmap);
3082
3083 pm = readw(pctrl->base + PM(off));
3084 for_each_set_bit(pin, &pinmap, max_pin) {
3085 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3086
3087 /* Nothing to do if PFC was not configured before. */
3088 if (!(cache->pmc[port] & BIT(pin)))
3089 continue;
3090
3091 /* Set pin to 'Non-use (Hi-Z input protection)' */
3092 pm &= ~(PM_MASK << (pin * 2));
3093 writew(pm, pctrl->base + PM(off));
3094
3095 /* Temporarily switch to GPIO mode with PMC register */
3096 pmc &= ~BIT(pin);
3097 writeb(pmc, pctrl->base + PMC(off));
3098
3099 /* Select Pin function mode. */
3100 pfc &= ~(PFC_MASK << (pin * 4));
3101 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
3102 writel(pfc, pctrl->base + PFC(off));
3103
3104 /* Switch to Peripheral pin function. */
3105 pmc |= BIT(pin);
3106 writeb(pmc, pctrl->base + PMC(off));
3107 }
3108 }
3109
3110 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
3111 spin_unlock_irqrestore(&pctrl->lock, flags);
3112 }
3113
rzg2l_pinctrl_suspend_noirq(struct device * dev)3114 static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
3115 {
3116 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
3117 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
3118 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
3119 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3120
3121 rzg2l_pinctrl_pm_setup_regs(pctrl, true);
3122 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true);
3123
3124 for (u8 i = 0; i < 2; i++) {
3125 if (regs->sd_ch)
3126 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
3127 if (regs->eth_poc)
3128 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
3129 }
3130
3131 cache->qspi = readb(pctrl->base + QSPI);
3132 cache->eth_mode = readb(pctrl->base + ETH_MODE);
3133
3134 if (!atomic_read(&pctrl->wakeup_path))
3135 clk_disable_unprepare(pctrl->clk);
3136 else
3137 device_set_wakeup_path(dev);
3138
3139 return 0;
3140 }
3141
rzg2l_pinctrl_resume_noirq(struct device * dev)3142 static int rzg2l_pinctrl_resume_noirq(struct device *dev)
3143 {
3144 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
3145 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
3146 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
3147 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3148 int ret;
3149
3150 if (!atomic_read(&pctrl->wakeup_path)) {
3151 ret = clk_prepare_enable(pctrl->clk);
3152 if (ret)
3153 return ret;
3154 }
3155
3156 writeb(cache->qspi, pctrl->base + QSPI);
3157 writeb(cache->eth_mode, pctrl->base + ETH_MODE);
3158 for (u8 i = 0; i < 2; i++) {
3159 if (regs->sd_ch)
3160 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
3161 if (regs->eth_poc)
3162 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i));
3163 }
3164
3165 rzg2l_pinctrl_pm_setup_pfc(pctrl);
3166 rzg2l_pinctrl_pm_setup_regs(pctrl, false);
3167 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false);
3168 rzg2l_gpio_irq_restore(pctrl);
3169
3170 return 0;
3171 }
3172
rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl * pctrl,bool lock)3173 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
3174 {
3175 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
3176
3177 if (lock) {
3178 /* Set the PWPR register to be write-protected */
3179 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
3180 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
3181 } else {
3182 /* Set the PWPR register to allow PFC register to write */
3183 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
3184 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
3185 }
3186 }
3187
rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl * pctrl,bool lock)3188 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
3189 {
3190 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
3191 u8 pwpr;
3192
3193 if (lock) {
3194 /* Set the PWPR register to be write-protected */
3195 pwpr = readb(pctrl->base + regs->pwpr);
3196 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
3197 } else {
3198 /* Set the PWPR register to allow PFC and PMC register to write */
3199 pwpr = readb(pctrl->base + regs->pwpr);
3200 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr);
3201 }
3202 }
3203
3204 static const struct rzg2l_hwcfg rzg2l_hwcfg = {
3205 .regs = {
3206 .pwpr = 0x3014,
3207 .sd_ch = 0x3000,
3208 .eth_poc = 0x300c,
3209 },
3210 .iolh_groupa_ua = {
3211 /* 3v3 power source */
3212 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
3213 },
3214 .iolh_groupb_oi = { 100, 66, 50, 33, },
3215 .tint_start_index = 9,
3216 .oen_max_pin = 0,
3217 };
3218
3219 static const struct rzg2l_hwcfg rzg3s_hwcfg = {
3220 .regs = {
3221 .pwpr = 0x3000,
3222 .sd_ch = 0x3004,
3223 .eth_poc = 0x3010,
3224 },
3225 .iolh_groupa_ua = {
3226 /* 1v8 power source */
3227 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
3228 /* 3v3 power source */
3229 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
3230 },
3231 .iolh_groupb_ua = {
3232 /* 1v8 power source */
3233 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
3234 /* 3v3 power source */
3235 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
3236 },
3237 .iolh_groupc_ua = {
3238 /* 1v8 power source */
3239 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
3240 /* 2v5 source */
3241 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
3242 /* 3v3 power source */
3243 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
3244 },
3245 .tint_start_index = 9,
3246 .drive_strength_ua = true,
3247 .func_base = 1,
3248 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
3249 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */
3250 };
3251
3252 static const struct rzg2l_hwcfg rzv2h_hwcfg = {
3253 .regs = {
3254 .pwpr = 0x3c04,
3255 },
3256 .tint_start_index = 17,
3257 };
3258
3259 static struct rzg2l_pinctrl_data r9a07g043_data = {
3260 .port_pins = rzg2l_gpio_names,
3261 .port_pin_configs = r9a07g043_gpio_configs,
3262 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
3263 .dedicated_pins = rzg2l_dedicated_pins.common,
3264 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
3265 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
3266 .hwcfg = &rzg2l_hwcfg,
3267 #ifdef CONFIG_RISCV
3268 .variable_pin_cfg = r9a07g043f_variable_pin_cfg,
3269 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
3270 #endif
3271 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3272 .pmc_writeb = &rzg2l_pmc_writeb,
3273 .oen_read = &rzg2l_read_oen,
3274 .oen_write = &rzg2l_write_oen,
3275 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3276 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3277 };
3278
3279 static struct rzg2l_pinctrl_data r9a07g044_data = {
3280 .port_pins = rzg2l_gpio_names,
3281 .port_pin_configs = r9a07g044_gpio_configs,
3282 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),
3283 .dedicated_pins = rzg2l_dedicated_pins.common,
3284 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,
3285 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
3286 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
3287 .hwcfg = &rzg2l_hwcfg,
3288 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3289 .pmc_writeb = &rzg2l_pmc_writeb,
3290 .oen_read = &rzg2l_read_oen,
3291 .oen_write = &rzg2l_write_oen,
3292 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3293 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3294 };
3295
3296 static struct rzg2l_pinctrl_data r9a08g045_data = {
3297 .port_pins = rzg2l_gpio_names,
3298 .port_pin_configs = r9a08g045_gpio_configs,
3299 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
3300 .dedicated_pins = rzg3s_dedicated_pins,
3301 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
3302 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
3303 .hwcfg = &rzg3s_hwcfg,
3304 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3305 .pmc_writeb = &rzg2l_pmc_writeb,
3306 .oen_read = &rzg3s_oen_read,
3307 .oen_write = &rzg3s_oen_write,
3308 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3309 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3310 };
3311
3312 static struct rzg2l_pinctrl_data r9a09g047_data = {
3313 .port_pins = rzg3e_gpio_names,
3314 .port_pin_configs = r9a09g047_gpio_configs,
3315 .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),
3316 .dedicated_pins = rzg3e_dedicated_pins,
3317 .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
3318 .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
3319 .hwcfg = &rzv2h_hwcfg,
3320 .variable_pin_cfg = r9a09g047_variable_pin_cfg,
3321 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
3322 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3323 .custom_params = renesas_rzv2h_custom_bindings,
3324 #ifdef CONFIG_DEBUG_FS
3325 .custom_conf_items = renesas_rzv2h_conf_items,
3326 #endif
3327 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3328 .pmc_writeb = &rzv2h_pmc_writeb,
3329 .oen_read = &rzv2h_oen_read,
3330 .oen_write = &rzv2h_oen_write,
3331 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3332 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3333 };
3334
3335 static struct rzg2l_pinctrl_data r9a09g057_data = {
3336 .port_pins = rzv2h_gpio_names,
3337 .port_pin_configs = r9a09g057_gpio_configs,
3338 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
3339 .dedicated_pins = rzv2h_dedicated_pins,
3340 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
3341 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),
3342 .hwcfg = &rzv2h_hwcfg,
3343 .variable_pin_cfg = r9a09g057_variable_pin_cfg,
3344 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
3345 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3346 .custom_params = renesas_rzv2h_custom_bindings,
3347 #ifdef CONFIG_DEBUG_FS
3348 .custom_conf_items = renesas_rzv2h_conf_items,
3349 #endif
3350 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3351 .pmc_writeb = &rzv2h_pmc_writeb,
3352 .oen_read = &rzv2h_oen_read,
3353 .oen_write = &rzv2h_oen_write,
3354 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3355 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3356 };
3357
3358 static const struct of_device_id rzg2l_pinctrl_of_table[] = {
3359 {
3360 .compatible = "renesas,r9a07g043-pinctrl",
3361 .data = &r9a07g043_data,
3362 },
3363 {
3364 .compatible = "renesas,r9a07g044-pinctrl",
3365 .data = &r9a07g044_data,
3366 },
3367 {
3368 .compatible = "renesas,r9a08g045-pinctrl",
3369 .data = &r9a08g045_data,
3370 },
3371 {
3372 .compatible = "renesas,r9a09g047-pinctrl",
3373 .data = &r9a09g047_data,
3374 },
3375 {
3376 .compatible = "renesas,r9a09g057-pinctrl",
3377 .data = &r9a09g057_data,
3378 },
3379 { /* sentinel */ }
3380 };
3381
3382 static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = {
3383 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq)
3384 };
3385
3386 static struct platform_driver rzg2l_pinctrl_driver = {
3387 .driver = {
3388 .name = DRV_NAME,
3389 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
3390 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops),
3391 .suppress_bind_attrs = true,
3392 },
3393 .probe = rzg2l_pinctrl_probe,
3394 };
3395
rzg2l_pinctrl_init(void)3396 static int __init rzg2l_pinctrl_init(void)
3397 {
3398 return platform_driver_register(&rzg2l_pinctrl_driver);
3399 }
3400 core_initcall(rzg2l_pinctrl_init);
3401
3402 MODULE_AUTHOR("Lad Prabhakar <[email protected]>");
3403 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
3404