1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
4 *
5 * Copyright (C) 2018 Chris Brandt
6 */
7
8 /*
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
10 * family.
11 */
12
13 #include <linux/bitops.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/of.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22
23 #include "../core.h"
24 #include "../pinmux.h"
25
26 #define DRIVER_NAME "pinctrl-rza2"
27
28 #define RZA2_PINS_PER_PORT 8
29 #define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
30 #define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
31
32 /*
33 * Use 16 lower bits [15:0] for pin identifier
34 * Use 16 higher bits [31:16] for pin mux function
35 */
36 #define MUX_PIN_ID_MASK GENMASK(15, 0)
37 #define MUX_FUNC_MASK GENMASK(31, 16)
38 #define MUX_FUNC_OFFS 16
39 #define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
40
41 static const char port_names[] = "0123456789ABCDEFGHJKLM";
42
43 struct rza2_pinctrl_priv {
44 struct device *dev;
45 void __iomem *base;
46
47 struct pinctrl_pin_desc *pins;
48 struct pinctrl_desc desc;
49 struct pinctrl_dev *pctl;
50 struct pinctrl_gpio_range gpio_range;
51 int npins;
52 struct mutex mutex; /* serialize adding groups and functions */
53 };
54
55 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
56 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
57 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
58 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
59 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
60 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
61
62 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
63 #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
64 #define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
65 #define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
66 #define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
67
68 #define RZA2_PDR_INPUT 0x02
69 #define RZA2_PDR_OUTPUT 0x03
70 #define RZA2_PDR_MASK 0x03
71
72 #define PWPR_B0WI BIT(7) /* Bit Write Disable */
73 #define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */
74 #define PFS_ISEL BIT(6) /* Interrupt Select */
75
rza2_set_pin_function(void __iomem * pfc_base,u8 port,u8 pin,u8 func)76 static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
77 u8 func)
78 {
79 u16 mask16;
80 u16 reg16;
81 u8 reg8;
82
83 /* Set pin to 'Non-use (Hi-z input protection)' */
84 reg16 = readw(pfc_base + RZA2_PDR(port));
85 mask16 = RZA2_PDR_MASK << (pin * 2);
86 reg16 &= ~mask16;
87 writew(reg16, pfc_base + RZA2_PDR(port));
88
89 /* Temporarily switch to GPIO */
90 reg8 = readb(pfc_base + RZA2_PMR(port));
91 reg8 &= ~BIT(pin);
92 writeb(reg8, pfc_base + RZA2_PMR(port));
93
94 /* PFS Register Write Protect : OFF */
95 writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
96 writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */
97
98 /* Set Pin function (interrupt disabled, ISEL=0) */
99 writeb(func, pfc_base + RZA2_PFS(port, pin));
100
101 /* PFS Register Write Protect : ON */
102 writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
103 writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
104
105 /* Port Mode : Peripheral module pin functions */
106 reg8 = readb(pfc_base + RZA2_PMR(port));
107 reg8 |= BIT(pin);
108 writeb(reg8, pfc_base + RZA2_PMR(port));
109 }
110
rza2_pin_to_gpio(void __iomem * pfc_base,unsigned int offset,u8 dir)111 static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
112 u8 dir)
113 {
114 u8 port = RZA2_PIN_ID_TO_PORT(offset);
115 u8 pin = RZA2_PIN_ID_TO_PIN(offset);
116 u16 mask16;
117 u16 reg16;
118
119 reg16 = readw(pfc_base + RZA2_PDR(port));
120 mask16 = RZA2_PDR_MASK << (pin * 2);
121 reg16 &= ~mask16;
122
123 if (dir)
124 reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
125 else
126 reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
127
128 writew(reg16, pfc_base + RZA2_PDR(port));
129 }
130
rza2_chip_get_direction(struct gpio_chip * chip,unsigned int offset)131 static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
132 {
133 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
134 u8 port = RZA2_PIN_ID_TO_PORT(offset);
135 u8 pin = RZA2_PIN_ID_TO_PIN(offset);
136 u16 reg16;
137
138 reg16 = readw(priv->base + RZA2_PDR(port));
139 reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
140
141 if (reg16 == RZA2_PDR_OUTPUT)
142 return GPIO_LINE_DIRECTION_OUT;
143
144 if (reg16 == RZA2_PDR_INPUT)
145 return GPIO_LINE_DIRECTION_IN;
146
147 /*
148 * This GPIO controller has a default Hi-Z state that is not input or
149 * output, so force the pin to input now.
150 */
151 rza2_pin_to_gpio(priv->base, offset, 1);
152
153 return GPIO_LINE_DIRECTION_IN;
154 }
155
rza2_chip_direction_input(struct gpio_chip * chip,unsigned int offset)156 static int rza2_chip_direction_input(struct gpio_chip *chip,
157 unsigned int offset)
158 {
159 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
160
161 rza2_pin_to_gpio(priv->base, offset, 1);
162
163 return 0;
164 }
165
rza2_chip_get(struct gpio_chip * chip,unsigned int offset)166 static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
167 {
168 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
169 u8 port = RZA2_PIN_ID_TO_PORT(offset);
170 u8 pin = RZA2_PIN_ID_TO_PIN(offset);
171
172 return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
173 }
174
rza2_chip_set(struct gpio_chip * chip,unsigned int offset,int value)175 static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
176 int value)
177 {
178 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
179 u8 port = RZA2_PIN_ID_TO_PORT(offset);
180 u8 pin = RZA2_PIN_ID_TO_PIN(offset);
181 u8 new_value;
182
183 new_value = readb(priv->base + RZA2_PODR(port));
184
185 if (value)
186 new_value |= BIT(pin);
187 else
188 new_value &= ~BIT(pin);
189
190 writeb(new_value, priv->base + RZA2_PODR(port));
191 }
192
rza2_chip_direction_output(struct gpio_chip * chip,unsigned int offset,int val)193 static int rza2_chip_direction_output(struct gpio_chip *chip,
194 unsigned int offset, int val)
195 {
196 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
197
198 rza2_chip_set(chip, offset, val);
199 rza2_pin_to_gpio(priv->base, offset, 0);
200
201 return 0;
202 }
203
204 static const char * const rza2_gpio_names[] = {
205 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
206 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
207 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
208 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
209 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
210 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
211 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
212 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
213 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
214 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
215 "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
216 "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
217 "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
218 "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
219 "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
220 "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
221 "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
222 "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
223 /* port I does not exist */
224 "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
225 "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
226 "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
227 "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
228 };
229
230 static struct gpio_chip chip = {
231 .names = rza2_gpio_names,
232 .base = -1,
233 .request = pinctrl_gpio_request,
234 .free = pinctrl_gpio_free,
235 .get_direction = rza2_chip_get_direction,
236 .direction_input = rza2_chip_direction_input,
237 .direction_output = rza2_chip_direction_output,
238 .get = rza2_chip_get,
239 .set = rza2_chip_set,
240 };
241
rza2_gpio_register(struct rza2_pinctrl_priv * priv)242 static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
243 {
244 struct device_node *np = priv->dev->of_node;
245 struct of_phandle_args of_args;
246 int ret;
247
248 chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
249 chip.parent = priv->dev;
250 chip.ngpio = priv->npins;
251
252 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
253 &of_args);
254 if (ret) {
255 dev_err(priv->dev, "Unable to parse gpio-ranges\n");
256 return ret;
257 }
258
259 of_node_put(of_args.np);
260
261 if ((of_args.args[0] != 0) ||
262 (of_args.args[1] != 0) ||
263 (of_args.args[2] != priv->npins)) {
264 dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
265 return -EINVAL;
266 }
267 priv->gpio_range.id = 0;
268 priv->gpio_range.pin_base = priv->gpio_range.base = 0;
269 priv->gpio_range.npins = priv->npins;
270 priv->gpio_range.name = chip.label;
271 priv->gpio_range.gc = &chip;
272
273 /* Register our gpio chip with gpiolib */
274 ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
275 if (ret)
276 return ret;
277
278 /* Register pin range with pinctrl core */
279 pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
280
281 dev_dbg(priv->dev, "Registered gpio controller\n");
282
283 return 0;
284 }
285
rza2_pinctrl_register(struct rza2_pinctrl_priv * priv)286 static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
287 {
288 struct pinctrl_pin_desc *pins;
289 unsigned int i;
290 int ret;
291
292 pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
293 if (!pins)
294 return -ENOMEM;
295
296 priv->pins = pins;
297 priv->desc.pins = pins;
298 priv->desc.npins = priv->npins;
299
300 for (i = 0; i < priv->npins; i++) {
301 pins[i].number = i;
302 pins[i].name = rza2_gpio_names[i];
303 }
304
305 ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
306 &priv->pctl);
307 if (ret) {
308 dev_err(priv->dev, "pinctrl registration failed\n");
309 return ret;
310 }
311
312 ret = pinctrl_enable(priv->pctl);
313 if (ret) {
314 dev_err(priv->dev, "pinctrl enable failed\n");
315 return ret;
316 }
317
318 ret = rza2_gpio_register(priv);
319 if (ret) {
320 dev_err(priv->dev, "GPIO registration failed\n");
321 return ret;
322 }
323
324 return 0;
325 }
326
327 /*
328 * For each DT node, create a single pin mapping. That pin mapping will only
329 * contain a single group of pins, and that group of pins will only have a
330 * single function that can be selected.
331 */
rza2_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)332 static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
333 struct device_node *np,
334 struct pinctrl_map **map,
335 unsigned int *num_maps)
336 {
337 struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
338 unsigned int *pins, *psel_val;
339 int i, ret, npins, gsel, fsel;
340 struct property *of_pins;
341 const char **pin_fn;
342
343 /* Find out how many pins to map */
344 of_pins = of_find_property(np, "pinmux", NULL);
345 if (!of_pins) {
346 dev_info(priv->dev, "Missing pinmux property\n");
347 return -ENOENT;
348 }
349 npins = of_pins->length / sizeof(u32);
350
351 pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
352 psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
353 GFP_KERNEL);
354 pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
355 if (!pins || !psel_val || !pin_fn)
356 return -ENOMEM;
357
358 /* Collect pin locations and mux settings from DT properties */
359 for (i = 0; i < npins; ++i) {
360 u32 value;
361
362 ret = of_property_read_u32_index(np, "pinmux", i, &value);
363 if (ret)
364 return ret;
365 pins[i] = value & MUX_PIN_ID_MASK;
366 psel_val[i] = MUX_FUNC(value);
367 }
368
369 mutex_lock(&priv->mutex);
370
371 /* Register a single pin group listing all the pins we read from DT */
372 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
373 if (gsel < 0) {
374 ret = gsel;
375 goto unlock;
376 }
377
378 /*
379 * Register a single group function where the 'data' is an array PSEL
380 * register values read from DT.
381 */
382 pin_fn[0] = np->name;
383 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
384 psel_val);
385 if (fsel < 0) {
386 ret = fsel;
387 goto remove_group;
388 }
389
390 dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
391
392 /* Create map where to retrieve function and mux settings from */
393 *num_maps = 0;
394 *map = kzalloc(sizeof(**map), GFP_KERNEL);
395 if (!*map) {
396 ret = -ENOMEM;
397 goto remove_function;
398 }
399
400 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
401 (*map)->data.mux.group = np->name;
402 (*map)->data.mux.function = np->name;
403 *num_maps = 1;
404
405 mutex_unlock(&priv->mutex);
406
407 return 0;
408
409 remove_function:
410 pinmux_generic_remove_function(pctldev, fsel);
411
412 remove_group:
413 pinctrl_generic_remove_group(pctldev, gsel);
414
415 unlock:
416 mutex_unlock(&priv->mutex);
417
418 dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
419
420 return ret;
421 }
422
rza2_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned int num_maps)423 static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
424 struct pinctrl_map *map, unsigned int num_maps)
425 {
426 kfree(map);
427 }
428
429 static const struct pinctrl_ops rza2_pinctrl_ops = {
430 .get_groups_count = pinctrl_generic_get_group_count,
431 .get_group_name = pinctrl_generic_get_group_name,
432 .get_group_pins = pinctrl_generic_get_group_pins,
433 .dt_node_to_map = rza2_dt_node_to_map,
434 .dt_free_map = rza2_dt_free_map,
435 };
436
rza2_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)437 static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
438 unsigned int group)
439 {
440 struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
441 struct function_desc *func;
442 unsigned int i, *psel_val;
443 struct group_desc *grp;
444
445 grp = pinctrl_generic_get_group(pctldev, group);
446 if (!grp)
447 return -EINVAL;
448
449 func = pinmux_generic_get_function(pctldev, selector);
450 if (!func)
451 return -EINVAL;
452
453 psel_val = func->data;
454
455 for (i = 0; i < grp->grp.npins; ++i) {
456 dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
457 port_names[RZA2_PIN_ID_TO_PORT(grp->grp.pins[i])],
458 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
459 psel_val[i]);
460 rza2_set_pin_function(
461 priv->base,
462 RZA2_PIN_ID_TO_PORT(grp->grp.pins[i]),
463 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
464 psel_val[i]);
465 }
466
467 return 0;
468 }
469
470 static const struct pinmux_ops rza2_pinmux_ops = {
471 .get_functions_count = pinmux_generic_get_function_count,
472 .get_function_name = pinmux_generic_get_function_name,
473 .get_function_groups = pinmux_generic_get_function_groups,
474 .set_mux = rza2_set_mux,
475 .strict = true,
476 };
477
rza2_pinctrl_probe(struct platform_device * pdev)478 static int rza2_pinctrl_probe(struct platform_device *pdev)
479 {
480 struct rza2_pinctrl_priv *priv;
481 int ret;
482
483 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
484 if (!priv)
485 return -ENOMEM;
486
487 priv->dev = &pdev->dev;
488
489 priv->base = devm_platform_ioremap_resource(pdev, 0);
490 if (IS_ERR(priv->base))
491 return PTR_ERR(priv->base);
492
493 mutex_init(&priv->mutex);
494
495 platform_set_drvdata(pdev, priv);
496
497 priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
498 RZA2_PINS_PER_PORT;
499
500 priv->desc.name = DRIVER_NAME;
501 priv->desc.pctlops = &rza2_pinctrl_ops;
502 priv->desc.pmxops = &rza2_pinmux_ops;
503 priv->desc.owner = THIS_MODULE;
504
505 ret = rza2_pinctrl_register(priv);
506 if (ret)
507 return ret;
508
509 dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
510 port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
511
512 return 0;
513 }
514
515 static const struct of_device_id rza2_pinctrl_of_match[] = {
516 { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
517 { /* sentinel */ }
518 };
519
520 static struct platform_driver rza2_pinctrl_driver = {
521 .driver = {
522 .name = DRIVER_NAME,
523 .of_match_table = rza2_pinctrl_of_match,
524 },
525 .probe = rza2_pinctrl_probe,
526 };
527
rza2_pinctrl_init(void)528 static int __init rza2_pinctrl_init(void)
529 {
530 return platform_driver_register(&rza2_pinctrl_driver);
531 }
532 core_initcall(rza2_pinctrl_init);
533
534 MODULE_AUTHOR("Chris Brandt <[email protected]>");
535 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
536