1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, Sony Mobile Communications AB.
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 */
6
7 #include <linux/gpio/driver.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
16 #include <linux/string_choices.h>
17
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22
23 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
24
25 #include "../core.h"
26 #include "../pinctrl-utils.h"
27
28 /* MPP registers */
29 #define SSBI_REG_ADDR_MPP_BASE 0x50
30 #define SSBI_REG_ADDR_MPP(n) (SSBI_REG_ADDR_MPP_BASE + n)
31
32 /* MPP Type: type */
33 #define PM8XXX_MPP_TYPE_D_INPUT 0
34 #define PM8XXX_MPP_TYPE_D_OUTPUT 1
35 #define PM8XXX_MPP_TYPE_D_BI_DIR 2
36 #define PM8XXX_MPP_TYPE_A_INPUT 3
37 #define PM8XXX_MPP_TYPE_A_OUTPUT 4
38 #define PM8XXX_MPP_TYPE_SINK 5
39 #define PM8XXX_MPP_TYPE_DTEST_SINK 6
40 #define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7
41
42 /* Digital Input: control */
43 #define PM8XXX_MPP_DIN_TO_INT 0
44 #define PM8XXX_MPP_DIN_TO_DBUS1 1
45 #define PM8XXX_MPP_DIN_TO_DBUS2 2
46 #define PM8XXX_MPP_DIN_TO_DBUS3 3
47
48 /* Digital Output: control */
49 #define PM8XXX_MPP_DOUT_CTRL_LOW 0
50 #define PM8XXX_MPP_DOUT_CTRL_HIGH 1
51 #define PM8XXX_MPP_DOUT_CTRL_MPP 2
52 #define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3
53
54 /* Bidirectional: control */
55 #define PM8XXX_MPP_BI_PULLUP_1KOHM 0
56 #define PM8XXX_MPP_BI_PULLUP_OPEN 1
57 #define PM8XXX_MPP_BI_PULLUP_10KOHM 2
58 #define PM8XXX_MPP_BI_PULLUP_30KOHM 3
59
60 /* Analog Output: control */
61 #define PM8XXX_MPP_AOUT_CTRL_DISABLE 0
62 #define PM8XXX_MPP_AOUT_CTRL_ENABLE 1
63 #define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2
64 #define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3
65
66 /* Current Sink: control */
67 #define PM8XXX_MPP_CS_CTRL_DISABLE 0
68 #define PM8XXX_MPP_CS_CTRL_ENABLE 1
69 #define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2
70 #define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3
71
72 /* DTEST Current Sink: control */
73 #define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0
74 #define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1
75 #define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2
76 #define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3
77
78 /* DTEST Digital Output: control */
79 #define PM8XXX_MPP_DTEST_DBUS1 0
80 #define PM8XXX_MPP_DTEST_DBUS2 1
81 #define PM8XXX_MPP_DTEST_DBUS3 2
82 #define PM8XXX_MPP_DTEST_DBUS4 3
83
84 /* custom pinconf parameters */
85 #define PM8XXX_CONFIG_AMUX (PIN_CONFIG_END + 1)
86 #define PM8XXX_CONFIG_DTEST_SELECTOR (PIN_CONFIG_END + 2)
87 #define PM8XXX_CONFIG_ALEVEL (PIN_CONFIG_END + 3)
88 #define PM8XXX_CONFIG_PAIRED (PIN_CONFIG_END + 4)
89
90 /**
91 * struct pm8xxx_pin_data - dynamic configuration for a pin
92 * @reg: address of the control register
93 * @mode: operating mode for the pin (digital, analog or current sink)
94 * @input: pin is input
95 * @output: pin is output
96 * @high_z: pin is floating
97 * @paired: mpp operates in paired mode
98 * @output_value: logical output value of the mpp
99 * @power_source: selected power source
100 * @dtest: DTEST route selector
101 * @amux: input muxing in analog mode
102 * @aout_level: selector of the output in analog mode
103 * @drive_strength: drive strength of the current sink
104 * @pullup: pull up value, when in digital bidirectional mode
105 */
106 struct pm8xxx_pin_data {
107 unsigned reg;
108
109 u8 mode;
110
111 bool input;
112 bool output;
113 bool high_z;
114 bool paired;
115 bool output_value;
116
117 u8 power_source;
118 u8 dtest;
119 u8 amux;
120 u8 aout_level;
121 u8 drive_strength;
122 unsigned pullup;
123 };
124
125 struct pm8xxx_mpp {
126 struct device *dev;
127 struct regmap *regmap;
128 struct pinctrl_dev *pctrl;
129 struct gpio_chip chip;
130
131 struct pinctrl_desc desc;
132 unsigned npins;
133 };
134
135 static const struct pinconf_generic_params pm8xxx_mpp_bindings[] = {
136 {"qcom,amux-route", PM8XXX_CONFIG_AMUX, 0},
137 {"qcom,analog-level", PM8XXX_CONFIG_ALEVEL, 0},
138 {"qcom,dtest", PM8XXX_CONFIG_DTEST_SELECTOR, 0},
139 {"qcom,paired", PM8XXX_CONFIG_PAIRED, 0},
140 };
141
142 #ifdef CONFIG_DEBUG_FS
143 static const struct pin_config_item pm8xxx_conf_items[] = {
144 PCONFDUMP(PM8XXX_CONFIG_AMUX, "analog mux", NULL, true),
145 PCONFDUMP(PM8XXX_CONFIG_ALEVEL, "analog level", NULL, true),
146 PCONFDUMP(PM8XXX_CONFIG_DTEST_SELECTOR, "dtest", NULL, true),
147 PCONFDUMP(PM8XXX_CONFIG_PAIRED, "paired", NULL, false),
148 };
149 #endif
150
151 #define PM8XXX_MAX_MPPS 12
152 #define PM8XXX_MPP_PHYSICAL_OFFSET 1
153
154 static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = {
155 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
156 "mpp9", "mpp10", "mpp11", "mpp12",
157 };
158
159 #define PM8XXX_MPP_DIGITAL 0
160 #define PM8XXX_MPP_ANALOG 1
161 #define PM8XXX_MPP_SINK 2
162
163 static const char * const pm8xxx_mpp_functions[] = {
164 "digital", "analog", "sink",
165 };
166
pm8xxx_mpp_update(struct pm8xxx_mpp * pctrl,struct pm8xxx_pin_data * pin)167 static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl,
168 struct pm8xxx_pin_data *pin)
169 {
170 unsigned level;
171 unsigned ctrl;
172 unsigned type;
173 int ret;
174 u8 val;
175
176 switch (pin->mode) {
177 case PM8XXX_MPP_DIGITAL:
178 if (pin->dtest) {
179 type = PM8XXX_MPP_TYPE_DTEST_OUTPUT;
180 ctrl = pin->dtest - 1;
181 } else if (pin->input && pin->output) {
182 type = PM8XXX_MPP_TYPE_D_BI_DIR;
183 if (pin->high_z)
184 ctrl = PM8XXX_MPP_BI_PULLUP_OPEN;
185 else if (pin->pullup == 600)
186 ctrl = PM8XXX_MPP_BI_PULLUP_1KOHM;
187 else if (pin->pullup == 10000)
188 ctrl = PM8XXX_MPP_BI_PULLUP_10KOHM;
189 else
190 ctrl = PM8XXX_MPP_BI_PULLUP_30KOHM;
191 } else if (pin->input) {
192 type = PM8XXX_MPP_TYPE_D_INPUT;
193 if (pin->dtest)
194 ctrl = pin->dtest;
195 else
196 ctrl = PM8XXX_MPP_DIN_TO_INT;
197 } else {
198 type = PM8XXX_MPP_TYPE_D_OUTPUT;
199 ctrl = !!pin->output_value;
200 if (pin->paired)
201 ctrl |= BIT(1);
202 }
203
204 level = pin->power_source;
205 break;
206 case PM8XXX_MPP_ANALOG:
207 if (pin->output) {
208 type = PM8XXX_MPP_TYPE_A_OUTPUT;
209 level = pin->aout_level;
210 ctrl = pin->output_value;
211 if (pin->paired)
212 ctrl |= BIT(1);
213 } else {
214 type = PM8XXX_MPP_TYPE_A_INPUT;
215 level = pin->amux;
216 ctrl = 0;
217 }
218 break;
219 case PM8XXX_MPP_SINK:
220 level = (pin->drive_strength / 5) - 1;
221 if (pin->dtest) {
222 type = PM8XXX_MPP_TYPE_DTEST_SINK;
223 ctrl = pin->dtest - 1;
224 } else {
225 type = PM8XXX_MPP_TYPE_SINK;
226 ctrl = pin->output_value;
227 if (pin->paired)
228 ctrl |= BIT(1);
229 }
230 break;
231 default:
232 return -EINVAL;
233 }
234
235 val = type << 5 | level << 2 | ctrl;
236 ret = regmap_write(pctrl->regmap, pin->reg, val);
237 if (ret)
238 dev_err(pctrl->dev, "failed to write register\n");
239
240 return ret;
241 }
242
pm8xxx_get_groups_count(struct pinctrl_dev * pctldev)243 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
244 {
245 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
246
247 return pctrl->npins;
248 }
249
pm8xxx_get_group_name(struct pinctrl_dev * pctldev,unsigned group)250 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
251 unsigned group)
252 {
253 return pm8xxx_groups[group];
254 }
255
256
pm8xxx_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)257 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
258 unsigned group,
259 const unsigned **pins,
260 unsigned *num_pins)
261 {
262 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
263
264 *pins = &pctrl->desc.pins[group].number;
265 *num_pins = 1;
266
267 return 0;
268 }
269
270 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
271 .get_groups_count = pm8xxx_get_groups_count,
272 .get_group_name = pm8xxx_get_group_name,
273 .get_group_pins = pm8xxx_get_group_pins,
274 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
275 .dt_free_map = pinctrl_utils_free_map,
276 };
277
pm8xxx_get_functions_count(struct pinctrl_dev * pctldev)278 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
279 {
280 return ARRAY_SIZE(pm8xxx_mpp_functions);
281 }
282
pm8xxx_get_function_name(struct pinctrl_dev * pctldev,unsigned function)283 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
284 unsigned function)
285 {
286 return pm8xxx_mpp_functions[function];
287 }
288
pm8xxx_get_function_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)289 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
290 unsigned function,
291 const char * const **groups,
292 unsigned * const num_groups)
293 {
294 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
295
296 *groups = pm8xxx_groups;
297 *num_groups = pctrl->npins;
298 return 0;
299 }
300
pm8xxx_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned function,unsigned group)301 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
302 unsigned function,
303 unsigned group)
304 {
305 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
306 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
307
308 pin->mode = function;
309 pm8xxx_mpp_update(pctrl, pin);
310
311 return 0;
312 }
313
314 static const struct pinmux_ops pm8xxx_pinmux_ops = {
315 .get_functions_count = pm8xxx_get_functions_count,
316 .get_function_name = pm8xxx_get_function_name,
317 .get_function_groups = pm8xxx_get_function_groups,
318 .set_mux = pm8xxx_pinmux_set_mux,
319 };
320
pm8xxx_pin_config_get(struct pinctrl_dev * pctldev,unsigned int offset,unsigned long * config)321 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
322 unsigned int offset,
323 unsigned long *config)
324 {
325 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
326 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
327 unsigned param = pinconf_to_config_param(*config);
328 unsigned arg;
329
330 switch (param) {
331 case PIN_CONFIG_BIAS_PULL_UP:
332 arg = pin->pullup;
333 break;
334 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
335 arg = pin->high_z;
336 break;
337 case PIN_CONFIG_INPUT_ENABLE:
338 arg = pin->input;
339 break;
340 case PIN_CONFIG_OUTPUT:
341 arg = pin->output_value;
342 break;
343 case PIN_CONFIG_POWER_SOURCE:
344 arg = pin->power_source;
345 break;
346 case PIN_CONFIG_DRIVE_STRENGTH:
347 arg = pin->drive_strength;
348 break;
349 case PM8XXX_CONFIG_DTEST_SELECTOR:
350 arg = pin->dtest;
351 break;
352 case PM8XXX_CONFIG_AMUX:
353 arg = pin->amux;
354 break;
355 case PM8XXX_CONFIG_ALEVEL:
356 arg = pin->aout_level;
357 break;
358 case PM8XXX_CONFIG_PAIRED:
359 arg = pin->paired;
360 break;
361 default:
362 return -EINVAL;
363 }
364
365 *config = pinconf_to_config_packed(param, arg);
366
367 return 0;
368 }
369
pm8xxx_pin_config_set(struct pinctrl_dev * pctldev,unsigned int offset,unsigned long * configs,unsigned num_configs)370 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
371 unsigned int offset,
372 unsigned long *configs,
373 unsigned num_configs)
374 {
375 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
376 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
377 unsigned param;
378 unsigned arg;
379 unsigned i;
380
381 for (i = 0; i < num_configs; i++) {
382 param = pinconf_to_config_param(configs[i]);
383 arg = pinconf_to_config_argument(configs[i]);
384
385 switch (param) {
386 case PIN_CONFIG_BIAS_PULL_UP:
387 pin->pullup = arg;
388 break;
389 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
390 pin->high_z = true;
391 break;
392 case PIN_CONFIG_INPUT_ENABLE:
393 pin->input = true;
394 break;
395 case PIN_CONFIG_OUTPUT:
396 pin->output = true;
397 pin->output_value = !!arg;
398 break;
399 case PIN_CONFIG_POWER_SOURCE:
400 pin->power_source = arg;
401 break;
402 case PIN_CONFIG_DRIVE_STRENGTH:
403 pin->drive_strength = arg;
404 break;
405 case PM8XXX_CONFIG_DTEST_SELECTOR:
406 pin->dtest = arg;
407 break;
408 case PM8XXX_CONFIG_AMUX:
409 pin->amux = arg;
410 break;
411 case PM8XXX_CONFIG_ALEVEL:
412 pin->aout_level = arg;
413 break;
414 case PM8XXX_CONFIG_PAIRED:
415 pin->paired = !!arg;
416 break;
417 default:
418 dev_err(pctrl->dev,
419 "unsupported config parameter: %x\n",
420 param);
421 return -EINVAL;
422 }
423 }
424
425 pm8xxx_mpp_update(pctrl, pin);
426
427 return 0;
428 }
429
430 static const struct pinconf_ops pm8xxx_pinconf_ops = {
431 .is_generic = true,
432 .pin_config_group_get = pm8xxx_pin_config_get,
433 .pin_config_group_set = pm8xxx_pin_config_set,
434 };
435
436 static const struct pinctrl_desc pm8xxx_pinctrl_desc = {
437 .name = "pm8xxx_mpp",
438 .pctlops = &pm8xxx_pinctrl_ops,
439 .pmxops = &pm8xxx_pinmux_ops,
440 .confops = &pm8xxx_pinconf_ops,
441 .owner = THIS_MODULE,
442 };
443
pm8xxx_mpp_direction_input(struct gpio_chip * chip,unsigned offset)444 static int pm8xxx_mpp_direction_input(struct gpio_chip *chip,
445 unsigned offset)
446 {
447 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
448 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
449
450 switch (pin->mode) {
451 case PM8XXX_MPP_DIGITAL:
452 pin->input = true;
453 break;
454 case PM8XXX_MPP_ANALOG:
455 pin->input = true;
456 pin->output = true;
457 break;
458 case PM8XXX_MPP_SINK:
459 return -EINVAL;
460 }
461
462 pm8xxx_mpp_update(pctrl, pin);
463
464 return 0;
465 }
466
pm8xxx_mpp_direction_output(struct gpio_chip * chip,unsigned offset,int value)467 static int pm8xxx_mpp_direction_output(struct gpio_chip *chip,
468 unsigned offset,
469 int value)
470 {
471 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
472 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
473
474 switch (pin->mode) {
475 case PM8XXX_MPP_DIGITAL:
476 pin->output = true;
477 break;
478 case PM8XXX_MPP_ANALOG:
479 pin->input = false;
480 pin->output = true;
481 break;
482 case PM8XXX_MPP_SINK:
483 pin->input = false;
484 pin->output = true;
485 break;
486 }
487
488 pm8xxx_mpp_update(pctrl, pin);
489
490 return 0;
491 }
492
pm8xxx_mpp_get(struct gpio_chip * chip,unsigned offset)493 static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset)
494 {
495 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
496 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
497 bool state;
498 int ret, irq;
499
500 if (!pin->input)
501 return !!pin->output_value;
502
503 irq = chip->to_irq(chip, offset);
504 if (irq < 0)
505 return irq;
506
507 ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, &state);
508 if (!ret)
509 ret = !!state;
510
511 return ret;
512 }
513
pm8xxx_mpp_set(struct gpio_chip * chip,unsigned offset,int value)514 static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int value)
515 {
516 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
517 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
518
519 pin->output_value = !!value;
520
521 pm8xxx_mpp_update(pctrl, pin);
522 }
523
pm8xxx_mpp_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpio_desc,u32 * flags)524 static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip,
525 const struct of_phandle_args *gpio_desc,
526 u32 *flags)
527 {
528 if (chip->of_gpio_n_cells < 2)
529 return -EINVAL;
530
531 if (flags)
532 *flags = gpio_desc->args[1];
533
534 return gpio_desc->args[0] - PM8XXX_MPP_PHYSICAL_OFFSET;
535 }
536
537
538 #ifdef CONFIG_DEBUG_FS
539
pm8xxx_mpp_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)540 static void pm8xxx_mpp_dbg_show_one(struct seq_file *s,
541 struct pinctrl_dev *pctldev,
542 struct gpio_chip *chip,
543 unsigned offset,
544 unsigned gpio)
545 {
546 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
547 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
548
549 static const char * const aout_lvls[] = {
550 "1v25", "1v25_2", "0v625", "0v3125", "mpp", "abus1", "abus2",
551 "abus3"
552 };
553
554 static const char * const amuxs[] = {
555 "amux5", "amux6", "amux7", "amux8", "amux9", "abus1", "abus2",
556 "abus3",
557 };
558
559 seq_printf(s, " mpp%-2d:", offset + PM8XXX_MPP_PHYSICAL_OFFSET);
560
561 switch (pin->mode) {
562 case PM8XXX_MPP_DIGITAL:
563 seq_puts(s, " digital ");
564 if (pin->dtest) {
565 seq_printf(s, "dtest%d\n", pin->dtest);
566 } else if (pin->input && pin->output) {
567 if (pin->high_z)
568 seq_puts(s, "bi-dir high-z");
569 else
570 seq_printf(s, "bi-dir %dOhm", pin->pullup);
571 } else if (pin->input) {
572 if (pin->dtest)
573 seq_printf(s, "in dtest%d", pin->dtest);
574 else
575 seq_puts(s, "in gpio");
576 } else if (pin->output) {
577 seq_puts(s, "out ");
578
579 if (!pin->paired) {
580 seq_puts(s, str_high_low(pin->output_value));
581 } else {
582 seq_puts(s, pin->output_value ?
583 "inverted" : "follow");
584 }
585 }
586 break;
587 case PM8XXX_MPP_ANALOG:
588 seq_puts(s, " analog ");
589 if (pin->output) {
590 seq_printf(s, "out %s ", aout_lvls[pin->aout_level]);
591 if (!pin->paired) {
592 seq_puts(s, str_high_low(pin->output_value));
593 } else {
594 seq_puts(s, pin->output_value ?
595 "inverted" : "follow");
596 }
597 } else {
598 seq_printf(s, "input mux %s", amuxs[pin->amux]);
599 }
600 break;
601 case PM8XXX_MPP_SINK:
602 seq_printf(s, " sink %dmA ", pin->drive_strength);
603 if (pin->dtest) {
604 seq_printf(s, "dtest%d", pin->dtest);
605 } else {
606 if (!pin->paired) {
607 seq_puts(s, str_high_low(pin->output_value));
608 } else {
609 seq_puts(s, pin->output_value ?
610 "inverted" : "follow");
611 }
612 }
613 break;
614 }
615 }
616
pm8xxx_mpp_dbg_show(struct seq_file * s,struct gpio_chip * chip)617 static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
618 {
619 unsigned gpio = chip->base;
620 unsigned i;
621
622 for (i = 0; i < chip->ngpio; i++, gpio++) {
623 pm8xxx_mpp_dbg_show_one(s, NULL, chip, i, gpio);
624 seq_puts(s, "\n");
625 }
626 }
627
628 #else
629 #define pm8xxx_mpp_dbg_show NULL
630 #endif
631
632 static const struct gpio_chip pm8xxx_mpp_template = {
633 .direction_input = pm8xxx_mpp_direction_input,
634 .direction_output = pm8xxx_mpp_direction_output,
635 .get = pm8xxx_mpp_get,
636 .set = pm8xxx_mpp_set,
637 .of_xlate = pm8xxx_mpp_of_xlate,
638 .dbg_show = pm8xxx_mpp_dbg_show,
639 .owner = THIS_MODULE,
640 };
641
pm8xxx_pin_populate(struct pm8xxx_mpp * pctrl,struct pm8xxx_pin_data * pin)642 static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl,
643 struct pm8xxx_pin_data *pin)
644 {
645 unsigned int val;
646 unsigned level;
647 unsigned ctrl;
648 unsigned type;
649 int ret;
650
651 ret = regmap_read(pctrl->regmap, pin->reg, &val);
652 if (ret) {
653 dev_err(pctrl->dev, "failed to read register\n");
654 return ret;
655 }
656
657 type = (val >> 5) & 7;
658 level = (val >> 2) & 7;
659 ctrl = (val) & 3;
660
661 switch (type) {
662 case PM8XXX_MPP_TYPE_D_INPUT:
663 pin->mode = PM8XXX_MPP_DIGITAL;
664 pin->input = true;
665 pin->power_source = level;
666 pin->dtest = ctrl;
667 break;
668 case PM8XXX_MPP_TYPE_D_OUTPUT:
669 pin->mode = PM8XXX_MPP_DIGITAL;
670 pin->output = true;
671 pin->power_source = level;
672 pin->output_value = !!(ctrl & BIT(0));
673 pin->paired = !!(ctrl & BIT(1));
674 break;
675 case PM8XXX_MPP_TYPE_D_BI_DIR:
676 pin->mode = PM8XXX_MPP_DIGITAL;
677 pin->input = true;
678 pin->output = true;
679 pin->power_source = level;
680 switch (ctrl) {
681 case PM8XXX_MPP_BI_PULLUP_1KOHM:
682 pin->pullup = 600;
683 break;
684 case PM8XXX_MPP_BI_PULLUP_OPEN:
685 pin->high_z = true;
686 break;
687 case PM8XXX_MPP_BI_PULLUP_10KOHM:
688 pin->pullup = 10000;
689 break;
690 case PM8XXX_MPP_BI_PULLUP_30KOHM:
691 pin->pullup = 30000;
692 break;
693 }
694 break;
695 case PM8XXX_MPP_TYPE_A_INPUT:
696 pin->mode = PM8XXX_MPP_ANALOG;
697 pin->input = true;
698 pin->amux = level;
699 break;
700 case PM8XXX_MPP_TYPE_A_OUTPUT:
701 pin->mode = PM8XXX_MPP_ANALOG;
702 pin->output = true;
703 pin->aout_level = level;
704 pin->output_value = !!(ctrl & BIT(0));
705 pin->paired = !!(ctrl & BIT(1));
706 break;
707 case PM8XXX_MPP_TYPE_SINK:
708 pin->mode = PM8XXX_MPP_SINK;
709 pin->drive_strength = 5 * (level + 1);
710 pin->output_value = !!(ctrl & BIT(0));
711 pin->paired = !!(ctrl & BIT(1));
712 break;
713 case PM8XXX_MPP_TYPE_DTEST_SINK:
714 pin->mode = PM8XXX_MPP_SINK;
715 pin->dtest = ctrl + 1;
716 pin->drive_strength = 5 * (level + 1);
717 break;
718 case PM8XXX_MPP_TYPE_DTEST_OUTPUT:
719 pin->mode = PM8XXX_MPP_DIGITAL;
720 pin->power_source = level;
721 if (ctrl >= 1)
722 pin->dtest = ctrl;
723 break;
724 }
725
726 return 0;
727 }
728
pm8xxx_mpp_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)729 static int pm8xxx_mpp_domain_translate(struct irq_domain *domain,
730 struct irq_fwspec *fwspec,
731 unsigned long *hwirq,
732 unsigned int *type)
733 {
734 struct pm8xxx_mpp *pctrl = container_of(domain->host_data,
735 struct pm8xxx_mpp, chip);
736
737 if (fwspec->param_count != 2 ||
738 fwspec->param[0] < PM8XXX_MPP_PHYSICAL_OFFSET ||
739 fwspec->param[0] > pctrl->chip.ngpio)
740 return -EINVAL;
741
742 *hwirq = fwspec->param[0] - PM8XXX_MPP_PHYSICAL_OFFSET;
743 *type = fwspec->param[1];
744
745 return 0;
746 }
747
pm8xxx_mpp_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)748 static unsigned int pm8xxx_mpp_child_offset_to_irq(struct gpio_chip *chip,
749 unsigned int offset)
750 {
751 return offset + PM8XXX_MPP_PHYSICAL_OFFSET;
752 }
753
pm8821_mpp_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int child_hwirq,unsigned int child_type,unsigned int * parent_hwirq,unsigned int * parent_type)754 static int pm8821_mpp_child_to_parent_hwirq(struct gpio_chip *chip,
755 unsigned int child_hwirq,
756 unsigned int child_type,
757 unsigned int *parent_hwirq,
758 unsigned int *parent_type)
759 {
760 *parent_hwirq = child_hwirq + 24;
761 *parent_type = child_type;
762
763 return 0;
764 }
765
pm8xxx_mpp_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int child_hwirq,unsigned int child_type,unsigned int * parent_hwirq,unsigned int * parent_type)766 static int pm8xxx_mpp_child_to_parent_hwirq(struct gpio_chip *chip,
767 unsigned int child_hwirq,
768 unsigned int child_type,
769 unsigned int *parent_hwirq,
770 unsigned int *parent_type)
771 {
772 *parent_hwirq = child_hwirq + 0x80;
773 *parent_type = child_type;
774
775 return 0;
776 }
777
pm8xxx_mpp_irq_disable(struct irq_data * d)778 static void pm8xxx_mpp_irq_disable(struct irq_data *d)
779 {
780 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
781
782 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
783 }
784
pm8xxx_mpp_irq_enable(struct irq_data * d)785 static void pm8xxx_mpp_irq_enable(struct irq_data *d)
786 {
787 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
788
789 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
790 }
791
792 static const struct irq_chip pm8xxx_mpp_irq_chip = {
793 .name = "ssbi-mpp",
794 .irq_mask_ack = irq_chip_mask_ack_parent,
795 .irq_unmask = irq_chip_unmask_parent,
796 .irq_disable = pm8xxx_mpp_irq_disable,
797 .irq_enable = pm8xxx_mpp_irq_enable,
798 .irq_set_type = irq_chip_set_type_parent,
799 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE |
800 IRQCHIP_IMMUTABLE,
801 GPIOCHIP_IRQ_RESOURCE_HELPERS,
802 };
803
804 static const struct of_device_id pm8xxx_mpp_of_match[] = {
805 { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 },
806 { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 },
807 { .compatible = "qcom,pm8058-mpp", .data = (void *) 12 },
808 { .compatible = "qcom,pm8821-mpp", .data = (void *) 4 },
809 { .compatible = "qcom,pm8917-mpp", .data = (void *) 10 },
810 { .compatible = "qcom,pm8921-mpp", .data = (void *) 12 },
811 { },
812 };
813 MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match);
814
pm8xxx_mpp_probe(struct platform_device * pdev)815 static int pm8xxx_mpp_probe(struct platform_device *pdev)
816 {
817 struct pm8xxx_pin_data *pin_data;
818 struct irq_domain *parent_domain;
819 struct device_node *parent_node;
820 struct pinctrl_pin_desc *pins;
821 struct gpio_irq_chip *girq;
822 struct pm8xxx_mpp *pctrl;
823 int ret;
824 int i;
825
826 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
827 if (!pctrl)
828 return -ENOMEM;
829
830 pctrl->dev = &pdev->dev;
831 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev);
832
833 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
834 if (!pctrl->regmap) {
835 dev_err(&pdev->dev, "parent regmap unavailable\n");
836 return -ENXIO;
837 }
838
839 pctrl->desc = pm8xxx_pinctrl_desc;
840 pctrl->desc.npins = pctrl->npins;
841
842 pins = devm_kcalloc(&pdev->dev,
843 pctrl->desc.npins,
844 sizeof(struct pinctrl_pin_desc),
845 GFP_KERNEL);
846 if (!pins)
847 return -ENOMEM;
848
849 pin_data = devm_kcalloc(&pdev->dev,
850 pctrl->desc.npins,
851 sizeof(struct pm8xxx_pin_data),
852 GFP_KERNEL);
853 if (!pin_data)
854 return -ENOMEM;
855
856 for (i = 0; i < pctrl->desc.npins; i++) {
857 pin_data[i].reg = SSBI_REG_ADDR_MPP(i);
858
859 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
860 if (ret)
861 return ret;
862
863 pins[i].number = i;
864 pins[i].name = pm8xxx_groups[i];
865 pins[i].drv_data = &pin_data[i];
866 }
867 pctrl->desc.pins = pins;
868
869 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings);
870 pctrl->desc.custom_params = pm8xxx_mpp_bindings;
871 #ifdef CONFIG_DEBUG_FS
872 pctrl->desc.custom_conf_items = pm8xxx_conf_items;
873 #endif
874
875 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
876 if (IS_ERR(pctrl->pctrl)) {
877 dev_err(&pdev->dev, "couldn't register pm8xxx mpp driver\n");
878 return PTR_ERR(pctrl->pctrl);
879 }
880
881 pctrl->chip = pm8xxx_mpp_template;
882 pctrl->chip.base = -1;
883 pctrl->chip.parent = &pdev->dev;
884 pctrl->chip.of_gpio_n_cells = 2;
885 pctrl->chip.label = dev_name(pctrl->dev);
886 pctrl->chip.ngpio = pctrl->npins;
887
888 parent_node = of_irq_find_parent(pctrl->dev->of_node);
889 if (!parent_node)
890 return -ENXIO;
891
892 parent_domain = irq_find_host(parent_node);
893 of_node_put(parent_node);
894 if (!parent_domain)
895 return -ENXIO;
896
897 girq = &pctrl->chip.irq;
898 gpio_irq_chip_set_chip(girq, &pm8xxx_mpp_irq_chip);
899 girq->default_type = IRQ_TYPE_NONE;
900 girq->handler = handle_level_irq;
901 girq->fwnode = dev_fwnode(pctrl->dev);
902 girq->parent_domain = parent_domain;
903 if (of_device_is_compatible(pdev->dev.of_node, "qcom,pm8821-mpp"))
904 girq->child_to_parent_hwirq = pm8821_mpp_child_to_parent_hwirq;
905 else
906 girq->child_to_parent_hwirq = pm8xxx_mpp_child_to_parent_hwirq;
907 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
908 girq->child_offset_to_irq = pm8xxx_mpp_child_offset_to_irq;
909 girq->child_irq_domain_ops.translate = pm8xxx_mpp_domain_translate;
910
911 ret = gpiochip_add_data(&pctrl->chip, pctrl);
912 if (ret) {
913 dev_err(&pdev->dev, "failed register gpiochip\n");
914 return ret;
915 }
916
917 ret = gpiochip_add_pin_range(&pctrl->chip,
918 dev_name(pctrl->dev),
919 0, 0, pctrl->chip.ngpio);
920 if (ret) {
921 dev_err(pctrl->dev, "failed to add pin range\n");
922 goto unregister_gpiochip;
923 }
924
925 platform_set_drvdata(pdev, pctrl);
926
927 dev_dbg(&pdev->dev, "Qualcomm pm8xxx mpp driver probed\n");
928
929 return 0;
930
931 unregister_gpiochip:
932 gpiochip_remove(&pctrl->chip);
933
934 return ret;
935 }
936
pm8xxx_mpp_remove(struct platform_device * pdev)937 static void pm8xxx_mpp_remove(struct platform_device *pdev)
938 {
939 struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev);
940
941 gpiochip_remove(&pctrl->chip);
942 }
943
944 static struct platform_driver pm8xxx_mpp_driver = {
945 .driver = {
946 .name = "qcom-ssbi-mpp",
947 .of_match_table = pm8xxx_mpp_of_match,
948 },
949 .probe = pm8xxx_mpp_probe,
950 .remove = pm8xxx_mpp_remove,
951 };
952
953 module_platform_driver(pm8xxx_mpp_driver);
954
955 MODULE_AUTHOR("Bjorn Andersson <[email protected]>");
956 MODULE_DESCRIPTION("Qualcomm PM8xxx MPP driver");
957 MODULE_LICENSE("GPL v2");
958