1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/gpio/driver.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
16 #include <linux/spmi.h>
17 #include <linux/string_choices.h>
18 #include <linux/types.h>
19
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinmux.h>
23
24 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
25
26 #include "../core.h"
27 #include "../pinctrl-utils.h"
28
29 #define PMIC_GPIO_ADDRESS_RANGE 0x100
30
31 /* type and subtype registers base address offsets */
32 #define PMIC_GPIO_REG_TYPE 0x4
33 #define PMIC_GPIO_REG_SUBTYPE 0x5
34
35 /* GPIO peripheral type and subtype out_values */
36 #define PMIC_GPIO_TYPE 0x10
37 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
38 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
39 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
40 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
41 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
42 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
43 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12
44 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13
45
46 #define PMIC_MPP_REG_RT_STS 0x10
47 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
48
49 /* control register base address offsets */
50 #define PMIC_GPIO_REG_MODE_CTL 0x40
51 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
52 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
53 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
54 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
55 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
56 #define PMIC_GPIO_REG_EN_CTL 0x46
57 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
58
59 /* PMIC_GPIO_REG_MODE_CTL */
60 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
61 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
62 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
63 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
64 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
65
66 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
67 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
68 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
69 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
70 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
71
72 /* PMIC_GPIO_REG_DIG_VIN_CTL */
73 #define PMIC_GPIO_REG_VIN_SHIFT 0
74 #define PMIC_GPIO_REG_VIN_MASK 0x7
75
76 /* PMIC_GPIO_REG_DIG_PULL_CTL */
77 #define PMIC_GPIO_REG_PULL_SHIFT 0
78 #define PMIC_GPIO_REG_PULL_MASK 0x7
79
80 #define PMIC_GPIO_PULL_DOWN 4
81 #define PMIC_GPIO_PULL_DISABLE 5
82
83 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
84 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
86 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
87
88 /* PMIC_GPIO_REG_DIG_IN_CTL */
89 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
91 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
92
93 /* PMIC_GPIO_REG_DIG_OUT_CTL */
94 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
95 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
96 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
97 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
98
99 /*
100 * Output type - indicates pin should be configured as push-pull,
101 * open drain or open source.
102 */
103 #define PMIC_GPIO_OUT_BUF_CMOS 0
104 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
106
107 #define PMIC_GPIO_OUT_STRENGTH_LOW 1
108 #define PMIC_GPIO_OUT_STRENGTH_HIGH 3
109
110 /* PMIC_GPIO_REG_EN_CTL */
111 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
112
113 #define PMIC_GPIO_PHYSICAL_OFFSET 1
114
115 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
116 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
117
118 /* Qualcomm specific pin configurations */
119 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
120 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
121 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
122 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
123 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
124
125 /* The index of each function in pmic_gpio_functions[] array */
126 enum pmic_gpio_func_index {
127 PMIC_GPIO_FUNC_INDEX_NORMAL,
128 PMIC_GPIO_FUNC_INDEX_PAIRED,
129 PMIC_GPIO_FUNC_INDEX_FUNC1,
130 PMIC_GPIO_FUNC_INDEX_FUNC2,
131 PMIC_GPIO_FUNC_INDEX_FUNC3,
132 PMIC_GPIO_FUNC_INDEX_FUNC4,
133 PMIC_GPIO_FUNC_INDEX_DTEST1,
134 PMIC_GPIO_FUNC_INDEX_DTEST2,
135 PMIC_GPIO_FUNC_INDEX_DTEST3,
136 PMIC_GPIO_FUNC_INDEX_DTEST4,
137 };
138
139 /**
140 * struct pmic_gpio_pad - keep current GPIO settings
141 * @base: Address base in SPMI device.
142 * @is_enabled: Set to false when GPIO should be put in high Z state.
143 * @out_value: Cached pin output value
144 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
145 * open-drain or open-source mode.
146 * @output_enabled: Set to true if GPIO output logic is enabled.
147 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
148 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
149 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
150 * @num_sources: Number of power-sources supported by this GPIO.
151 * @power_source: Current power-source used.
152 * @buffer_type: Push-pull, open-drain or open-source.
153 * @pullup: Constant current which flow trough GPIO output buffer.
154 * @strength: No, Low, Medium, High
155 * @function: See pmic_gpio_functions[]
156 * @atest: the ATEST selection for GPIO analog-pass-through mode
157 * @dtest_buffer: the DTEST buffer selection for digital input mode.
158 */
159 struct pmic_gpio_pad {
160 u16 base;
161 bool is_enabled;
162 bool out_value;
163 bool have_buffer;
164 bool output_enabled;
165 bool input_enabled;
166 bool analog_pass;
167 bool lv_mv_type;
168 unsigned int num_sources;
169 unsigned int power_source;
170 unsigned int buffer_type;
171 unsigned int pullup;
172 unsigned int strength;
173 unsigned int function;
174 unsigned int atest;
175 unsigned int dtest_buffer;
176 };
177
178 struct pmic_gpio_state {
179 struct device *dev;
180 struct regmap *map;
181 struct pinctrl_dev *ctrl;
182 struct gpio_chip chip;
183 u8 usid;
184 u8 pid_base;
185 };
186
187 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
188 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
189 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
190 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
191 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
192 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
193 };
194
195 #ifdef CONFIG_DEBUG_FS
196 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
197 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
198 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
199 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
200 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
201 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
202 };
203 #endif
204
205 static const char *const pmic_gpio_groups[] = {
206 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
207 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
208 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
209 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
210 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
211 };
212
213 static const char *const pmic_gpio_functions[] = {
214 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
215 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
216 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
217 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
218 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
219 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
220 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
221 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
222 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
223 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
224 };
225
pmic_gpio_read(struct pmic_gpio_state * state,struct pmic_gpio_pad * pad,unsigned int addr)226 static int pmic_gpio_read(struct pmic_gpio_state *state,
227 struct pmic_gpio_pad *pad, unsigned int addr)
228 {
229 unsigned int val;
230 int ret;
231
232 ret = regmap_read(state->map, pad->base + addr, &val);
233 if (ret < 0)
234 dev_err(state->dev, "read 0x%x failed\n", addr);
235 else
236 ret = val;
237
238 return ret;
239 }
240
pmic_gpio_write(struct pmic_gpio_state * state,struct pmic_gpio_pad * pad,unsigned int addr,unsigned int val)241 static int pmic_gpio_write(struct pmic_gpio_state *state,
242 struct pmic_gpio_pad *pad, unsigned int addr,
243 unsigned int val)
244 {
245 int ret;
246
247 ret = regmap_write(state->map, pad->base + addr, val);
248 if (ret < 0)
249 dev_err(state->dev, "write 0x%x failed\n", addr);
250
251 return ret;
252 }
253
pmic_gpio_get_groups_count(struct pinctrl_dev * pctldev)254 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
255 {
256 /* Every PIN is a group */
257 return pctldev->desc->npins;
258 }
259
pmic_gpio_get_group_name(struct pinctrl_dev * pctldev,unsigned pin)260 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
261 unsigned pin)
262 {
263 return pctldev->desc->pins[pin].name;
264 }
265
pmic_gpio_get_group_pins(struct pinctrl_dev * pctldev,unsigned pin,const unsigned ** pins,unsigned * num_pins)266 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
267 const unsigned **pins, unsigned *num_pins)
268 {
269 *pins = &pctldev->desc->pins[pin].number;
270 *num_pins = 1;
271 return 0;
272 }
273
274 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
275 .get_groups_count = pmic_gpio_get_groups_count,
276 .get_group_name = pmic_gpio_get_group_name,
277 .get_group_pins = pmic_gpio_get_group_pins,
278 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
279 .dt_free_map = pinctrl_utils_free_map,
280 };
281
pmic_gpio_get_functions_count(struct pinctrl_dev * pctldev)282 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
283 {
284 return ARRAY_SIZE(pmic_gpio_functions);
285 }
286
pmic_gpio_get_function_name(struct pinctrl_dev * pctldev,unsigned function)287 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
288 unsigned function)
289 {
290 return pmic_gpio_functions[function];
291 }
292
pmic_gpio_get_function_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_qgroups)293 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
294 unsigned function,
295 const char *const **groups,
296 unsigned *const num_qgroups)
297 {
298 *groups = pmic_gpio_groups;
299 *num_qgroups = pctldev->desc->npins;
300 return 0;
301 }
302
pmic_gpio_set_mux(struct pinctrl_dev * pctldev,unsigned function,unsigned pin)303 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
304 unsigned pin)
305 {
306 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
307 struct pmic_gpio_pad *pad;
308 unsigned int val;
309 int ret;
310
311 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
312 pr_err("function: %d is not defined\n", function);
313 return -EINVAL;
314 }
315
316 pad = pctldev->desc->pins[pin].drv_data;
317 /*
318 * Non-LV/MV subtypes only support 2 special functions,
319 * offsetting the dtestx function values by 2
320 */
321 if (!pad->lv_mv_type) {
322 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
323 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
324 pr_err("LV/MV subtype doesn't have func3/func4\n");
325 return -EINVAL;
326 }
327 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
328 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
329 PMIC_GPIO_FUNC_INDEX_FUNC3);
330 }
331
332 pad->function = function;
333
334 if (pad->analog_pass)
335 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
336 else if (pad->output_enabled && pad->input_enabled)
337 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
338 else if (pad->output_enabled)
339 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
340 else
341 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
342
343 if (pad->lv_mv_type) {
344 ret = pmic_gpio_write(state, pad,
345 PMIC_GPIO_REG_MODE_CTL, val);
346 if (ret < 0)
347 return ret;
348
349 val = pad->atest - 1;
350 ret = pmic_gpio_write(state, pad,
351 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
352 if (ret < 0)
353 return ret;
354
355 val = pad->out_value
356 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
357 val |= pad->function
358 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
359 ret = pmic_gpio_write(state, pad,
360 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
361 if (ret < 0)
362 return ret;
363 } else {
364 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
365 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
366 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
367
368 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
369 if (ret < 0)
370 return ret;
371 }
372
373 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
374
375 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
376 }
377
378 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
379 .get_functions_count = pmic_gpio_get_functions_count,
380 .get_function_name = pmic_gpio_get_function_name,
381 .get_function_groups = pmic_gpio_get_function_groups,
382 .set_mux = pmic_gpio_set_mux,
383 };
384
pmic_gpio_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)385 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
386 unsigned int pin, unsigned long *config)
387 {
388 unsigned param = pinconf_to_config_param(*config);
389 struct pmic_gpio_pad *pad;
390 unsigned arg;
391
392 pad = pctldev->desc->pins[pin].drv_data;
393
394 switch (param) {
395 case PIN_CONFIG_DRIVE_PUSH_PULL:
396 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
397 return -EINVAL;
398 arg = 1;
399 break;
400 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
401 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
402 return -EINVAL;
403 arg = 1;
404 break;
405 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
406 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
407 return -EINVAL;
408 arg = 1;
409 break;
410 case PIN_CONFIG_BIAS_PULL_DOWN:
411 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
412 return -EINVAL;
413 arg = 1;
414 break;
415 case PIN_CONFIG_BIAS_DISABLE:
416 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
417 return -EINVAL;
418 arg = 1;
419 break;
420 case PIN_CONFIG_BIAS_PULL_UP:
421 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
422 return -EINVAL;
423 arg = 1;
424 break;
425 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
426 if (pad->is_enabled)
427 return -EINVAL;
428 arg = 1;
429 break;
430 case PIN_CONFIG_POWER_SOURCE:
431 arg = pad->power_source;
432 break;
433 case PIN_CONFIG_INPUT_ENABLE:
434 if (!pad->input_enabled)
435 return -EINVAL;
436 arg = 1;
437 break;
438 case PIN_CONFIG_OUTPUT_ENABLE:
439 arg = pad->output_enabled;
440 break;
441 case PIN_CONFIG_OUTPUT:
442 arg = pad->out_value;
443 break;
444 case PMIC_GPIO_CONF_PULL_UP:
445 arg = pad->pullup;
446 break;
447 case PMIC_GPIO_CONF_STRENGTH:
448 switch (pad->strength) {
449 case PMIC_GPIO_OUT_STRENGTH_HIGH:
450 arg = PMIC_GPIO_STRENGTH_HIGH;
451 break;
452 case PMIC_GPIO_OUT_STRENGTH_LOW:
453 arg = PMIC_GPIO_STRENGTH_LOW;
454 break;
455 default:
456 arg = pad->strength;
457 break;
458 }
459 break;
460 case PMIC_GPIO_CONF_ATEST:
461 arg = pad->atest;
462 break;
463 case PMIC_GPIO_CONF_ANALOG_PASS:
464 arg = pad->analog_pass;
465 break;
466 case PMIC_GPIO_CONF_DTEST_BUFFER:
467 arg = pad->dtest_buffer;
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 *config = pinconf_to_config_packed(param, arg);
474 return 0;
475 }
476
pmic_gpio_config_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned nconfs)477 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
478 unsigned long *configs, unsigned nconfs)
479 {
480 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
481 struct pmic_gpio_pad *pad;
482 unsigned param, arg;
483 unsigned int val;
484 int i, ret;
485
486 pad = pctldev->desc->pins[pin].drv_data;
487
488 pad->is_enabled = true;
489 for (i = 0; i < nconfs; i++) {
490 param = pinconf_to_config_param(configs[i]);
491 arg = pinconf_to_config_argument(configs[i]);
492
493 switch (param) {
494 case PIN_CONFIG_DRIVE_PUSH_PULL:
495 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
496 break;
497 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
498 if (!pad->have_buffer)
499 return -EINVAL;
500 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
501 break;
502 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
503 if (!pad->have_buffer)
504 return -EINVAL;
505 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
506 break;
507 case PIN_CONFIG_BIAS_DISABLE:
508 pad->pullup = PMIC_GPIO_PULL_DISABLE;
509 break;
510 case PIN_CONFIG_BIAS_PULL_UP:
511 pad->pullup = PMIC_GPIO_PULL_UP_30;
512 break;
513 case PIN_CONFIG_BIAS_PULL_DOWN:
514 if (arg)
515 pad->pullup = PMIC_GPIO_PULL_DOWN;
516 else
517 pad->pullup = PMIC_GPIO_PULL_DISABLE;
518 break;
519 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
520 pad->is_enabled = false;
521 break;
522 case PIN_CONFIG_POWER_SOURCE:
523 if (arg >= pad->num_sources)
524 return -EINVAL;
525 pad->power_source = arg;
526 break;
527 case PIN_CONFIG_INPUT_ENABLE:
528 pad->input_enabled = arg ? true : false;
529 break;
530 case PIN_CONFIG_OUTPUT_ENABLE:
531 pad->output_enabled = arg ? true : false;
532 break;
533 case PIN_CONFIG_OUTPUT:
534 pad->output_enabled = true;
535 pad->out_value = arg;
536 break;
537 case PMIC_GPIO_CONF_PULL_UP:
538 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
539 return -EINVAL;
540 pad->pullup = arg;
541 break;
542 case PMIC_GPIO_CONF_STRENGTH:
543 if (arg > PMIC_GPIO_STRENGTH_LOW)
544 return -EINVAL;
545 switch (arg) {
546 case PMIC_GPIO_STRENGTH_HIGH:
547 pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH;
548 break;
549 case PMIC_GPIO_STRENGTH_LOW:
550 pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW;
551 break;
552 default:
553 pad->strength = arg;
554 break;
555 }
556 break;
557 case PMIC_GPIO_CONF_ATEST:
558 if (!pad->lv_mv_type || arg > 4)
559 return -EINVAL;
560 pad->atest = arg;
561 break;
562 case PMIC_GPIO_CONF_ANALOG_PASS:
563 if (!pad->lv_mv_type)
564 return -EINVAL;
565 pad->analog_pass = true;
566 break;
567 case PMIC_GPIO_CONF_DTEST_BUFFER:
568 if (arg > 4)
569 return -EINVAL;
570 pad->dtest_buffer = arg;
571 break;
572 default:
573 return -EINVAL;
574 }
575 }
576
577 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
578
579 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
580 if (ret < 0)
581 return ret;
582
583 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
584
585 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
586 if (ret < 0)
587 return ret;
588
589 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
590 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
591
592 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
593 if (ret < 0)
594 return ret;
595
596 if (pad->dtest_buffer == 0) {
597 val = 0;
598 } else {
599 if (pad->lv_mv_type) {
600 val = pad->dtest_buffer - 1;
601 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
602 } else {
603 val = BIT(pad->dtest_buffer - 1);
604 }
605 }
606 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
607 if (ret < 0)
608 return ret;
609
610 if (pad->analog_pass)
611 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
612 else if (pad->output_enabled && pad->input_enabled)
613 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
614 else if (pad->output_enabled)
615 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
616 else
617 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
618
619 if (pad->lv_mv_type) {
620 ret = pmic_gpio_write(state, pad,
621 PMIC_GPIO_REG_MODE_CTL, val);
622 if (ret < 0)
623 return ret;
624
625 val = pad->atest - 1;
626 ret = pmic_gpio_write(state, pad,
627 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
628 if (ret < 0)
629 return ret;
630
631 val = pad->out_value
632 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
633 val |= pad->function
634 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
635 ret = pmic_gpio_write(state, pad,
636 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
637 if (ret < 0)
638 return ret;
639 } else {
640 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
641 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
642 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
643
644 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
645 if (ret < 0)
646 return ret;
647 }
648
649 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
650
651 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
652
653 return ret;
654 }
655
pmic_gpio_config_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned pin)656 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
657 struct seq_file *s, unsigned pin)
658 {
659 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
660 struct pmic_gpio_pad *pad;
661 int ret, val, function;
662
663 static const char *const biases[] = {
664 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
665 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
666 };
667 static const char *const buffer_types[] = {
668 "push-pull", "open-drain", "open-source"
669 };
670 static const char *const strengths[] = {
671 "no", "low", "medium", "high"
672 };
673
674 pad = pctldev->desc->pins[pin].drv_data;
675
676 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
677
678 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
679
680 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
681 seq_puts(s, " ---");
682 } else {
683 if (pad->input_enabled) {
684 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
685 if (ret < 0)
686 return;
687
688 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
689 pad->out_value = ret;
690 }
691 /*
692 * For the non-LV/MV subtypes only 2 special functions are
693 * available, offsetting the dtest function values by 2.
694 */
695 function = pad->function;
696 if (!pad->lv_mv_type &&
697 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
698 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
699 PMIC_GPIO_FUNC_INDEX_FUNC3;
700
701 if (pad->analog_pass)
702 seq_puts(s, " analog-pass");
703 else
704 seq_printf(s, " %-4s",
705 pad->output_enabled ? "out" : "in");
706 seq_printf(s, " %-4s", str_high_low(pad->out_value));
707 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
708 seq_printf(s, " vin-%d", pad->power_source);
709 seq_printf(s, " %-27s", biases[pad->pullup]);
710 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
711 seq_printf(s, " %-7s", strengths[pad->strength]);
712 seq_printf(s, " atest-%d", pad->atest);
713 seq_printf(s, " dtest-%d", pad->dtest_buffer);
714 }
715 }
716
717 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
718 .is_generic = true,
719 .pin_config_group_get = pmic_gpio_config_get,
720 .pin_config_group_set = pmic_gpio_config_set,
721 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
722 };
723
pmic_gpio_direction_input(struct gpio_chip * chip,unsigned pin)724 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
725 {
726 struct pmic_gpio_state *state = gpiochip_get_data(chip);
727 unsigned long config;
728
729 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
730
731 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
732 }
733
pmic_gpio_direction_output(struct gpio_chip * chip,unsigned pin,int val)734 static int pmic_gpio_direction_output(struct gpio_chip *chip,
735 unsigned pin, int val)
736 {
737 struct pmic_gpio_state *state = gpiochip_get_data(chip);
738 unsigned long config;
739
740 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
741
742 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
743 }
744
pmic_gpio_get(struct gpio_chip * chip,unsigned pin)745 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
746 {
747 struct pmic_gpio_state *state = gpiochip_get_data(chip);
748 struct pmic_gpio_pad *pad;
749 int ret;
750
751 pad = state->ctrl->desc->pins[pin].drv_data;
752
753 if (!pad->is_enabled)
754 return -EINVAL;
755
756 if (pad->input_enabled) {
757 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
758 if (ret < 0)
759 return ret;
760
761 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
762 }
763
764 return !!pad->out_value;
765 }
766
pmic_gpio_set(struct gpio_chip * chip,unsigned pin,int value)767 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
768 {
769 struct pmic_gpio_state *state = gpiochip_get_data(chip);
770 unsigned long config;
771
772 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
773
774 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
775 }
776
pmic_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpio_desc,u32 * flags)777 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
778 const struct of_phandle_args *gpio_desc,
779 u32 *flags)
780 {
781 if (chip->of_gpio_n_cells < 2)
782 return -EINVAL;
783
784 if (flags)
785 *flags = gpio_desc->args[1];
786
787 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
788 }
789
pmic_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)790 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
791 {
792 struct pmic_gpio_state *state = gpiochip_get_data(chip);
793 unsigned i;
794
795 for (i = 0; i < chip->ngpio; i++) {
796 pmic_gpio_config_dbg_show(state->ctrl, s, i);
797 seq_puts(s, "\n");
798 }
799 }
800
801 static const struct gpio_chip pmic_gpio_gpio_template = {
802 .direction_input = pmic_gpio_direction_input,
803 .direction_output = pmic_gpio_direction_output,
804 .get = pmic_gpio_get,
805 .set = pmic_gpio_set,
806 .request = gpiochip_generic_request,
807 .free = gpiochip_generic_free,
808 .of_xlate = pmic_gpio_of_xlate,
809 .dbg_show = pmic_gpio_dbg_show,
810 };
811
pmic_gpio_populate(struct pmic_gpio_state * state,struct pmic_gpio_pad * pad)812 static int pmic_gpio_populate(struct pmic_gpio_state *state,
813 struct pmic_gpio_pad *pad)
814 {
815 int type, subtype, val, dir;
816
817 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
818 if (type < 0)
819 return type;
820
821 if (type != PMIC_GPIO_TYPE) {
822 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
823 type, pad->base);
824 return -ENODEV;
825 }
826
827 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
828 if (subtype < 0)
829 return subtype;
830
831 switch (subtype) {
832 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
833 pad->have_buffer = true;
834 fallthrough;
835 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
836 pad->num_sources = 4;
837 break;
838 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
839 pad->have_buffer = true;
840 fallthrough;
841 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
842 pad->num_sources = 8;
843 break;
844 case PMIC_GPIO_SUBTYPE_GPIO_LV:
845 pad->num_sources = 1;
846 pad->have_buffer = true;
847 pad->lv_mv_type = true;
848 break;
849 case PMIC_GPIO_SUBTYPE_GPIO_MV:
850 pad->num_sources = 2;
851 pad->have_buffer = true;
852 pad->lv_mv_type = true;
853 break;
854 case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2:
855 pad->num_sources = 2;
856 pad->have_buffer = true;
857 pad->lv_mv_type = true;
858 break;
859 case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3:
860 pad->num_sources = 3;
861 pad->have_buffer = true;
862 pad->lv_mv_type = true;
863 break;
864 default:
865 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
866 return -ENODEV;
867 }
868
869 if (pad->lv_mv_type) {
870 val = pmic_gpio_read(state, pad,
871 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
872 if (val < 0)
873 return val;
874
875 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
876 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
877
878 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
879 if (val < 0)
880 return val;
881
882 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
883 } else {
884 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
885 if (val < 0)
886 return val;
887
888 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
889
890 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
891 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
892 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
893 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
894 }
895
896 switch (dir) {
897 case PMIC_GPIO_MODE_DIGITAL_INPUT:
898 pad->input_enabled = true;
899 pad->output_enabled = false;
900 break;
901 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
902 pad->input_enabled = false;
903 pad->output_enabled = true;
904 break;
905 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
906 pad->input_enabled = true;
907 pad->output_enabled = true;
908 break;
909 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
910 if (!pad->lv_mv_type)
911 return -ENODEV;
912 pad->analog_pass = true;
913 break;
914 default:
915 dev_err(state->dev, "unknown GPIO direction\n");
916 return -ENODEV;
917 }
918
919 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
920 if (val < 0)
921 return val;
922
923 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
924 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
925
926 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
927 if (val < 0)
928 return val;
929
930 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
931 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
932
933 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
934 if (val < 0)
935 return val;
936
937 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
938 pad->dtest_buffer =
939 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
940 else if (!pad->lv_mv_type)
941 pad->dtest_buffer = ffs(val);
942 else
943 pad->dtest_buffer = 0;
944
945 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
946 if (val < 0)
947 return val;
948
949 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
950 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
951
952 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
953 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
954
955 if (pad->lv_mv_type) {
956 val = pmic_gpio_read(state, pad,
957 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
958 if (val < 0)
959 return val;
960 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
961 }
962
963 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
964 pad->is_enabled = true;
965 return 0;
966 }
967
pmic_gpio_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)968 static int pmic_gpio_domain_translate(struct irq_domain *domain,
969 struct irq_fwspec *fwspec,
970 unsigned long *hwirq,
971 unsigned int *type)
972 {
973 struct pmic_gpio_state *state = container_of(domain->host_data,
974 struct pmic_gpio_state,
975 chip);
976
977 if (fwspec->param_count != 2 ||
978 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
979 return -EINVAL;
980
981 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
982 *type = fwspec->param[1];
983
984 return 0;
985 }
986
pmic_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)987 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
988 unsigned int offset)
989 {
990 return offset + PMIC_GPIO_PHYSICAL_OFFSET;
991 }
992
pmic_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int child_hwirq,unsigned int child_type,unsigned int * parent_hwirq,unsigned int * parent_type)993 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
994 unsigned int child_hwirq,
995 unsigned int child_type,
996 unsigned int *parent_hwirq,
997 unsigned int *parent_type)
998 {
999 struct pmic_gpio_state *state = gpiochip_get_data(chip);
1000
1001 *parent_hwirq = child_hwirq + state->pid_base;
1002 *parent_type = child_type;
1003
1004 return 0;
1005 }
1006
pmic_gpio_populate_parent_fwspec(struct gpio_chip * chip,union gpio_irq_fwspec * gfwspec,unsigned int parent_hwirq,unsigned int parent_type)1007 static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
1008 union gpio_irq_fwspec *gfwspec,
1009 unsigned int parent_hwirq,
1010 unsigned int parent_type)
1011 {
1012 struct pmic_gpio_state *state = gpiochip_get_data(chip);
1013 struct irq_fwspec *fwspec = &gfwspec->fwspec;
1014
1015 fwspec->fwnode = chip->irq.parent_domain->fwnode;
1016
1017 fwspec->param_count = 4;
1018 fwspec->param[0] = state->usid;
1019 fwspec->param[1] = parent_hwirq;
1020 /* param[2] must be left as 0 */
1021 fwspec->param[3] = parent_type;
1022
1023 return 0;
1024 }
1025
pmic_gpio_irq_mask(struct irq_data * data)1026 static void pmic_gpio_irq_mask(struct irq_data *data)
1027 {
1028 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1029
1030 irq_chip_mask_parent(data);
1031 gpiochip_disable_irq(gc, data->hwirq);
1032 }
1033
pmic_gpio_irq_unmask(struct irq_data * data)1034 static void pmic_gpio_irq_unmask(struct irq_data *data)
1035 {
1036 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1037
1038 gpiochip_enable_irq(gc, data->hwirq);
1039 irq_chip_unmask_parent(data);
1040 }
1041
1042 static const struct irq_chip spmi_gpio_irq_chip = {
1043 .name = "spmi-gpio",
1044 .irq_ack = irq_chip_ack_parent,
1045 .irq_mask = pmic_gpio_irq_mask,
1046 .irq_unmask = pmic_gpio_irq_unmask,
1047 .irq_set_type = irq_chip_set_type_parent,
1048 .irq_set_wake = irq_chip_set_wake_parent,
1049 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
1050 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1051 };
1052
pmic_gpio_probe(struct platform_device * pdev)1053 static int pmic_gpio_probe(struct platform_device *pdev)
1054 {
1055 struct irq_domain *parent_domain;
1056 struct device_node *parent_node;
1057 struct device *dev = &pdev->dev;
1058 struct pinctrl_pin_desc *pindesc;
1059 struct pinctrl_desc *pctrldesc;
1060 struct pmic_gpio_pad *pad, *pads;
1061 struct pmic_gpio_state *state;
1062 struct gpio_irq_chip *girq;
1063 const struct spmi_device *parent_spmi_dev;
1064 int ret, npins, i;
1065 u32 reg;
1066
1067 ret = of_property_read_u32(dev->of_node, "reg", ®);
1068 if (ret < 0) {
1069 dev_err(dev, "missing base address");
1070 return ret;
1071 }
1072
1073 npins = (uintptr_t) device_get_match_data(&pdev->dev);
1074
1075 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1076 if (!state)
1077 return -ENOMEM;
1078
1079 platform_set_drvdata(pdev, state);
1080
1081 state->dev = &pdev->dev;
1082 state->map = dev_get_regmap(dev->parent, NULL);
1083 parent_spmi_dev = to_spmi_device(dev->parent);
1084 state->usid = parent_spmi_dev->usid;
1085 state->pid_base = reg >> 8;
1086
1087 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1088 if (!pindesc)
1089 return -ENOMEM;
1090
1091 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1092 if (!pads)
1093 return -ENOMEM;
1094
1095 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1096 if (!pctrldesc)
1097 return -ENOMEM;
1098
1099 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1100 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1101 pctrldesc->confops = &pmic_gpio_pinconf_ops;
1102 pctrldesc->owner = THIS_MODULE;
1103 pctrldesc->name = dev_name(dev);
1104 pctrldesc->pins = pindesc;
1105 pctrldesc->npins = npins;
1106 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1107 pctrldesc->custom_params = pmic_gpio_bindings;
1108 #ifdef CONFIG_DEBUG_FS
1109 pctrldesc->custom_conf_items = pmic_conf_items;
1110 #endif
1111
1112 for (i = 0; i < npins; i++, pindesc++) {
1113 pad = &pads[i];
1114 pindesc->drv_data = pad;
1115 pindesc->number = i;
1116 pindesc->name = pmic_gpio_groups[i];
1117
1118 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1119
1120 ret = pmic_gpio_populate(state, pad);
1121 if (ret < 0)
1122 return ret;
1123 }
1124
1125 state->chip = pmic_gpio_gpio_template;
1126 state->chip.parent = dev;
1127 state->chip.base = -1;
1128 state->chip.ngpio = npins;
1129 state->chip.label = dev_name(dev);
1130 state->chip.of_gpio_n_cells = 2;
1131 state->chip.can_sleep = false;
1132
1133 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1134 if (IS_ERR(state->ctrl))
1135 return PTR_ERR(state->ctrl);
1136
1137 parent_node = of_irq_find_parent(state->dev->of_node);
1138 if (!parent_node)
1139 return -ENXIO;
1140
1141 parent_domain = irq_find_host(parent_node);
1142 of_node_put(parent_node);
1143 if (!parent_domain)
1144 return -ENXIO;
1145
1146 girq = &state->chip.irq;
1147 gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip);
1148 girq->default_type = IRQ_TYPE_NONE;
1149 girq->handler = handle_level_irq;
1150 girq->fwnode = dev_fwnode(state->dev);
1151 girq->parent_domain = parent_domain;
1152 girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1153 girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1154 girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1155 girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1156
1157 ret = gpiochip_add_data(&state->chip, state);
1158 if (ret) {
1159 dev_err(state->dev, "can't add gpio chip\n");
1160 return ret;
1161 }
1162
1163 /*
1164 * For DeviceTree-supported systems, the gpio core checks the
1165 * pinctrl's device node for the "gpio-ranges" property.
1166 * If it is present, it takes care of adding the pin ranges
1167 * for the driver. In this case the driver can skip ahead.
1168 *
1169 * In order to remain compatible with older, existing DeviceTree
1170 * files which don't set the "gpio-ranges" property or systems that
1171 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1172 */
1173 if (!of_property_present(dev->of_node, "gpio-ranges")) {
1174 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1175 npins);
1176 if (ret) {
1177 dev_err(dev, "failed to add pin range\n");
1178 goto err_range;
1179 }
1180 }
1181
1182 return 0;
1183
1184 err_range:
1185 gpiochip_remove(&state->chip);
1186 return ret;
1187 }
1188
pmic_gpio_remove(struct platform_device * pdev)1189 static void pmic_gpio_remove(struct platform_device *pdev)
1190 {
1191 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1192
1193 gpiochip_remove(&state->chip);
1194 }
1195
1196 static const struct of_device_id pmic_gpio_of_match[] = {
1197 { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
1198 /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1199 { .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1200 /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1201 { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1202 { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
1203 { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1204 { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1205 { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
1206 { .compatible = "qcom,pm6450-gpio", .data = (void *) 9 },
1207 { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 },
1208 { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1209 { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8},
1210 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1211 { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1212 /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1213 { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1214 { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1215 /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1216 { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1217 /* pm8150l has 12 GPIOs with holes on 7 */
1218 { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1219 { .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1220 { .compatible = "qcom,pm8226-gpio", .data = (void *) 8 },
1221 { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1222 { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1223 { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1224 { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1225 { .compatible = "qcom,pm8550-gpio", .data = (void *) 12 },
1226 { .compatible = "qcom,pm8550b-gpio", .data = (void *) 12 },
1227 { .compatible = "qcom,pm8550ve-gpio", .data = (void *) 8 },
1228 { .compatible = "qcom,pm8550vs-gpio", .data = (void *) 6 },
1229 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1230 /* pm8937 has 8 GPIOs with holes on 3, 4 and 6 */
1231 { .compatible = "qcom,pm8937-gpio", .data = (void *) 8 },
1232 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1233 /* pm8950 has 8 GPIOs with holes on 3 */
1234 { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1235 /* pm8953 has 8 GPIOs with holes on 3 and 6 */
1236 { .compatible = "qcom,pm8953-gpio", .data = (void *) 8 },
1237 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1238 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1239 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1240 { .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
1241 { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },
1242 { .compatible = "qcom,pmi632-gpio", .data = (void *) 8 },
1243 { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1244 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1245 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1246 { .compatible = "qcom,pmih0108-gpio", .data = (void *) 18 },
1247 { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1248 { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 },
1249 { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1250 { .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 },
1251 /* pmp8074 has 12 GPIOs with holes on 1 and 12 */
1252 { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
1253 { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1254 { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1255 { .compatible = "qcom,pmr735d-gpio", .data = (void *) 2 },
1256 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1257 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1258 /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1259 { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1260 { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
1261 { .compatible = "qcom,pmx75-gpio", .data = (void *) 16 },
1262 { .compatible = "qcom,pmxr2230-gpio", .data = (void *) 12 },
1263 { },
1264 };
1265
1266 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1267
1268 static struct platform_driver pmic_gpio_driver = {
1269 .driver = {
1270 .name = "qcom-spmi-gpio",
1271 .of_match_table = pmic_gpio_of_match,
1272 },
1273 .probe = pmic_gpio_probe,
1274 .remove = pmic_gpio_remove,
1275 };
1276
1277 module_platform_driver(pmic_gpio_driver);
1278
1279 MODULE_AUTHOR("Ivan T. Ivanov <[email protected]>");
1280 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1281 MODULE_ALIAS("platform:qcom-spmi-gpio");
1282 MODULE_LICENSE("GPL v2");
1283