1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 *
6 * Author: Algea Cao <[email protected]>
7 * Author: Cristian Ciocaltea <[email protected]>
8 */
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/rational.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define GRF_HDPTX_CON0 0x00
25 #define HDPTX_I_PLL_EN BIT(7)
26 #define HDPTX_I_BIAS_EN BIT(6)
27 #define HDPTX_I_BGR_EN BIT(5)
28 #define GRF_HDPTX_STATUS 0x80
29 #define HDPTX_O_PLL_LOCK_DONE BIT(3)
30 #define HDPTX_O_PHY_CLK_RDY BIT(2)
31 #define HDPTX_O_PHY_RDY BIT(1)
32 #define HDPTX_O_SB_RDY BIT(0)
33
34 #define HDTPX_REG(_n, _min, _max) \
35 ( \
36 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
37 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
38 ((0x##_n) * 4) \
39 )
40
41 #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
42 #define SB_REG(n) HDTPX_REG(n, 0100, 0129)
43 #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
44 #define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
45
46 /* CMN_REG(0008) */
47 #define LCPLL_EN_MASK BIT(6)
48 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
49 /* CMN_REG(001e) */
50 #define LCPLL_PI_EN_MASK BIT(5)
51 #define LCPLL_100M_CLK_EN_MASK BIT(0)
52 /* CMN_REG(0025) */
53 #define LCPLL_PMS_IQDIV_RSTN BIT(4)
54 /* CMN_REG(0028) */
55 #define LCPLL_SDC_FRAC_EN BIT(2)
56 #define LCPLL_SDC_FRAC_RSTN BIT(0)
57 /* CMN_REG(002d) */
58 #define LCPLL_SDC_N_MASK GENMASK(3, 1)
59 /* CMN_REG(002e) */
60 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
61 /* CMN_REG(002f) */
62 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
63 #define LCPLL_SDC_NDIV_RSTN BIT(0)
64 /* CMN_REG(003d) */
65 #define ROPLL_LCVCO_EN BIT(4)
66 /* CMN_REG(004e) */
67 #define ROPLL_PI_EN BIT(5)
68 /* CMN_REG(005c) */
69 #define ROPLL_PMS_IQDIV_RSTN BIT(5)
70 /* CMN_REG(005e) */
71 #define ROPLL_SDM_EN_MASK BIT(6)
72 #define ROPLL_SDM_FRAC_EN_RBR BIT(3)
73 #define ROPLL_SDM_FRAC_EN_HBR BIT(2)
74 #define ROPLL_SDM_FRAC_EN_HBR2 BIT(1)
75 #define ROPLL_SDM_FRAC_EN_HBR3 BIT(0)
76 /* CMN_REG(0064) */
77 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
78 /* CMN_REG(0069) */
79 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
80 /* CMN_REG(0074) */
81 #define ROPLL_SDC_NDIV_RSTN BIT(2)
82 #define ROPLL_SSC_EN BIT(0)
83 /* CMN_REG(0081) */
84 #define OVRD_PLL_CD_CLK_EN BIT(8)
85 #define PLL_CD_HSCLK_EAST_EN BIT(0)
86 /* CMN_REG(0086) */
87 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
88 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
89 #define PLL_PCG_CLK_EN BIT(0)
90 /* CMN_REG(0087) */
91 #define PLL_FRL_MODE_EN BIT(3)
92 #define PLL_TX_HS_CLK_EN BIT(2)
93 /* CMN_REG(0089) */
94 #define LCPLL_ALONE_MODE BIT(1)
95 /* CMN_REG(0097) */
96 #define DIG_CLK_SEL BIT(1)
97 #define ROPLL_REF BIT(1)
98 #define LCPLL_REF 0
99 /* CMN_REG(0099) */
100 #define CMN_ROPLL_ALONE_MODE BIT(2)
101 #define ROPLL_ALONE_MODE BIT(2)
102 /* CMN_REG(009a) */
103 #define HS_SPEED_SEL BIT(0)
104 #define DIV_10_CLOCK BIT(0)
105 /* CMN_REG(009b) */
106 #define IS_SPEED_SEL BIT(4)
107 #define LINK_SYMBOL_CLOCK BIT(4)
108 #define LINK_SYMBOL_CLOCK1_2 0
109
110 /* SB_REG(0102) */
111 #define OVRD_SB_RXTERM_EN_MASK BIT(5)
112 #define SB_RXTERM_EN_MASK BIT(4)
113 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
114 /* SB_REG(0103) */
115 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)
116 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1)
117 #define SB_RX_RESCAL_DONE_MASK BIT(0)
118 /* SB_REG(0104) */
119 #define OVRD_SB_EN_MASK BIT(5)
120 #define SB_EN_MASK BIT(4)
121 /* SB_REG(0105) */
122 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
123 #define SB_EARC_CMDC_EN_MASK BIT(5)
124 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
125 /* SB_REG(0106) */
126 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
127 /* SB_REG(0109) */
128 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
129 /* SB_REG(010f) */
130 #define OVRD_SB_VREG_EN_MASK BIT(7)
131 #define SB_VREG_EN_MASK BIT(6)
132 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5)
133 #define SB_VREG_LPF_BYPASS_MASK BIT(4)
134 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
135 /* SB_REG(0110) */
136 #define ANA_SB_VREG_REF_SEL_MASK BIT(0)
137 /* SB_REG(0113) */
138 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
139 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
140 /* SB_REG(0114) */
141 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)
142 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
143 /* SB_REG(0115) */
144 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)
145 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
146 /* SB_REG(0116) */
147 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
148 /* SB_REG(0117) */
149 #define FAST_PULSE_TIME_MASK GENMASK(3, 0)
150 /* SB_REG(011b) */
151 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
152 #define SB_AFC_TOL_MASK GENMASK(3, 0)
153 /* SB_REG(011f) */
154 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
155 #define SB_RCAL_RSTN_MASK BIT(1)
156 /* SB_REG(0120) */
157 #define SB_EARC_EN_MASK BIT(1)
158 #define SB_EARC_AFC_EN_MASK BIT(2)
159 /* SB_REG(0123) */
160 #define OVRD_SB_READY_MASK BIT(5)
161 #define SB_READY_MASK BIT(4)
162
163 /* LNTOP_REG(0200) */
164 #define PROTOCOL_SEL BIT(2)
165 #define HDMI_MODE BIT(2)
166 #define HDMI_TMDS_FRL_SEL BIT(1)
167 /* LNTOP_REG(0206) */
168 #define DATA_BUS_SEL BIT(0)
169 #define DATA_BUS_36_40 BIT(0)
170 /* LNTOP_REG(0207) */
171 #define LANE_EN 0xf
172 #define ALL_LANE_EN 0xf
173
174 /* LANE_REG(0312) */
175 #define LN0_TX_SER_RATE_SEL_RBR BIT(5)
176 #define LN0_TX_SER_RATE_SEL_HBR BIT(4)
177 #define LN0_TX_SER_RATE_SEL_HBR2 BIT(3)
178 #define LN0_TX_SER_RATE_SEL_HBR3 BIT(2)
179 /* LANE_REG(0412) */
180 #define LN1_TX_SER_RATE_SEL_RBR BIT(5)
181 #define LN1_TX_SER_RATE_SEL_HBR BIT(4)
182 #define LN1_TX_SER_RATE_SEL_HBR2 BIT(3)
183 #define LN1_TX_SER_RATE_SEL_HBR3 BIT(2)
184 /* LANE_REG(0512) */
185 #define LN2_TX_SER_RATE_SEL_RBR BIT(5)
186 #define LN2_TX_SER_RATE_SEL_HBR BIT(4)
187 #define LN2_TX_SER_RATE_SEL_HBR2 BIT(3)
188 #define LN2_TX_SER_RATE_SEL_HBR3 BIT(2)
189 /* LANE_REG(0612) */
190 #define LN3_TX_SER_RATE_SEL_RBR BIT(5)
191 #define LN3_TX_SER_RATE_SEL_HBR BIT(4)
192 #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
193 #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
194
195 #define HDMI20_MAX_RATE 600000000
196
197 struct lcpll_config {
198 u32 bit_rate;
199 u8 lcvco_mode_en;
200 u8 pi_en;
201 u8 clk_en_100m;
202 u8 pms_mdiv;
203 u8 pms_mdiv_afc;
204 u8 pms_pdiv;
205 u8 pms_refdiv;
206 u8 pms_sdiv;
207 u8 pi_cdiv_rstn;
208 u8 pi_cdiv_sel;
209 u8 sdm_en;
210 u8 sdm_rstn;
211 u8 sdc_frac_en;
212 u8 sdc_rstn;
213 u8 sdm_deno;
214 u8 sdm_num_sign;
215 u8 sdm_num;
216 u8 sdc_n;
217 u8 sdc_n2;
218 u8 sdc_num;
219 u8 sdc_deno;
220 u8 sdc_ndiv_rstn;
221 u8 ssc_en;
222 u8 ssc_fm_dev;
223 u8 ssc_fm_freq;
224 u8 ssc_clk_div_sel;
225 u8 cd_tx_ser_rate_sel;
226 };
227
228 struct ropll_config {
229 u32 bit_rate;
230 u8 pms_mdiv;
231 u8 pms_mdiv_afc;
232 u8 pms_pdiv;
233 u8 pms_refdiv;
234 u8 pms_sdiv;
235 u8 pms_iqdiv_rstn;
236 u8 ref_clk_sel;
237 u8 sdm_en;
238 u8 sdm_rstn;
239 u8 sdc_frac_en;
240 u8 sdc_rstn;
241 u8 sdm_clk_div;
242 u8 sdm_deno;
243 u8 sdm_num_sign;
244 u8 sdm_num;
245 u8 sdc_n;
246 u8 sdc_num;
247 u8 sdc_deno;
248 u8 sdc_ndiv_rstn;
249 u8 ssc_en;
250 u8 ssc_fm_dev;
251 u8 ssc_fm_freq;
252 u8 ssc_clk_div_sel;
253 u8 ana_cpp_ctrl;
254 u8 ana_lpf_c_sel;
255 u8 cd_tx_ser_rate_sel;
256 };
257
258 enum rk_hdptx_reset {
259 RST_APB = 0,
260 RST_INIT,
261 RST_CMN,
262 RST_LANE,
263 RST_MAX
264 };
265
266 #define MAX_HDPTX_PHY_NUM 2
267
268 struct rk_hdptx_phy_cfg {
269 unsigned int num_phys;
270 unsigned int phy_ids[MAX_HDPTX_PHY_NUM];
271 };
272
273 struct rk_hdptx_phy {
274 struct device *dev;
275 struct regmap *regmap;
276 struct regmap *grf;
277
278 /* PHY const config */
279 const struct rk_hdptx_phy_cfg *cfgs;
280 int phy_id;
281
282 struct phy *phy;
283 struct phy_config *phy_cfg;
284 struct clk_bulk_data *clks;
285 int nr_clks;
286 struct reset_control_bulk_data rsts[RST_MAX];
287
288 /* clk provider */
289 struct clk_hw hw;
290 unsigned long rate;
291
292 atomic_t usage_count;
293 };
294
295 static const struct ropll_config ropll_tmds_cfg[] = {
296 { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
297 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
298 { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
299 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
300 { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
301 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
302 { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
303 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
304 { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
305 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
306 { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
307 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
308 { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
309 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
310 { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
311 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
312 { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
313 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
314 { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
315 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
316 { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
317 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
318 { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
319 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
320 { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
321 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
322 { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
323 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
324 { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
325 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
326 { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
327 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
328 { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
329 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
330 { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
331 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
332 { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
333 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
334 { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
335 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
336 };
337
338 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
339 REG_SEQ0(CMN_REG(0009), 0x0c),
340 REG_SEQ0(CMN_REG(000a), 0x83),
341 REG_SEQ0(CMN_REG(000b), 0x06),
342 REG_SEQ0(CMN_REG(000c), 0x20),
343 REG_SEQ0(CMN_REG(000d), 0xb8),
344 REG_SEQ0(CMN_REG(000e), 0x0f),
345 REG_SEQ0(CMN_REG(000f), 0x0f),
346 REG_SEQ0(CMN_REG(0010), 0x04),
347 REG_SEQ0(CMN_REG(0011), 0x00),
348 REG_SEQ0(CMN_REG(0012), 0x26),
349 REG_SEQ0(CMN_REG(0013), 0x22),
350 REG_SEQ0(CMN_REG(0014), 0x24),
351 REG_SEQ0(CMN_REG(0015), 0x77),
352 REG_SEQ0(CMN_REG(0016), 0x08),
353 REG_SEQ0(CMN_REG(0017), 0x00),
354 REG_SEQ0(CMN_REG(0018), 0x04),
355 REG_SEQ0(CMN_REG(0019), 0x48),
356 REG_SEQ0(CMN_REG(001a), 0x01),
357 REG_SEQ0(CMN_REG(001b), 0x00),
358 REG_SEQ0(CMN_REG(001c), 0x01),
359 REG_SEQ0(CMN_REG(001d), 0x64),
360 REG_SEQ0(CMN_REG(001f), 0x00),
361 REG_SEQ0(CMN_REG(0026), 0x53),
362 REG_SEQ0(CMN_REG(0029), 0x01),
363 REG_SEQ0(CMN_REG(0030), 0x00),
364 REG_SEQ0(CMN_REG(0031), 0x20),
365 REG_SEQ0(CMN_REG(0032), 0x30),
366 REG_SEQ0(CMN_REG(0033), 0x0b),
367 REG_SEQ0(CMN_REG(0034), 0x23),
368 REG_SEQ0(CMN_REG(0035), 0x00),
369 REG_SEQ0(CMN_REG(0038), 0x00),
370 REG_SEQ0(CMN_REG(0039), 0x00),
371 REG_SEQ0(CMN_REG(003a), 0x00),
372 REG_SEQ0(CMN_REG(003b), 0x00),
373 REG_SEQ0(CMN_REG(003c), 0x80),
374 REG_SEQ0(CMN_REG(003e), 0x0c),
375 REG_SEQ0(CMN_REG(003f), 0x83),
376 REG_SEQ0(CMN_REG(0040), 0x06),
377 REG_SEQ0(CMN_REG(0041), 0x20),
378 REG_SEQ0(CMN_REG(0042), 0xb8),
379 REG_SEQ0(CMN_REG(0043), 0x00),
380 REG_SEQ0(CMN_REG(0044), 0x46),
381 REG_SEQ0(CMN_REG(0045), 0x24),
382 REG_SEQ0(CMN_REG(0046), 0xff),
383 REG_SEQ0(CMN_REG(0047), 0x00),
384 REG_SEQ0(CMN_REG(0048), 0x44),
385 REG_SEQ0(CMN_REG(0049), 0xfa),
386 REG_SEQ0(CMN_REG(004a), 0x08),
387 REG_SEQ0(CMN_REG(004b), 0x00),
388 REG_SEQ0(CMN_REG(004c), 0x01),
389 REG_SEQ0(CMN_REG(004d), 0x64),
390 REG_SEQ0(CMN_REG(004e), 0x14),
391 REG_SEQ0(CMN_REG(004f), 0x00),
392 REG_SEQ0(CMN_REG(0050), 0x00),
393 REG_SEQ0(CMN_REG(005d), 0x0c),
394 REG_SEQ0(CMN_REG(005f), 0x01),
395 REG_SEQ0(CMN_REG(006b), 0x04),
396 REG_SEQ0(CMN_REG(0073), 0x30),
397 REG_SEQ0(CMN_REG(0074), 0x00),
398 REG_SEQ0(CMN_REG(0075), 0x20),
399 REG_SEQ0(CMN_REG(0076), 0x30),
400 REG_SEQ0(CMN_REG(0077), 0x08),
401 REG_SEQ0(CMN_REG(0078), 0x0c),
402 REG_SEQ0(CMN_REG(0079), 0x00),
403 REG_SEQ0(CMN_REG(007b), 0x00),
404 REG_SEQ0(CMN_REG(007c), 0x00),
405 REG_SEQ0(CMN_REG(007d), 0x00),
406 REG_SEQ0(CMN_REG(007e), 0x00),
407 REG_SEQ0(CMN_REG(007f), 0x00),
408 REG_SEQ0(CMN_REG(0080), 0x00),
409 REG_SEQ0(CMN_REG(0081), 0x09),
410 REG_SEQ0(CMN_REG(0082), 0x04),
411 REG_SEQ0(CMN_REG(0083), 0x24),
412 REG_SEQ0(CMN_REG(0084), 0x20),
413 REG_SEQ0(CMN_REG(0085), 0x03),
414 REG_SEQ0(CMN_REG(0086), 0x01),
415 REG_SEQ0(CMN_REG(0087), 0x0c),
416 REG_SEQ0(CMN_REG(008a), 0x55),
417 REG_SEQ0(CMN_REG(008b), 0x25),
418 REG_SEQ0(CMN_REG(008c), 0x2c),
419 REG_SEQ0(CMN_REG(008d), 0x22),
420 REG_SEQ0(CMN_REG(008e), 0x14),
421 REG_SEQ0(CMN_REG(008f), 0x20),
422 REG_SEQ0(CMN_REG(0090), 0x00),
423 REG_SEQ0(CMN_REG(0091), 0x00),
424 REG_SEQ0(CMN_REG(0092), 0x00),
425 REG_SEQ0(CMN_REG(0093), 0x00),
426 REG_SEQ0(CMN_REG(009a), 0x11),
427 REG_SEQ0(CMN_REG(009b), 0x10),
428 };
429
430 static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
431 REG_SEQ0(CMN_REG(0008), 0x00),
432 REG_SEQ0(CMN_REG(0011), 0x01),
433 REG_SEQ0(CMN_REG(0017), 0x20),
434 REG_SEQ0(CMN_REG(001e), 0x14),
435 REG_SEQ0(CMN_REG(0020), 0x00),
436 REG_SEQ0(CMN_REG(0021), 0x00),
437 REG_SEQ0(CMN_REG(0022), 0x11),
438 REG_SEQ0(CMN_REG(0023), 0x00),
439 REG_SEQ0(CMN_REG(0024), 0x00),
440 REG_SEQ0(CMN_REG(0025), 0x53),
441 REG_SEQ0(CMN_REG(0026), 0x00),
442 REG_SEQ0(CMN_REG(0027), 0x00),
443 REG_SEQ0(CMN_REG(0028), 0x01),
444 REG_SEQ0(CMN_REG(002a), 0x00),
445 REG_SEQ0(CMN_REG(002b), 0x00),
446 REG_SEQ0(CMN_REG(002c), 0x00),
447 REG_SEQ0(CMN_REG(002d), 0x00),
448 REG_SEQ0(CMN_REG(002e), 0x04),
449 REG_SEQ0(CMN_REG(002f), 0x00),
450 REG_SEQ0(CMN_REG(0030), 0x20),
451 REG_SEQ0(CMN_REG(0031), 0x30),
452 REG_SEQ0(CMN_REG(0032), 0x0b),
453 REG_SEQ0(CMN_REG(0033), 0x23),
454 REG_SEQ0(CMN_REG(0034), 0x00),
455 REG_SEQ0(CMN_REG(003d), 0x40),
456 REG_SEQ0(CMN_REG(0042), 0x78),
457 REG_SEQ0(CMN_REG(004e), 0x34),
458 REG_SEQ0(CMN_REG(005c), 0x25),
459 REG_SEQ0(CMN_REG(005e), 0x4f),
460 REG_SEQ0(CMN_REG(0074), 0x04),
461 REG_SEQ0(CMN_REG(0081), 0x01),
462 REG_SEQ0(CMN_REG(0087), 0x04),
463 REG_SEQ0(CMN_REG(0089), 0x00),
464 REG_SEQ0(CMN_REG(0095), 0x00),
465 REG_SEQ0(CMN_REG(0097), 0x02),
466 REG_SEQ0(CMN_REG(0099), 0x04),
467 REG_SEQ0(CMN_REG(009b), 0x00),
468 };
469
470 static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
471 REG_SEQ0(SB_REG(0114), 0x00),
472 REG_SEQ0(SB_REG(0115), 0x00),
473 REG_SEQ0(SB_REG(0116), 0x00),
474 REG_SEQ0(SB_REG(0117), 0x00),
475 };
476
477 static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
478 REG_SEQ0(LNTOP_REG(0201), 0x00),
479 REG_SEQ0(LNTOP_REG(0202), 0x00),
480 REG_SEQ0(LNTOP_REG(0203), 0x0f),
481 REG_SEQ0(LNTOP_REG(0204), 0xff),
482 REG_SEQ0(LNTOP_REG(0205), 0xff),
483 };
484
485 static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
486 REG_SEQ0(LNTOP_REG(0201), 0x07),
487 REG_SEQ0(LNTOP_REG(0202), 0xc1),
488 REG_SEQ0(LNTOP_REG(0203), 0xf0),
489 REG_SEQ0(LNTOP_REG(0204), 0x7c),
490 REG_SEQ0(LNTOP_REG(0205), 0x1f),
491 };
492
493 static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
494 REG_SEQ0(LANE_REG(0303), 0x0c),
495 REG_SEQ0(LANE_REG(0307), 0x20),
496 REG_SEQ0(LANE_REG(030a), 0x17),
497 REG_SEQ0(LANE_REG(030b), 0x77),
498 REG_SEQ0(LANE_REG(030c), 0x77),
499 REG_SEQ0(LANE_REG(030d), 0x77),
500 REG_SEQ0(LANE_REG(030e), 0x38),
501 REG_SEQ0(LANE_REG(0310), 0x03),
502 REG_SEQ0(LANE_REG(0311), 0x0f),
503 REG_SEQ0(LANE_REG(0316), 0x02),
504 REG_SEQ0(LANE_REG(031b), 0x01),
505 REG_SEQ0(LANE_REG(031f), 0x15),
506 REG_SEQ0(LANE_REG(0320), 0xa0),
507 REG_SEQ0(LANE_REG(0403), 0x0c),
508 REG_SEQ0(LANE_REG(0407), 0x20),
509 REG_SEQ0(LANE_REG(040a), 0x17),
510 REG_SEQ0(LANE_REG(040b), 0x77),
511 REG_SEQ0(LANE_REG(040c), 0x77),
512 REG_SEQ0(LANE_REG(040d), 0x77),
513 REG_SEQ0(LANE_REG(040e), 0x38),
514 REG_SEQ0(LANE_REG(0410), 0x03),
515 REG_SEQ0(LANE_REG(0411), 0x0f),
516 REG_SEQ0(LANE_REG(0416), 0x02),
517 REG_SEQ0(LANE_REG(041b), 0x01),
518 REG_SEQ0(LANE_REG(041f), 0x15),
519 REG_SEQ0(LANE_REG(0420), 0xa0),
520 REG_SEQ0(LANE_REG(0503), 0x0c),
521 REG_SEQ0(LANE_REG(0507), 0x20),
522 REG_SEQ0(LANE_REG(050a), 0x17),
523 REG_SEQ0(LANE_REG(050b), 0x77),
524 REG_SEQ0(LANE_REG(050c), 0x77),
525 REG_SEQ0(LANE_REG(050d), 0x77),
526 REG_SEQ0(LANE_REG(050e), 0x38),
527 REG_SEQ0(LANE_REG(0510), 0x03),
528 REG_SEQ0(LANE_REG(0511), 0x0f),
529 REG_SEQ0(LANE_REG(0516), 0x02),
530 REG_SEQ0(LANE_REG(051b), 0x01),
531 REG_SEQ0(LANE_REG(051f), 0x15),
532 REG_SEQ0(LANE_REG(0520), 0xa0),
533 REG_SEQ0(LANE_REG(0603), 0x0c),
534 REG_SEQ0(LANE_REG(0607), 0x20),
535 REG_SEQ0(LANE_REG(060a), 0x17),
536 REG_SEQ0(LANE_REG(060b), 0x77),
537 REG_SEQ0(LANE_REG(060c), 0x77),
538 REG_SEQ0(LANE_REG(060d), 0x77),
539 REG_SEQ0(LANE_REG(060e), 0x38),
540 REG_SEQ0(LANE_REG(0610), 0x03),
541 REG_SEQ0(LANE_REG(0611), 0x0f),
542 REG_SEQ0(LANE_REG(0616), 0x02),
543 REG_SEQ0(LANE_REG(061b), 0x01),
544 REG_SEQ0(LANE_REG(061f), 0x15),
545 REG_SEQ0(LANE_REG(0620), 0xa0),
546 };
547
548 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
549 REG_SEQ0(LANE_REG(0312), 0x00),
550 REG_SEQ0(LANE_REG(031e), 0x00),
551 REG_SEQ0(LANE_REG(0412), 0x00),
552 REG_SEQ0(LANE_REG(041e), 0x00),
553 REG_SEQ0(LANE_REG(0512), 0x00),
554 REG_SEQ0(LANE_REG(051e), 0x00),
555 REG_SEQ0(LANE_REG(0612), 0x00),
556 REG_SEQ0(LANE_REG(061e), 0x08),
557 REG_SEQ0(LANE_REG(0303), 0x2f),
558 REG_SEQ0(LANE_REG(0403), 0x2f),
559 REG_SEQ0(LANE_REG(0503), 0x2f),
560 REG_SEQ0(LANE_REG(0603), 0x2f),
561 REG_SEQ0(LANE_REG(0305), 0x03),
562 REG_SEQ0(LANE_REG(0405), 0x03),
563 REG_SEQ0(LANE_REG(0505), 0x03),
564 REG_SEQ0(LANE_REG(0605), 0x03),
565 REG_SEQ0(LANE_REG(0306), 0x1c),
566 REG_SEQ0(LANE_REG(0406), 0x1c),
567 REG_SEQ0(LANE_REG(0506), 0x1c),
568 REG_SEQ0(LANE_REG(0606), 0x1c),
569 };
570
rk_hdptx_phy_is_rw_reg(struct device * dev,unsigned int reg)571 static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
572 {
573 switch (reg) {
574 case 0x0000 ... 0x029c:
575 case 0x0400 ... 0x04a4:
576 case 0x0800 ... 0x08a4:
577 case 0x0c00 ... 0x0cb4:
578 case 0x1000 ... 0x10b4:
579 case 0x1400 ... 0x14b4:
580 case 0x1800 ... 0x18b4:
581 return true;
582 }
583
584 return false;
585 }
586
587 static const struct regmap_config rk_hdptx_phy_regmap_config = {
588 .reg_bits = 32,
589 .reg_stride = 4,
590 .val_bits = 32,
591 .writeable_reg = rk_hdptx_phy_is_rw_reg,
592 .readable_reg = rk_hdptx_phy_is_rw_reg,
593 .fast_io = true,
594 .max_register = 0x18b4,
595 };
596
597 #define rk_hdptx_multi_reg_write(hdptx, seq) \
598 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq))
599
rk_hdptx_pre_power_up(struct rk_hdptx_phy * hdptx)600 static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx)
601 {
602 u32 val;
603
604 reset_control_assert(hdptx->rsts[RST_APB].rstc);
605 usleep_range(20, 25);
606 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
607
608 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
609 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
610 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
611
612 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
613 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
614 }
615
rk_hdptx_post_enable_lane(struct rk_hdptx_phy * hdptx)616 static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
617 {
618 u32 val;
619 int ret;
620
621 reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
622
623 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
624 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
625 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
626
627 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
628 (val & HDPTX_O_PHY_RDY) &&
629 (val & HDPTX_O_PLL_LOCK_DONE),
630 100, 5000);
631 if (ret) {
632 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret);
633 return ret;
634 }
635
636 dev_dbg(hdptx->dev, "PHY lane locked\n");
637
638 return 0;
639 }
640
rk_hdptx_post_enable_pll(struct rk_hdptx_phy * hdptx)641 static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
642 {
643 u32 val;
644 int ret;
645
646 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
647 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
648 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
649
650 usleep_range(10, 15);
651 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
652
653 usleep_range(10, 15);
654 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
655 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
656
657 usleep_range(10, 15);
658 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
659
660 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
661 val & HDPTX_O_PHY_CLK_RDY, 20, 400);
662 if (ret) {
663 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret);
664 return ret;
665 }
666
667 dev_dbg(hdptx->dev, "PHY clk ready\n");
668
669 return 0;
670 }
671
rk_hdptx_phy_disable(struct rk_hdptx_phy * hdptx)672 static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
673 {
674 u32 val;
675
676 reset_control_assert(hdptx->rsts[RST_APB].rstc);
677 usleep_range(20, 30);
678 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
679
680 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
681 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
682 regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
683 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80);
684 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80);
685 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80);
686 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80);
687
688 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
689 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
690 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
691
692 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
693 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
694 }
695
rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,struct ropll_config * cfg)696 static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
697 struct ropll_config *cfg)
698 {
699 const unsigned int fout = data_rate / 2, fref = 24000;
700 unsigned long k = 0, lc, k_sub, lc_sub;
701 unsigned int fvco, sdc;
702 u32 mdiv, sdiv, n = 8;
703
704 if (fout > 0xfffffff)
705 return false;
706
707 for (sdiv = 16; sdiv >= 1; sdiv--) {
708 if (sdiv % 2 && sdiv != 1)
709 continue;
710
711 fvco = fout * sdiv;
712
713 if (fvco < 2000000 || fvco > 4000000)
714 continue;
715
716 mdiv = DIV_ROUND_UP(fvco, fref);
717 if (mdiv < 20 || mdiv > 255)
718 continue;
719
720 if (fref * mdiv - fvco) {
721 for (sdc = 264000; sdc <= 750000; sdc += fref)
722 if (sdc * n > fref * mdiv)
723 break;
724
725 if (sdc > 750000)
726 continue;
727
728 rational_best_approximation(fref * mdiv - fvco,
729 sdc / 16,
730 GENMASK(6, 0),
731 GENMASK(7, 0),
732 &k, &lc);
733
734 rational_best_approximation(sdc * n - fref * mdiv,
735 sdc,
736 GENMASK(6, 0),
737 GENMASK(7, 0),
738 &k_sub, &lc_sub);
739 }
740
741 break;
742 }
743
744 if (sdiv < 1)
745 return false;
746
747 if (cfg) {
748 cfg->pms_mdiv = mdiv;
749 cfg->pms_mdiv_afc = mdiv;
750 cfg->pms_pdiv = 1;
751 cfg->pms_refdiv = 1;
752 cfg->pms_sdiv = sdiv - 1;
753
754 cfg->sdm_en = k > 0 ? 1 : 0;
755 if (cfg->sdm_en) {
756 cfg->sdm_deno = lc;
757 cfg->sdm_num_sign = 1;
758 cfg->sdm_num = k;
759 cfg->sdc_n = n - 3;
760 cfg->sdc_num = k_sub;
761 cfg->sdc_deno = lc_sub;
762 }
763 }
764
765 return true;
766 }
767
rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy * hdptx,unsigned int rate)768 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
769 unsigned int rate)
770 {
771 const struct ropll_config *cfg = NULL;
772 struct ropll_config rc = {0};
773 int i;
774
775 hdptx->rate = rate * 100;
776
777 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
778 if (rate == ropll_tmds_cfg[i].bit_rate) {
779 cfg = &ropll_tmds_cfg[i];
780 break;
781 }
782
783 if (!cfg) {
784 if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) {
785 cfg = &rc;
786 } else {
787 dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
788 return -EINVAL;
789 }
790 }
791
792 dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n",
793 cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
794 cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
795
796 rk_hdptx_pre_power_up(hdptx);
797
798 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
799 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
800
801 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
802 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
803 regmap_write(hdptx->regmap, CMN_REG(0059),
804 (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
805 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
806
807 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
808 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
809 if (!cfg->sdm_en)
810 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
811
812 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
813 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
814
815 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
816 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
817
818 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
819 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
820
821 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
822 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
823
824 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
825 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
826
827 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
828 PLL_PCG_CLK_EN);
829
830 return rk_hdptx_post_enable_pll(hdptx);
831 }
832
rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy * hdptx,unsigned int rate)833 static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
834 unsigned int rate)
835 {
836 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
837
838 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
839
840 if (rate >= 3400000) {
841 /* For 1/40 bitrate clk */
842 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
843 } else {
844 /* For 1/10 bitrate clk */
845 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
846 }
847
848 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
849 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
850
851 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
852 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
853
854 return rk_hdptx_post_enable_lane(hdptx);
855 }
856
rk_hdptx_phy_consumer_get(struct rk_hdptx_phy * hdptx,unsigned int rate)857 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
858 unsigned int rate)
859 {
860 u32 status;
861 int ret;
862
863 if (atomic_inc_return(&hdptx->usage_count) > 1)
864 return 0;
865
866 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
867 if (ret)
868 goto dec_usage;
869
870 if (status & HDPTX_O_PLL_LOCK_DONE)
871 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
872
873 if (rate) {
874 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
875 if (ret)
876 goto dec_usage;
877 }
878
879 return 0;
880
881 dec_usage:
882 atomic_dec(&hdptx->usage_count);
883 return ret;
884 }
885
rk_hdptx_phy_consumer_put(struct rk_hdptx_phy * hdptx,bool force)886 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
887 {
888 u32 status;
889 int ret;
890
891 ret = atomic_dec_return(&hdptx->usage_count);
892 if (ret > 0)
893 return 0;
894
895 if (ret < 0) {
896 dev_warn(hdptx->dev, "Usage count underflow!\n");
897 ret = -EINVAL;
898 } else {
899 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
900 if (!ret) {
901 if (status & HDPTX_O_PLL_LOCK_DONE)
902 rk_hdptx_phy_disable(hdptx);
903 return 0;
904 } else if (force) {
905 return 0;
906 }
907 }
908
909 atomic_inc(&hdptx->usage_count);
910 return ret;
911 }
912
rk_hdptx_phy_power_on(struct phy * phy)913 static int rk_hdptx_phy_power_on(struct phy *phy)
914 {
915 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
916 int bus_width = phy_get_bus_width(hdptx->phy);
917 int ret;
918
919 /*
920 * FIXME: Temporary workaround to pass pixel_clk_rate
921 * from the HDMI bridge driver until phy_configure_opts_hdmi
922 * becomes available in the PHY API.
923 */
924 unsigned int rate = bus_width & 0xfffffff;
925
926 dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
927 __func__, bus_width, rate);
928
929 ret = rk_hdptx_phy_consumer_get(hdptx, rate);
930 if (ret)
931 return ret;
932
933 ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
934 if (ret)
935 rk_hdptx_phy_consumer_put(hdptx, true);
936
937 return ret;
938 }
939
rk_hdptx_phy_power_off(struct phy * phy)940 static int rk_hdptx_phy_power_off(struct phy *phy)
941 {
942 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
943
944 return rk_hdptx_phy_consumer_put(hdptx, false);
945 }
946
947 static const struct phy_ops rk_hdptx_phy_ops = {
948 .power_on = rk_hdptx_phy_power_on,
949 .power_off = rk_hdptx_phy_power_off,
950 .owner = THIS_MODULE,
951 };
952
to_rk_hdptx_phy(struct clk_hw * hw)953 static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
954 {
955 return container_of(hw, struct rk_hdptx_phy, hw);
956 }
957
rk_hdptx_phy_clk_prepare(struct clk_hw * hw)958 static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
959 {
960 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
961
962 return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
963 }
964
rk_hdptx_phy_clk_unprepare(struct clk_hw * hw)965 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
966 {
967 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
968
969 rk_hdptx_phy_consumer_put(hdptx, true);
970 }
971
rk_hdptx_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)972 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
973 unsigned long parent_rate)
974 {
975 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
976
977 return hdptx->rate;
978 }
979
rk_hdptx_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)980 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
981 unsigned long *parent_rate)
982 {
983 u32 bit_rate = rate / 100;
984 int i;
985
986 if (rate > HDMI20_MAX_RATE)
987 return rate;
988
989 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
990 if (bit_rate == ropll_tmds_cfg[i].bit_rate)
991 break;
992
993 if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
994 !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
995 return -EINVAL;
996
997 return rate;
998 }
999
rk_hdptx_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1000 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1001 unsigned long parent_rate)
1002 {
1003 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1004
1005 return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
1006 }
1007
1008 static const struct clk_ops hdptx_phy_clk_ops = {
1009 .prepare = rk_hdptx_phy_clk_prepare,
1010 .unprepare = rk_hdptx_phy_clk_unprepare,
1011 .recalc_rate = rk_hdptx_phy_clk_recalc_rate,
1012 .round_rate = rk_hdptx_phy_clk_round_rate,
1013 .set_rate = rk_hdptx_phy_clk_set_rate,
1014 };
1015
rk_hdptx_phy_clk_register(struct rk_hdptx_phy * hdptx)1016 static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
1017 {
1018 struct device *dev = hdptx->dev;
1019 const char *name, *pname;
1020 struct clk *refclk;
1021 int ret;
1022
1023 refclk = devm_clk_get(dev, "ref");
1024 if (IS_ERR(refclk))
1025 return dev_err_probe(dev, PTR_ERR(refclk),
1026 "Failed to get ref clock\n");
1027
1028 name = hdptx->phy_id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
1029 pname = __clk_get_name(refclk);
1030
1031 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
1032 CLK_GET_RATE_NOCACHE);
1033
1034 ret = devm_clk_hw_register(dev, &hdptx->hw);
1035 if (ret)
1036 return dev_err_probe(dev, ret, "Failed to register clock\n");
1037
1038 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
1039 if (ret)
1040 return dev_err_probe(dev, ret,
1041 "Failed to register clk provider\n");
1042 return 0;
1043 }
1044
rk_hdptx_phy_runtime_suspend(struct device * dev)1045 static int rk_hdptx_phy_runtime_suspend(struct device *dev)
1046 {
1047 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1048
1049 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
1050
1051 return 0;
1052 }
1053
rk_hdptx_phy_runtime_resume(struct device * dev)1054 static int rk_hdptx_phy_runtime_resume(struct device *dev)
1055 {
1056 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1057 int ret;
1058
1059 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
1060 if (ret)
1061 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret);
1062
1063 return ret;
1064 }
1065
rk_hdptx_phy_probe(struct platform_device * pdev)1066 static int rk_hdptx_phy_probe(struct platform_device *pdev)
1067 {
1068 struct phy_provider *phy_provider;
1069 struct device *dev = &pdev->dev;
1070 struct rk_hdptx_phy *hdptx;
1071 struct resource *res;
1072 void __iomem *regs;
1073 int ret, id;
1074
1075 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
1076 if (!hdptx)
1077 return -ENOMEM;
1078
1079 hdptx->dev = dev;
1080
1081 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1082 if (IS_ERR(regs))
1083 return dev_err_probe(dev, PTR_ERR(regs),
1084 "Failed to ioremap resource\n");
1085
1086 hdptx->cfgs = device_get_match_data(dev);
1087 if (!hdptx->cfgs)
1088 return dev_err_probe(dev, -EINVAL, "missing match data\n");
1089
1090 /* find the phy-id from the io address */
1091 hdptx->phy_id = -ENODEV;
1092 for (id = 0; id < hdptx->cfgs->num_phys; id++) {
1093 if (res->start == hdptx->cfgs->phy_ids[id]) {
1094 hdptx->phy_id = id;
1095 break;
1096 }
1097 }
1098
1099 if (hdptx->phy_id < 0)
1100 return dev_err_probe(dev, -ENODEV, "no matching device found\n");
1101
1102 ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
1103 if (ret < 0)
1104 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1105 if (ret == 0)
1106 return dev_err_probe(dev, -EINVAL, "Missing clocks\n");
1107
1108 hdptx->nr_clks = ret;
1109
1110 hdptx->regmap = devm_regmap_init_mmio(dev, regs,
1111 &rk_hdptx_phy_regmap_config);
1112 if (IS_ERR(hdptx->regmap))
1113 return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
1114 "Failed to init regmap\n");
1115
1116 hdptx->rsts[RST_APB].id = "apb";
1117 hdptx->rsts[RST_INIT].id = "init";
1118 hdptx->rsts[RST_CMN].id = "cmn";
1119 hdptx->rsts[RST_LANE].id = "lane";
1120
1121 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts);
1122 if (ret)
1123 return dev_err_probe(dev, ret, "Failed to get resets\n");
1124
1125 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1126 "rockchip,grf");
1127 if (IS_ERR(hdptx->grf))
1128 return dev_err_probe(dev, PTR_ERR(hdptx->grf),
1129 "Could not get GRF syscon\n");
1130
1131 platform_set_drvdata(pdev, hdptx);
1132
1133 ret = devm_pm_runtime_enable(dev);
1134 if (ret)
1135 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
1136
1137 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
1138 if (IS_ERR(hdptx->phy))
1139 return dev_err_probe(dev, PTR_ERR(hdptx->phy),
1140 "Failed to create HDMI PHY\n");
1141
1142 phy_set_drvdata(hdptx->phy, hdptx);
1143 phy_set_bus_width(hdptx->phy, 8);
1144
1145 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1146 if (IS_ERR(phy_provider))
1147 return dev_err_probe(dev, PTR_ERR(phy_provider),
1148 "Failed to register PHY provider\n");
1149
1150 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
1151 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
1152 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1153
1154 return rk_hdptx_phy_clk_register(hdptx);
1155 }
1156
1157 static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
1158 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend,
1159 rk_hdptx_phy_runtime_resume, NULL)
1160 };
1161
1162 static const struct rk_hdptx_phy_cfg rk3588_hdptx_phy_cfgs = {
1163 .num_phys = 2,
1164 .phy_ids = {
1165 0xfed60000,
1166 0xfed70000,
1167 },
1168 };
1169
1170 static const struct of_device_id rk_hdptx_phy_of_match[] = {
1171 {
1172 .compatible = "rockchip,rk3588-hdptx-phy",
1173 .data = &rk3588_hdptx_phy_cfgs
1174 },
1175 {}
1176 };
1177 MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match);
1178
1179 static struct platform_driver rk_hdptx_phy_driver = {
1180 .probe = rk_hdptx_phy_probe,
1181 .driver = {
1182 .name = "rockchip-hdptx-phy",
1183 .pm = &rk_hdptx_phy_pm_ops,
1184 .of_match_table = rk_hdptx_phy_of_match,
1185 },
1186 };
1187 module_platform_driver(rk_hdptx_phy_driver);
1188
1189 MODULE_AUTHOR("Algea Cao <[email protected]>");
1190 MODULE_AUTHOR("Cristian Ciocaltea <[email protected]>");
1191 MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver");
1192 MODULE_LICENSE("GPL");
1193