1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip PCIe PHY driver
4 *
5 * Copyright (C) 2016 Shawn Lin <[email protected]>
6 * Copyright (C) 2016 ROCKCHIP, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20
21 /*
22 * The higher 16-bit of this register is used for write protection
23 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
24 */
25 #define HIWORD_UPDATE(val, mask, shift) \
26 ((val) << (shift) | (mask) << ((shift) + 16))
27
28 #define PHY_MAX_LANE_NUM 4
29 #define PHY_CFG_DATA_SHIFT 7
30 #define PHY_CFG_ADDR_SHIFT 1
31 #define PHY_CFG_DATA_MASK 0xf
32 #define PHY_CFG_ADDR_MASK 0x3f
33 #define PHY_CFG_RD_MASK 0x3ff
34 #define PHY_CFG_WR_ENABLE 1
35 #define PHY_CFG_WR_DISABLE 1
36 #define PHY_CFG_WR_SHIFT 0
37 #define PHY_CFG_WR_MASK 1
38 #define PHY_CFG_PLL_LOCK 0x10
39 #define PHY_CFG_CLK_TEST 0x10
40 #define PHY_CFG_CLK_SCC 0x12
41 #define PHY_CFG_SEPE_RATE BIT(3)
42 #define PHY_CFG_PLL_100M BIT(3)
43 #define PHY_PLL_LOCKED BIT(9)
44 #define PHY_PLL_OUTPUT BIT(10)
45 #define PHY_LANE_A_STATUS 0x30
46 #define PHY_LANE_B_STATUS 0x31
47 #define PHY_LANE_C_STATUS 0x32
48 #define PHY_LANE_D_STATUS 0x33
49 #define PHY_LANE_RX_DET_SHIFT 11
50 #define PHY_LANE_RX_DET_TH 0x1
51 #define PHY_LANE_IDLE_OFF 0x1
52 #define PHY_LANE_IDLE_MASK 0x1
53 #define PHY_LANE_IDLE_A_SHIFT 3
54 #define PHY_LANE_IDLE_B_SHIFT 4
55 #define PHY_LANE_IDLE_C_SHIFT 5
56 #define PHY_LANE_IDLE_D_SHIFT 6
57
58 struct rockchip_pcie_data {
59 unsigned int pcie_conf;
60 unsigned int pcie_status;
61 unsigned int pcie_laneoff;
62 };
63
64 struct rockchip_pcie_phy {
65 const struct rockchip_pcie_data *phy_data;
66 struct regmap *reg_base;
67 struct phy_pcie_instance {
68 struct phy *phy;
69 u32 index;
70 } phys[PHY_MAX_LANE_NUM];
71 struct mutex pcie_mutex;
72 struct reset_control *phy_rst;
73 struct clk *clk_pciephy_ref;
74 int pwr_cnt;
75 int init_cnt;
76 };
77
to_pcie_phy(struct phy_pcie_instance * inst)78 static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
79 {
80 return container_of(inst, struct rockchip_pcie_phy,
81 phys[inst->index]);
82 }
83
rockchip_pcie_phy_of_xlate(struct device * dev,const struct of_phandle_args * args)84 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
85 const struct of_phandle_args *args)
86 {
87 struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
88
89 if (args->args_count == 0)
90 return rk_phy->phys[0].phy;
91
92 if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
93 return ERR_PTR(-ENODEV);
94
95 return rk_phy->phys[args->args[0]].phy;
96 }
97
98
phy_wr_cfg(struct rockchip_pcie_phy * rk_phy,u32 addr,u32 data)99 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
100 u32 addr, u32 data)
101 {
102 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
103 HIWORD_UPDATE(data,
104 PHY_CFG_DATA_MASK,
105 PHY_CFG_DATA_SHIFT) |
106 HIWORD_UPDATE(addr,
107 PHY_CFG_ADDR_MASK,
108 PHY_CFG_ADDR_SHIFT));
109 udelay(1);
110 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
111 HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
112 PHY_CFG_WR_MASK,
113 PHY_CFG_WR_SHIFT));
114 udelay(1);
115 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
116 HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
117 PHY_CFG_WR_MASK,
118 PHY_CFG_WR_SHIFT));
119 }
120
rockchip_pcie_phy_power_off(struct phy * phy)121 static int rockchip_pcie_phy_power_off(struct phy *phy)
122 {
123 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
124 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
125 int err = 0;
126
127 guard(mutex)(&rk_phy->pcie_mutex);
128
129 regmap_write(rk_phy->reg_base,
130 rk_phy->phy_data->pcie_laneoff,
131 HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
132 PHY_LANE_IDLE_MASK,
133 PHY_LANE_IDLE_A_SHIFT + inst->index));
134
135 if (--rk_phy->pwr_cnt) {
136 return 0;
137 }
138
139 err = reset_control_assert(rk_phy->phy_rst);
140 if (err) {
141 dev_err(&phy->dev, "assert phy_rst err %d\n", err);
142 rk_phy->pwr_cnt++;
143 regmap_write(rk_phy->reg_base,
144 rk_phy->phy_data->pcie_laneoff,
145 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
146 PHY_LANE_IDLE_MASK,
147 PHY_LANE_IDLE_A_SHIFT + inst->index));
148 return err;
149 }
150
151 return err;
152 }
153
rockchip_pcie_phy_power_on(struct phy * phy)154 static int rockchip_pcie_phy_power_on(struct phy *phy)
155 {
156 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
157 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
158 int err = 0;
159 u32 status;
160
161 guard(mutex)(&rk_phy->pcie_mutex);
162
163 if (rk_phy->pwr_cnt++) {
164 return 0;
165 }
166
167 err = reset_control_deassert(rk_phy->phy_rst);
168 if (err) {
169 dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
170 rk_phy->pwr_cnt--;
171 return err;
172 }
173
174 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
175 HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
176 PHY_CFG_ADDR_MASK,
177 PHY_CFG_ADDR_SHIFT));
178
179 regmap_write(rk_phy->reg_base,
180 rk_phy->phy_data->pcie_laneoff,
181 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
182 PHY_LANE_IDLE_MASK,
183 PHY_LANE_IDLE_A_SHIFT + inst->index));
184
185 /*
186 * No documented timeout value for phy operation below,
187 * so we make it large enough here. And we use loop-break
188 * method which should not be harmful.
189 */
190 err = regmap_read_poll_timeout(rk_phy->reg_base,
191 rk_phy->phy_data->pcie_status,
192 status,
193 status & PHY_PLL_LOCKED,
194 200, 100000);
195 if (err) {
196 dev_err(&phy->dev, "pll lock timeout!\n");
197 goto err_pll_lock;
198 }
199
200 phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
201 phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
202
203 err = regmap_read_poll_timeout(rk_phy->reg_base,
204 rk_phy->phy_data->pcie_status,
205 status,
206 !(status & PHY_PLL_OUTPUT),
207 200, 100000);
208 if (err) {
209 dev_err(&phy->dev, "pll output enable timeout!\n");
210 goto err_pll_lock;
211 }
212
213 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
214 HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
215 PHY_CFG_ADDR_MASK,
216 PHY_CFG_ADDR_SHIFT));
217
218 err = regmap_read_poll_timeout(rk_phy->reg_base,
219 rk_phy->phy_data->pcie_status,
220 status,
221 status & PHY_PLL_LOCKED,
222 200, 100000);
223 if (err) {
224 dev_err(&phy->dev, "pll relock timeout!\n");
225 goto err_pll_lock;
226 }
227
228 return err;
229
230 err_pll_lock:
231 reset_control_assert(rk_phy->phy_rst);
232 rk_phy->pwr_cnt--;
233 return err;
234 }
235
rockchip_pcie_phy_init(struct phy * phy)236 static int rockchip_pcie_phy_init(struct phy *phy)
237 {
238 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
239 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
240 int err = 0;
241
242 guard(mutex)(&rk_phy->pcie_mutex);
243
244 if (rk_phy->init_cnt++) {
245 return 0;
246 }
247
248 err = reset_control_assert(rk_phy->phy_rst);
249 if (err) {
250 dev_err(&phy->dev, "assert phy_rst err %d\n", err);
251 rk_phy->init_cnt--;
252 return err;
253 }
254
255 return err;
256 }
257
rockchip_pcie_phy_exit(struct phy * phy)258 static int rockchip_pcie_phy_exit(struct phy *phy)
259 {
260 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
261 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
262
263 guard(mutex)(&rk_phy->pcie_mutex);
264
265 if (--rk_phy->init_cnt)
266 goto err_init_cnt;
267
268 err_init_cnt:
269 return 0;
270 }
271
272 static const struct phy_ops ops = {
273 .init = rockchip_pcie_phy_init,
274 .exit = rockchip_pcie_phy_exit,
275 .power_on = rockchip_pcie_phy_power_on,
276 .power_off = rockchip_pcie_phy_power_off,
277 .owner = THIS_MODULE,
278 };
279
280 static const struct rockchip_pcie_data rk3399_pcie_data = {
281 .pcie_conf = 0xe220,
282 .pcie_status = 0xe2a4,
283 .pcie_laneoff = 0xe214,
284 };
285
286 static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
287 {
288 .compatible = "rockchip,rk3399-pcie-phy",
289 .data = &rk3399_pcie_data,
290 },
291 {}
292 };
293
294 MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
295
rockchip_pcie_phy_probe(struct platform_device * pdev)296 static int rockchip_pcie_phy_probe(struct platform_device *pdev)
297 {
298 struct device *dev = &pdev->dev;
299 struct rockchip_pcie_phy *rk_phy;
300 struct phy_provider *phy_provider;
301 struct regmap *grf;
302 int i;
303 u32 phy_num;
304
305 grf = syscon_node_to_regmap(dev->parent->of_node);
306 if (IS_ERR(grf)) {
307 dev_err(dev, "Cannot find GRF syscon\n");
308 return PTR_ERR(grf);
309 }
310
311 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
312 if (!rk_phy)
313 return -ENOMEM;
314
315 rk_phy->phy_data = device_get_match_data(&pdev->dev);
316 if (!rk_phy->phy_data)
317 return -EINVAL;
318
319 rk_phy->reg_base = grf;
320
321 mutex_init(&rk_phy->pcie_mutex);
322
323 rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
324 if (IS_ERR(rk_phy->phy_rst))
325 return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst),
326 "missing phy property for reset controller\n");
327
328 rk_phy->clk_pciephy_ref = devm_clk_get_enabled(dev, "refclk");
329 if (IS_ERR(rk_phy->clk_pciephy_ref))
330 return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->clk_pciephy_ref),
331 "failed to get phyclk\n");
332
333 /* parse #phy-cells to see if it's legacy PHY model */
334 if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
335 return -ENOENT;
336
337 phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
338 dev_dbg(dev, "phy number is %d\n", phy_num);
339
340 for (i = 0; i < phy_num; i++) {
341 rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
342 if (IS_ERR(rk_phy->phys[i].phy)) {
343 dev_err(dev, "failed to create PHY%d\n", i);
344 return PTR_ERR(rk_phy->phys[i].phy);
345 }
346 rk_phy->phys[i].index = i;
347 phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
348 }
349
350 platform_set_drvdata(pdev, rk_phy);
351 phy_provider = devm_of_phy_provider_register(dev,
352 rockchip_pcie_phy_of_xlate);
353
354 return PTR_ERR_OR_ZERO(phy_provider);
355 }
356
357 static struct platform_driver rockchip_pcie_driver = {
358 .probe = rockchip_pcie_phy_probe,
359 .driver = {
360 .name = "rockchip-pcie-phy",
361 .of_match_table = rockchip_pcie_phy_dt_ids,
362 },
363 };
364
365 module_platform_driver(rockchip_pcie_driver);
366
367 MODULE_AUTHOR("Shawn Lin <[email protected]>");
368 MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
369 MODULE_LICENSE("GPL v2");
370