1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Copyright (c) 2022 BayLibre, SAS
5 */
6 #include <linux/delay.h>
7 #include <linux/io.h>
8 #include <linux/mfd/syscon.h>
9 #include <linux/module.h>
10 #include <linux/phy/phy.h>
11 #include <linux/platform_device.h>
12 #include <linux/regulator/driver.h>
13 #include <linux/regulator/of_regulator.h>
14 #include <linux/types.h>
15 #include <linux/units.h>
16 #include <linux/nvmem-consumer.h>
17
18 #include "phy-mtk-io.h"
19 #include "phy-mtk-hdmi.h"
20 #include "phy-mtk-hdmi-mt8195.h"
21
mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy * hdmi_phy)22 static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy)
23 {
24 /* make data fifo writable for hdmi2.0 */
25 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN);
26 }
27
28 static void
mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy * hdmi_phy,bool enable)29 mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable)
30 {
31 void __iomem *regs = hdmi_phy->regs;
32
33 mtk_hdmi_ana_fifo_en(hdmi_phy);
34
35 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G,
36 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10
37 */
38 if (enable)
39 mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3);
40 else
41 mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV);
42 }
43
mtk_hdmi_pll_sel_src(struct clk_hw * hw)44 static void mtk_hdmi_pll_sel_src(struct clk_hw *hw)
45 {
46 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
47 void __iomem *regs = hdmi_phy->regs;
48
49 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL);
50 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL);
51
52 /* DA_HDMITX21_REF_CK for TXPLL input source */
53 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL);
54 }
55
mtk_hdmi_pll_perf(struct clk_hw * hw)56 static void mtk_hdmi_pll_perf(struct clk_hw *hw)
57 {
58 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
59 void __iomem *regs = hdmi_phy->regs;
60
61 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2);
62 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC);
63 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1);
64 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2);
65 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2);
66 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP);
67 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN);
68 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14);
69 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO);
70 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1);
71 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1);
72 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11);
73 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN);
74 }
75
mtk_hdmi_pll_set_hw(struct clk_hw * hw,u8 prediv,u8 fbkdiv_high,u32 fbkdiv_low,u8 fbkdiv_hs3,u8 posdiv1,u8 posdiv2,u8 txprediv,u8 txposdiv,u8 digital_div)76 static int mtk_hdmi_pll_set_hw(struct clk_hw *hw, u8 prediv,
77 u8 fbkdiv_high,
78 u32 fbkdiv_low,
79 u8 fbkdiv_hs3, u8 posdiv1,
80 u8 posdiv2, u8 txprediv,
81 u8 txposdiv,
82 u8 digital_div)
83 {
84 u8 txposdiv_value;
85 u8 div3_ctrl_value;
86 u8 posdiv_vallue;
87 u8 div_ctrl_value;
88 u8 reserve_3_2_value;
89 u8 prediv_value;
90 u8 reserve13_value;
91 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
92 void __iomem *regs = hdmi_phy->regs;
93
94 mtk_hdmi_pll_sel_src(hw);
95
96 mtk_hdmi_pll_perf(hw);
97
98 mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2);
99 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL);
100 mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2);
101 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB);
102 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN);
103 mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11);
104 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);
105
106 /* TXPOSDIV */
107 txposdiv_value = ilog2(txposdiv);
108
109 mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV, txposdiv_value);
110 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN);
111 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN);
112
113 /* TXPREDIV */
114 switch (txprediv) {
115 case 2:
116 div3_ctrl_value = 0x0;
117 posdiv_vallue = 0x0;
118 break;
119 case 4:
120 div3_ctrl_value = 0x0;
121 posdiv_vallue = 0x1;
122 break;
123 case 6:
124 div3_ctrl_value = 0x1;
125 posdiv_vallue = 0x0;
126 break;
127 case 12:
128 div3_ctrl_value = 0x1;
129 posdiv_vallue = 0x1;
130 break;
131 default:
132 return -EINVAL;
133 }
134
135 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value);
136 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv_vallue);
137
138 /* POSDIV1 */
139 switch (posdiv1) {
140 case 5:
141 div_ctrl_value = 0x0;
142 break;
143 case 10:
144 div_ctrl_value = 0x1;
145 break;
146 case 12:
147 div_ctrl_value = 0x2;
148 break;
149 case 15:
150 div_ctrl_value = 0x3;
151 break;
152 default:
153 return -EINVAL;
154 }
155
156 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value);
157
158 /* DE add new setting */
159 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14);
160
161 /* POSDIV2 */
162 switch (posdiv2) {
163 case 1:
164 reserve_3_2_value = 0x0;
165 break;
166 case 2:
167 reserve_3_2_value = 0x1;
168 break;
169 case 4:
170 reserve_3_2_value = 0x2;
171 break;
172 case 6:
173 reserve_3_2_value = 0x3;
174 break;
175 default:
176 return -EINVAL;
177 }
178
179 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2, reserve_3_2_value);
180
181 /* DE add new setting */
182 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2);
183
184 /* PREDIV */
185 prediv_value = ilog2(prediv);
186
187 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv_value);
188
189 /* FBKDIV_HS3 */
190 reserve13_value = ilog2(fbkdiv_hs3);
191
192 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13, reserve13_value);
193
194 /* FBDIV */
195 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, fbkdiv_high);
196 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fbkdiv_low);
197
198 /* Digital DIVIDER */
199 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL);
200
201 if (digital_div == 1) {
202 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK);
203 } else {
204 mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK);
205 mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1);
206 }
207
208 return 0;
209 }
210
mtk_hdmi_pll_calc(struct mtk_hdmi_phy * hdmi_phy,struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)211 static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
212 unsigned long rate, unsigned long parent_rate)
213 {
214 u8 digital_div, txprediv, txposdiv, fbkdiv_high, posdiv1, posdiv2;
215 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw;
216 u8 txpredivs[4] = { 2, 4, 6, 12 };
217 u32 fbkdiv_low;
218 int i;
219
220 pixel_clk = rate;
221 tmds_clk = pixel_clk;
222
223 if (tmds_clk < 25 * MEGA || tmds_clk > 594 * MEGA)
224 return -EINVAL;
225
226 if (tmds_clk >= 340 * MEGA)
227 hdmi_phy->tmds_over_340M = true;
228 else
229 hdmi_phy->tmds_over_340M = false;
230
231 /* in Hz */
232 da_hdmitx21_ref_ck = 26 * MEGA;
233
234 /* TXPOSDIV stage treatment:
235 * 0M < TMDS clk < 54M /8
236 * 54M <= TMDS clk < 148.35M /4
237 * 148.35M <=TMDS clk < 296.7M /2
238 * 296.7 <=TMDS clk <= 594M /1
239 */
240 if (tmds_clk < 54 * MEGA)
241 txposdiv = 8;
242 else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA)
243 txposdiv = 4;
244 else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 * MEGA)
245 txposdiv = 2;
246 else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA)
247 txposdiv = 1;
248 else
249 return -EINVAL;
250
251 /* calculate txprediv: can be 2, 4, 6, 12
252 * ICO clk = 5*TMDS_CLK*TXPOSDIV*TXPREDIV
253 * ICO clk constraint: 5G =< ICO clk <= 12G
254 */
255 for (i = 0; i < ARRAY_SIZE(txpredivs); i++) {
256 ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i];
257 if (ns_hdmipll_ck >= 5 * GIGA &&
258 ns_hdmipll_ck <= 12 * GIGA)
259 break;
260 }
261 if (i == (ARRAY_SIZE(txpredivs) - 1) &&
262 (ns_hdmipll_ck < 5 * GIGA || ns_hdmipll_ck > 12 * GIGA)) {
263 return -EINVAL;
264 }
265 if (i == ARRAY_SIZE(txpredivs))
266 return -EINVAL;
267
268 txprediv = txpredivs[i];
269
270 /* PCW calculation: FBKDIV
271 * formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3;
272 * RG_HDMITXPLL_FBKDIV[32:0]:
273 * [32,24] 9bit integer, [23,0]:24bit fraction
274 */
275 pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,
276 da_hdmitx21_ref_ck * PLL_FBKDIV_HS3);
277
278 if (pcw > GENMASK_ULL(32, 0))
279 return -EINVAL;
280
281 fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw);
282 fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw);
283
284 /* posdiv1:
285 * posdiv1 stage treatment according to color_depth:
286 * 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5,
287 * 36bit -> posdiv1 /15, 48bit -> posdiv1 /10
288 */
289 posdiv1 = 10;
290 posdiv2 = 1;
291
292 /* Digital clk divider, max /32 */
293 digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk);
294 if (!(digital_div <= 32 && digital_div >= 1))
295 return -EINVAL;
296
297 return mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
298 PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
299 txposdiv, digital_div);
300 }
301
mtk_hdmi_pll_drv_setting(struct clk_hw * hw)302 static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw)
303 {
304 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
305 void __iomem *regs = hdmi_phy->regs;
306 u8 data_channel_bias, clk_channel_bias;
307 u8 impedance, impedance_en;
308 u32 tmds_clk;
309 u32 pixel_clk = hdmi_phy->pll_rate;
310
311 tmds_clk = pixel_clk;
312
313 /* bias & impedance setting:
314 * 3G < data rate <= 6G: enable impedance 100ohm,
315 * data channel bias 24mA, clock channel bias 20mA
316 * pixel clk >= HD, 74.175MHZ <= pixel clk <= 300MHZ:
317 * enalbe impedance 100ohm
318 * data channel 20mA, clock channel 16mA
319 * 27M =< pixel clk < 74.175: disable impedance
320 * data channel & clock channel bias 10mA
321 */
322
323 /* 3G < data rate <= 6G, 300M < tmds rate <= 594M */
324 if (tmds_clk > 300 * MEGA && tmds_clk <= 594 * MEGA) {
325 data_channel_bias = 0x3c; /* 24mA */
326 clk_channel_bias = 0x34; /* 20mA */
327 impedance_en = 0xf;
328 impedance = 0x36; /* 100ohm */
329 } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) {
330 data_channel_bias = 0x34; /* 20mA */
331 clk_channel_bias = 0x2c; /* 16mA */
332 impedance_en = 0xf;
333 impedance = 0x36; /* 100ohm */
334 } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) {
335 data_channel_bias = 0x14; /* 10mA */
336 clk_channel_bias = 0x14; /* 10mA */
337 impedance_en = 0x0;
338 impedance = 0x0;
339 } else {
340 return -EINVAL;
341 }
342
343 /* bias */
344 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_channel_bias);
345 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_channel_bias);
346 mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_channel_bias);
347 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias);
348
349 /* impedance */
350 mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en);
351 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, impedance);
352 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, impedance);
353 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, impedance);
354 mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, impedance);
355
356 return 0;
357 }
358
mtk_hdmi_pll_prepare(struct clk_hw * hw)359 static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
360 {
361 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
362 void __iomem *regs = hdmi_phy->regs;
363
364 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN);
365
366 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_SER_EN);
367 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D0_DRV_OP_EN);
368 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D1_DRV_OP_EN);
369 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D2_DRV_OP_EN);
370 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_CK_DRV_OP_EN);
371
372 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D0_EN);
373 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D1_EN);
374 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN);
375 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN);
376
377 mtk_hdmi_pll_drv_setting(hw);
378
379 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD);
380 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN);
381 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN);
382 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN);
383
384 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON);
385 usleep_range(5, 10);
386 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN);
387 usleep_range(5, 10);
388 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);
389 usleep_range(30, 50);
390 return 0;
391 }
392
mtk_hdmi_pll_unprepare(struct clk_hw * hw)393 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
394 {
395 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
396 void __iomem *regs = hdmi_phy->regs;
397
398 mtk_phy_set_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD);
399 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN);
400 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN);
401 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN);
402
403 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);
404 usleep_range(10, 20);
405 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN);
406 usleep_range(10, 20);
407 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON);
408 }
409
mtk_hdmi_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)410 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
411 unsigned long parent_rate)
412 {
413 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
414
415 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate,
416 parent_rate);
417
418 return mtk_hdmi_pll_calc(hdmi_phy, hw, rate, parent_rate);
419 }
420
mtk_hdmi_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)421 static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
422 unsigned long *parent_rate)
423 {
424 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
425
426 hdmi_phy->pll_rate = rate;
427 return rate;
428 }
429
mtk_hdmi_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)430 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
431 unsigned long parent_rate)
432 {
433 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
434
435 return hdmi_phy->pll_rate;
436 }
437
438 static const struct clk_ops mtk_hdmi_pll_ops = {
439 .prepare = mtk_hdmi_pll_prepare,
440 .unprepare = mtk_hdmi_pll_unprepare,
441 .set_rate = mtk_hdmi_pll_set_rate,
442 .round_rate = mtk_hdmi_pll_round_rate,
443 .recalc_rate = mtk_hdmi_pll_recalc_rate,
444 };
445
vtx_signal_en(struct mtk_hdmi_phy * hdmi_phy,bool on)446 static void vtx_signal_en(struct mtk_hdmi_phy *hdmi_phy, bool on)
447 {
448 void __iomem *regs = hdmi_phy->regs;
449
450 if (on)
451 mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN);
452 else
453 mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN);
454 }
455
mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy * hdmi_phy)456 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
457 {
458 vtx_signal_en(hdmi_phy, true);
459 usleep_range(100, 150);
460 }
461
mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy * hdmi_phy)462 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
463 {
464 vtx_signal_en(hdmi_phy, false);
465 }
466
mtk_hdmi_phy_configure(struct phy * phy,union phy_configure_opts * opts)467 static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts)
468 {
469 struct phy_configure_opts_dp *dp_opts = &opts->dp;
470 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
471 int ret;
472
473 ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate);
474
475 if (ret)
476 return ret;
477
478 mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M);
479
480 return ret;
481 }
482
mtk_hdmi_phy_pwr5v_enable(struct regulator_dev * rdev)483 static int mtk_hdmi_phy_pwr5v_enable(struct regulator_dev *rdev)
484 {
485 struct mtk_hdmi_phy *hdmi_phy = rdev_get_drvdata(rdev);
486
487 mtk_phy_set_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O);
488
489 return 0;
490 }
491
mtk_hdmi_phy_pwr5v_disable(struct regulator_dev * rdev)492 static int mtk_hdmi_phy_pwr5v_disable(struct regulator_dev *rdev)
493 {
494 struct mtk_hdmi_phy *hdmi_phy = rdev_get_drvdata(rdev);
495
496 mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O);
497
498 return 0;
499 }
500
mtk_hdmi_phy_pwr5v_is_enabled(struct regulator_dev * rdev)501 static int mtk_hdmi_phy_pwr5v_is_enabled(struct regulator_dev *rdev)
502 {
503 struct mtk_hdmi_phy *hdmi_phy = rdev_get_drvdata(rdev);
504
505 return !!(readl(hdmi_phy->regs + HDMI_CTL_1) & RG_HDMITX_PWR5V_O);
506 }
507
508 static const struct regulator_ops mtk_hdmi_pwr5v_regulator_ops = {
509 .enable = mtk_hdmi_phy_pwr5v_enable,
510 .disable = mtk_hdmi_phy_pwr5v_disable,
511 .is_enabled = mtk_hdmi_phy_pwr5v_is_enabled
512 };
513
514 static const struct regulator_desc mtk_hdmi_phy_pwr5v_desc = {
515 .name = "hdmi-pwr5v",
516 .id = -1,
517 .n_voltages = 1,
518 .fixed_uV = 5000000,
519 .ops = &mtk_hdmi_pwr5v_regulator_ops,
520 .type = REGULATOR_VOLTAGE,
521 .owner = THIS_MODULE,
522 };
523
524 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf = {
525 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
526 .hdmi_phy_regulator_desc = &mtk_hdmi_phy_pwr5v_desc,
527 .hdmi_phy_clk_ops = &mtk_hdmi_pll_ops,
528 .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
529 .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
530 .hdmi_phy_configure = mtk_hdmi_phy_configure,
531 };
532
533 MODULE_AUTHOR("Can Zeng <[email protected]>");
534 MODULE_DESCRIPTION("MediaTek MT8195 HDMI PHY Driver");
535 MODULE_LICENSE("GPL v2");
536