1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Rockchip SoCs.
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 * http://www.rock-chips.com
7 *
8 * Author: Simon Xue <[email protected]>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #include "pcie-designware.h"
25
26 /*
27 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write
28 * mask for the lower 16 bits.
29 */
30 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
31 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
33
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
35
36 #define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
37 #define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
38 #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
39 #define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
40 #define PCIE_CLIENT_INTR_STATUS_MISC 0x10
41 #define PCIE_CLIENT_INTR_MASK_MISC 0x24
42 #define PCIE_SMLH_LINKUP BIT(16)
43 #define PCIE_RDLH_LINKUP BIT(17)
44 #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
45 #define PCIE_RDLH_LINK_UP_CHGED BIT(1)
46 #define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
47 #define PCIE_L0S_ENTRY 0x11
48 #define PCIE_CLIENT_GENERAL_CONTROL 0x0
49 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
50 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
51 #define PCIE_CLIENT_GENERAL_DEBUG 0x104
52 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
53 #define PCIE_CLIENT_LTSSM_STATUS 0x300
54 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
55 #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
56
57 struct rockchip_pcie {
58 struct dw_pcie pci;
59 void __iomem *apb_base;
60 struct phy *phy;
61 struct clk_bulk_data *clks;
62 unsigned int clk_cnt;
63 struct reset_control *rst;
64 struct gpio_desc *rst_gpio;
65 struct regulator *vpcie3v3;
66 struct irq_domain *irq_domain;
67 const struct rockchip_pcie_of_data *data;
68 };
69
70 struct rockchip_pcie_of_data {
71 enum dw_pcie_device_mode mode;
72 const struct pci_epc_features *epc_features;
73 };
74
rockchip_pcie_readl_apb(struct rockchip_pcie * rockchip,u32 reg)75 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
76 {
77 return readl_relaxed(rockchip->apb_base + reg);
78 }
79
rockchip_pcie_writel_apb(struct rockchip_pcie * rockchip,u32 val,u32 reg)80 static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val,
81 u32 reg)
82 {
83 writel_relaxed(val, rockchip->apb_base + reg);
84 }
85
rockchip_pcie_intx_handler(struct irq_desc * desc)86 static void rockchip_pcie_intx_handler(struct irq_desc *desc)
87 {
88 struct irq_chip *chip = irq_desc_get_chip(desc);
89 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
90 unsigned long reg, hwirq;
91
92 chained_irq_enter(chip, desc);
93
94 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
95
96 for_each_set_bit(hwirq, ®, 4)
97 generic_handle_domain_irq(rockchip->irq_domain, hwirq);
98
99 chained_irq_exit(chip, desc);
100 }
101
rockchip_intx_mask(struct irq_data * data)102 static void rockchip_intx_mask(struct irq_data *data)
103 {
104 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
105 HIWORD_UPDATE_BIT(BIT(data->hwirq)),
106 PCIE_CLIENT_INTR_MASK_LEGACY);
107 };
108
rockchip_intx_unmask(struct irq_data * data)109 static void rockchip_intx_unmask(struct irq_data *data)
110 {
111 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
112 HIWORD_DISABLE_BIT(BIT(data->hwirq)),
113 PCIE_CLIENT_INTR_MASK_LEGACY);
114 };
115
116 static struct irq_chip rockchip_intx_irq_chip = {
117 .name = "INTx",
118 .irq_mask = rockchip_intx_mask,
119 .irq_unmask = rockchip_intx_unmask,
120 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
121 };
122
rockchip_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)123 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
124 irq_hw_number_t hwirq)
125 {
126 irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
127 irq_set_chip_data(irq, domain->host_data);
128
129 return 0;
130 }
131
132 static const struct irq_domain_ops intx_domain_ops = {
133 .map = rockchip_pcie_intx_map,
134 };
135
rockchip_pcie_init_irq_domain(struct rockchip_pcie * rockchip)136 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
137 {
138 struct device *dev = rockchip->pci.dev;
139 struct device_node *intc;
140
141 intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
142 if (!intc) {
143 dev_err(dev, "missing child interrupt-controller node\n");
144 return -EINVAL;
145 }
146
147 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
148 &intx_domain_ops, rockchip);
149 of_node_put(intc);
150 if (!rockchip->irq_domain) {
151 dev_err(dev, "failed to get a INTx IRQ domain\n");
152 return -EINVAL;
153 }
154
155 return 0;
156 }
157
rockchip_pcie_get_ltssm(struct rockchip_pcie * rockchip)158 static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)
159 {
160 return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
161 }
162
rockchip_pcie_enable_ltssm(struct rockchip_pcie * rockchip)163 static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
164 {
165 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
166 PCIE_CLIENT_GENERAL_CONTROL);
167 }
168
rockchip_pcie_disable_ltssm(struct rockchip_pcie * rockchip)169 static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
170 {
171 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
172 PCIE_CLIENT_GENERAL_CONTROL);
173 }
174
rockchip_pcie_link_up(struct dw_pcie * pci)175 static int rockchip_pcie_link_up(struct dw_pcie *pci)
176 {
177 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
178 u32 val = rockchip_pcie_get_ltssm(rockchip);
179
180 if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
181 (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
182 return 1;
183
184 return 0;
185 }
186
rockchip_pcie_start_link(struct dw_pcie * pci)187 static int rockchip_pcie_start_link(struct dw_pcie *pci)
188 {
189 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
190
191 /* Reset device */
192 gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
193
194 rockchip_pcie_enable_ltssm(rockchip);
195
196 /*
197 * PCIe requires the refclk to be stable for 100µs prior to releasing
198 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
199 * Express Card Electromechanical Specification, 1.1. However, we don't
200 * know if the refclk is coming from RC's PHY or external OSC. If it's
201 * from RC, so enabling LTSSM is the just right place to release #PERST.
202 * We need more extra time as before, rather than setting just
203 * 100us as we don't know how long should the device need to reset.
204 */
205 msleep(100);
206 gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
207
208 return 0;
209 }
210
rockchip_pcie_stop_link(struct dw_pcie * pci)211 static void rockchip_pcie_stop_link(struct dw_pcie *pci)
212 {
213 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
214
215 rockchip_pcie_disable_ltssm(rockchip);
216 }
217
rockchip_pcie_host_init(struct dw_pcie_rp * pp)218 static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
219 {
220 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
221 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
222 struct device *dev = rockchip->pci.dev;
223 int irq, ret;
224
225 irq = of_irq_get_byname(dev->of_node, "legacy");
226 if (irq < 0)
227 return irq;
228
229 ret = rockchip_pcie_init_irq_domain(rockchip);
230 if (ret < 0)
231 dev_err(dev, "failed to init irq domain\n");
232
233 irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
234 rockchip);
235
236 return 0;
237 }
238
239 static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
240 .init = rockchip_pcie_host_init,
241 };
242
rockchip_pcie_ep_init(struct dw_pcie_ep * ep)243 static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
244 {
245 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
246 enum pci_barno bar;
247
248 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
249 dw_pcie_ep_reset_bar(pci, bar);
250 };
251
rockchip_pcie_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)252 static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
253 unsigned int type, u16 interrupt_num)
254 {
255 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
256
257 switch (type) {
258 case PCI_IRQ_INTX:
259 return dw_pcie_ep_raise_intx_irq(ep, func_no);
260 case PCI_IRQ_MSI:
261 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
262 case PCI_IRQ_MSIX:
263 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
264 default:
265 dev_err(pci->dev, "UNKNOWN IRQ type\n");
266 }
267
268 return 0;
269 }
270
271 static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
272 .linkup_notifier = true,
273 .msi_capable = true,
274 .msix_capable = true,
275 .align = SZ_64K,
276 .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
277 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
278 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
279 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
280 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
281 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
282 };
283
284 /*
285 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
286 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
287 * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by
288 * default.) If the host could write to BAR4, the iATU settings (for all other
289 * BARs) would be overwritten, resulting in (all other BARs) no longer working.
290 */
291 static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
292 .linkup_notifier = true,
293 .msi_capable = true,
294 .msix_capable = true,
295 .align = SZ_64K,
296 .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
297 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
298 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
299 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
300 .bar[BAR_4] = { .type = BAR_RESERVED, },
301 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
302 };
303
304 static const struct pci_epc_features *
rockchip_pcie_get_features(struct dw_pcie_ep * ep)305 rockchip_pcie_get_features(struct dw_pcie_ep *ep)
306 {
307 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
308 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
309
310 return rockchip->data->epc_features;
311 }
312
313 static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {
314 .init = rockchip_pcie_ep_init,
315 .raise_irq = rockchip_pcie_raise_irq,
316 .get_features = rockchip_pcie_get_features,
317 };
318
rockchip_pcie_clk_init(struct rockchip_pcie * rockchip)319 static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)
320 {
321 struct device *dev = rockchip->pci.dev;
322 int ret;
323
324 ret = devm_clk_bulk_get_all(dev, &rockchip->clks);
325 if (ret < 0)
326 return dev_err_probe(dev, ret, "failed to get clocks\n");
327
328 rockchip->clk_cnt = ret;
329
330 ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);
331 if (ret)
332 return dev_err_probe(dev, ret, "failed to enable clocks\n");
333
334 return 0;
335 }
336
rockchip_pcie_resource_get(struct platform_device * pdev,struct rockchip_pcie * rockchip)337 static int rockchip_pcie_resource_get(struct platform_device *pdev,
338 struct rockchip_pcie *rockchip)
339 {
340 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
341 if (IS_ERR(rockchip->apb_base))
342 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base),
343 "failed to map apb registers\n");
344
345 rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
346 GPIOD_OUT_LOW);
347 if (IS_ERR(rockchip->rst_gpio))
348 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst_gpio),
349 "failed to get reset gpio\n");
350
351 rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
352 if (IS_ERR(rockchip->rst))
353 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
354 "failed to get reset lines\n");
355
356 return 0;
357 }
358
rockchip_pcie_phy_init(struct rockchip_pcie * rockchip)359 static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
360 {
361 struct device *dev = rockchip->pci.dev;
362 int ret;
363
364 rockchip->phy = devm_phy_get(dev, "pcie-phy");
365 if (IS_ERR(rockchip->phy))
366 return dev_err_probe(dev, PTR_ERR(rockchip->phy),
367 "missing PHY\n");
368
369 ret = phy_init(rockchip->phy);
370 if (ret < 0)
371 return ret;
372
373 ret = phy_power_on(rockchip->phy);
374 if (ret)
375 phy_exit(rockchip->phy);
376
377 return ret;
378 }
379
rockchip_pcie_phy_deinit(struct rockchip_pcie * rockchip)380 static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
381 {
382 phy_exit(rockchip->phy);
383 phy_power_off(rockchip->phy);
384 }
385
386 static const struct dw_pcie_ops dw_pcie_ops = {
387 .link_up = rockchip_pcie_link_up,
388 .start_link = rockchip_pcie_start_link,
389 .stop_link = rockchip_pcie_stop_link,
390 };
391
rockchip_pcie_rc_sys_irq_thread(int irq,void * arg)392 static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
393 {
394 struct rockchip_pcie *rockchip = arg;
395 struct dw_pcie *pci = &rockchip->pci;
396 struct dw_pcie_rp *pp = &pci->pp;
397 struct device *dev = pci->dev;
398 u32 reg, val;
399
400 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
401 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
402
403 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
404 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
405
406 if (reg & PCIE_RDLH_LINK_UP_CHGED) {
407 val = rockchip_pcie_get_ltssm(rockchip);
408 if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
409 dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
410 /* Rescan the bus to enumerate endpoint devices */
411 pci_lock_rescan_remove();
412 pci_rescan_bus(pp->bridge->bus);
413 pci_unlock_rescan_remove();
414 }
415 }
416
417 return IRQ_HANDLED;
418 }
419
rockchip_pcie_ep_sys_irq_thread(int irq,void * arg)420 static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
421 {
422 struct rockchip_pcie *rockchip = arg;
423 struct dw_pcie *pci = &rockchip->pci;
424 struct device *dev = pci->dev;
425 u32 reg, val;
426
427 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
428 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
429
430 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
431 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
432
433 if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
434 dev_dbg(dev, "hot reset or link-down reset\n");
435 dw_pcie_ep_linkdown(&pci->ep);
436 }
437
438 if (reg & PCIE_RDLH_LINK_UP_CHGED) {
439 val = rockchip_pcie_get_ltssm(rockchip);
440 if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
441 dev_dbg(dev, "link up\n");
442 dw_pcie_ep_linkup(&pci->ep);
443 }
444 }
445
446 return IRQ_HANDLED;
447 }
448
rockchip_pcie_configure_rc(struct platform_device * pdev,struct rockchip_pcie * rockchip)449 static int rockchip_pcie_configure_rc(struct platform_device *pdev,
450 struct rockchip_pcie *rockchip)
451 {
452 struct device *dev = &pdev->dev;
453 struct dw_pcie_rp *pp;
454 int irq, ret;
455 u32 val;
456
457 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))
458 return -ENODEV;
459
460 irq = platform_get_irq_byname(pdev, "sys");
461 if (irq < 0)
462 return irq;
463
464 ret = devm_request_threaded_irq(dev, irq, NULL,
465 rockchip_pcie_rc_sys_irq_thread,
466 IRQF_ONESHOT, "pcie-sys-rc", rockchip);
467 if (ret) {
468 dev_err(dev, "failed to request PCIe sys IRQ\n");
469 return ret;
470 }
471
472 /* LTSSM enable control mode */
473 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
474 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
475
476 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
477 PCIE_CLIENT_GENERAL_CONTROL);
478
479 pp = &rockchip->pci.pp;
480 pp->ops = &rockchip_pcie_host_ops;
481 pp->use_linkup_irq = true;
482
483 ret = dw_pcie_host_init(pp);
484 if (ret) {
485 dev_err(dev, "failed to initialize host\n");
486 return ret;
487 }
488
489 /* unmask DLL up/down indicator */
490 val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED, 0);
491 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
492
493 return ret;
494 }
495
rockchip_pcie_configure_ep(struct platform_device * pdev,struct rockchip_pcie * rockchip)496 static int rockchip_pcie_configure_ep(struct platform_device *pdev,
497 struct rockchip_pcie *rockchip)
498 {
499 struct device *dev = &pdev->dev;
500 int irq, ret;
501 u32 val;
502
503 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))
504 return -ENODEV;
505
506 irq = platform_get_irq_byname(pdev, "sys");
507 if (irq < 0)
508 return irq;
509
510 ret = devm_request_threaded_irq(dev, irq, NULL,
511 rockchip_pcie_ep_sys_irq_thread,
512 IRQF_ONESHOT, "pcie-sys-ep", rockchip);
513 if (ret) {
514 dev_err(dev, "failed to request PCIe sys IRQ\n");
515 return ret;
516 }
517
518 /* LTSSM enable control mode */
519 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
520 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
521
522 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
523 PCIE_CLIENT_GENERAL_CONTROL);
524
525 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
526 rockchip->pci.ep.page_size = SZ_64K;
527
528 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
529
530 ret = dw_pcie_ep_init(&rockchip->pci.ep);
531 if (ret) {
532 dev_err(dev, "failed to initialize endpoint\n");
533 return ret;
534 }
535
536 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);
537 if (ret) {
538 dev_err(dev, "failed to initialize DWC endpoint registers\n");
539 dw_pcie_ep_deinit(&rockchip->pci.ep);
540 return ret;
541 }
542
543 pci_epc_init_notify(rockchip->pci.ep.epc);
544
545 /* unmask DLL up/down indicator and hot reset/link-down reset */
546 val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED | PCIE_LINK_REQ_RST_NOT_INT, 0);
547 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
548
549 return ret;
550 }
551
rockchip_pcie_probe(struct platform_device * pdev)552 static int rockchip_pcie_probe(struct platform_device *pdev)
553 {
554 struct device *dev = &pdev->dev;
555 struct rockchip_pcie *rockchip;
556 const struct rockchip_pcie_of_data *data;
557 int ret;
558
559 data = of_device_get_match_data(dev);
560 if (!data)
561 return -EINVAL;
562
563 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
564 if (!rockchip)
565 return -ENOMEM;
566
567 platform_set_drvdata(pdev, rockchip);
568
569 rockchip->pci.dev = dev;
570 rockchip->pci.ops = &dw_pcie_ops;
571 rockchip->data = data;
572
573 ret = rockchip_pcie_resource_get(pdev, rockchip);
574 if (ret)
575 return ret;
576
577 ret = reset_control_assert(rockchip->rst);
578 if (ret)
579 return ret;
580
581 /* DON'T MOVE ME: must be enable before PHY init */
582 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
583 if (IS_ERR(rockchip->vpcie3v3)) {
584 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
585 return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),
586 "failed to get vpcie3v3 regulator\n");
587 rockchip->vpcie3v3 = NULL;
588 } else {
589 ret = regulator_enable(rockchip->vpcie3v3);
590 if (ret)
591 return dev_err_probe(dev, ret,
592 "failed to enable vpcie3v3 regulator\n");
593 }
594
595 ret = rockchip_pcie_phy_init(rockchip);
596 if (ret)
597 goto disable_regulator;
598
599 ret = reset_control_deassert(rockchip->rst);
600 if (ret)
601 goto deinit_phy;
602
603 ret = rockchip_pcie_clk_init(rockchip);
604 if (ret)
605 goto deinit_phy;
606
607 switch (data->mode) {
608 case DW_PCIE_RC_TYPE:
609 ret = rockchip_pcie_configure_rc(pdev, rockchip);
610 if (ret)
611 goto deinit_clk;
612 break;
613 case DW_PCIE_EP_TYPE:
614 ret = rockchip_pcie_configure_ep(pdev, rockchip);
615 if (ret)
616 goto deinit_clk;
617 break;
618 default:
619 dev_err(dev, "INVALID device type %d\n", data->mode);
620 ret = -EINVAL;
621 goto deinit_clk;
622 }
623
624 return 0;
625
626 deinit_clk:
627 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
628 deinit_phy:
629 rockchip_pcie_phy_deinit(rockchip);
630 disable_regulator:
631 if (rockchip->vpcie3v3)
632 regulator_disable(rockchip->vpcie3v3);
633
634 return ret;
635 }
636
637 static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
638 .mode = DW_PCIE_RC_TYPE,
639 };
640
641 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = {
642 .mode = DW_PCIE_EP_TYPE,
643 .epc_features = &rockchip_pcie_epc_features_rk3568,
644 };
645
646 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = {
647 .mode = DW_PCIE_EP_TYPE,
648 .epc_features = &rockchip_pcie_epc_features_rk3588,
649 };
650
651 static const struct of_device_id rockchip_pcie_of_match[] = {
652 {
653 .compatible = "rockchip,rk3568-pcie",
654 .data = &rockchip_pcie_rc_of_data_rk3568,
655 },
656 {
657 .compatible = "rockchip,rk3568-pcie-ep",
658 .data = &rockchip_pcie_ep_of_data_rk3568,
659 },
660 {
661 .compatible = "rockchip,rk3588-pcie-ep",
662 .data = &rockchip_pcie_ep_of_data_rk3588,
663 },
664 {},
665 };
666
667 static struct platform_driver rockchip_pcie_driver = {
668 .driver = {
669 .name = "rockchip-dw-pcie",
670 .of_match_table = rockchip_pcie_of_match,
671 .suppress_bind_attrs = true,
672 },
673 .probe = rockchip_pcie_probe,
674 };
675 builtin_platform_driver(rockchip_pcie_driver);
676