1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4 #include <linux/ip.h>
5 #include <linux/udp.h>
6
7 #include "cam.h"
8 #include "chan.h"
9 #include "coex.h"
10 #include "core.h"
11 #include "efuse.h"
12 #include "fw.h"
13 #include "mac.h"
14 #include "phy.h"
15 #include "ps.h"
16 #include "reg.h"
17 #include "sar.h"
18 #include "ser.h"
19 #include "txrx.h"
20 #include "util.h"
21 #include "wow.h"
22
23 static bool rtw89_disable_ps_mode;
24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
26
27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
37
38 static struct ieee80211_channel rtw89_channels_2ghz[] = {
39 RTW89_DEF_CHAN_2G(2412, 1),
40 RTW89_DEF_CHAN_2G(2417, 2),
41 RTW89_DEF_CHAN_2G(2422, 3),
42 RTW89_DEF_CHAN_2G(2427, 4),
43 RTW89_DEF_CHAN_2G(2432, 5),
44 RTW89_DEF_CHAN_2G(2437, 6),
45 RTW89_DEF_CHAN_2G(2442, 7),
46 RTW89_DEF_CHAN_2G(2447, 8),
47 RTW89_DEF_CHAN_2G(2452, 9),
48 RTW89_DEF_CHAN_2G(2457, 10),
49 RTW89_DEF_CHAN_2G(2462, 11),
50 RTW89_DEF_CHAN_2G(2467, 12),
51 RTW89_DEF_CHAN_2G(2472, 13),
52 RTW89_DEF_CHAN_2G(2484, 14),
53 };
54
55 static struct ieee80211_channel rtw89_channels_5ghz[] = {
56 RTW89_DEF_CHAN_5G(5180, 36),
57 RTW89_DEF_CHAN_5G(5200, 40),
58 RTW89_DEF_CHAN_5G(5220, 44),
59 RTW89_DEF_CHAN_5G(5240, 48),
60 RTW89_DEF_CHAN_5G(5260, 52),
61 RTW89_DEF_CHAN_5G(5280, 56),
62 RTW89_DEF_CHAN_5G(5300, 60),
63 RTW89_DEF_CHAN_5G(5320, 64),
64 RTW89_DEF_CHAN_5G(5500, 100),
65 RTW89_DEF_CHAN_5G(5520, 104),
66 RTW89_DEF_CHAN_5G(5540, 108),
67 RTW89_DEF_CHAN_5G(5560, 112),
68 RTW89_DEF_CHAN_5G(5580, 116),
69 RTW89_DEF_CHAN_5G(5600, 120),
70 RTW89_DEF_CHAN_5G(5620, 124),
71 RTW89_DEF_CHAN_5G(5640, 128),
72 RTW89_DEF_CHAN_5G(5660, 132),
73 RTW89_DEF_CHAN_5G(5680, 136),
74 RTW89_DEF_CHAN_5G(5700, 140),
75 RTW89_DEF_CHAN_5G(5720, 144),
76 RTW89_DEF_CHAN_5G(5745, 149),
77 RTW89_DEF_CHAN_5G(5765, 153),
78 RTW89_DEF_CHAN_5G(5785, 157),
79 RTW89_DEF_CHAN_5G(5805, 161),
80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
81 RTW89_DEF_CHAN_5G(5845, 169),
82 RTW89_DEF_CHAN_5G(5865, 173),
83 RTW89_DEF_CHAN_5G(5885, 177),
84 };
85
86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
87 ARRAY_SIZE(rtw89_channels_5ghz));
88
89 static struct ieee80211_channel rtw89_channels_6ghz[] = {
90 RTW89_DEF_CHAN_6G(5955, 1),
91 RTW89_DEF_CHAN_6G(5975, 5),
92 RTW89_DEF_CHAN_6G(5995, 9),
93 RTW89_DEF_CHAN_6G(6015, 13),
94 RTW89_DEF_CHAN_6G(6035, 17),
95 RTW89_DEF_CHAN_6G(6055, 21),
96 RTW89_DEF_CHAN_6G(6075, 25),
97 RTW89_DEF_CHAN_6G(6095, 29),
98 RTW89_DEF_CHAN_6G(6115, 33),
99 RTW89_DEF_CHAN_6G(6135, 37),
100 RTW89_DEF_CHAN_6G(6155, 41),
101 RTW89_DEF_CHAN_6G(6175, 45),
102 RTW89_DEF_CHAN_6G(6195, 49),
103 RTW89_DEF_CHAN_6G(6215, 53),
104 RTW89_DEF_CHAN_6G(6235, 57),
105 RTW89_DEF_CHAN_6G(6255, 61),
106 RTW89_DEF_CHAN_6G(6275, 65),
107 RTW89_DEF_CHAN_6G(6295, 69),
108 RTW89_DEF_CHAN_6G(6315, 73),
109 RTW89_DEF_CHAN_6G(6335, 77),
110 RTW89_DEF_CHAN_6G(6355, 81),
111 RTW89_DEF_CHAN_6G(6375, 85),
112 RTW89_DEF_CHAN_6G(6395, 89),
113 RTW89_DEF_CHAN_6G(6415, 93),
114 RTW89_DEF_CHAN_6G(6435, 97),
115 RTW89_DEF_CHAN_6G(6455, 101),
116 RTW89_DEF_CHAN_6G(6475, 105),
117 RTW89_DEF_CHAN_6G(6495, 109),
118 RTW89_DEF_CHAN_6G(6515, 113),
119 RTW89_DEF_CHAN_6G(6535, 117),
120 RTW89_DEF_CHAN_6G(6555, 121),
121 RTW89_DEF_CHAN_6G(6575, 125),
122 RTW89_DEF_CHAN_6G(6595, 129),
123 RTW89_DEF_CHAN_6G(6615, 133),
124 RTW89_DEF_CHAN_6G(6635, 137),
125 RTW89_DEF_CHAN_6G(6655, 141),
126 RTW89_DEF_CHAN_6G(6675, 145),
127 RTW89_DEF_CHAN_6G(6695, 149),
128 RTW89_DEF_CHAN_6G(6715, 153),
129 RTW89_DEF_CHAN_6G(6735, 157),
130 RTW89_DEF_CHAN_6G(6755, 161),
131 RTW89_DEF_CHAN_6G(6775, 165),
132 RTW89_DEF_CHAN_6G(6795, 169),
133 RTW89_DEF_CHAN_6G(6815, 173),
134 RTW89_DEF_CHAN_6G(6835, 177),
135 RTW89_DEF_CHAN_6G(6855, 181),
136 RTW89_DEF_CHAN_6G(6875, 185),
137 RTW89_DEF_CHAN_6G(6895, 189),
138 RTW89_DEF_CHAN_6G(6915, 193),
139 RTW89_DEF_CHAN_6G(6935, 197),
140 RTW89_DEF_CHAN_6G(6955, 201),
141 RTW89_DEF_CHAN_6G(6975, 205),
142 RTW89_DEF_CHAN_6G(6995, 209),
143 RTW89_DEF_CHAN_6G(7015, 213),
144 RTW89_DEF_CHAN_6G(7035, 217),
145 RTW89_DEF_CHAN_6G(7055, 221),
146 RTW89_DEF_CHAN_6G(7075, 225),
147 RTW89_DEF_CHAN_6G(7095, 229),
148 RTW89_DEF_CHAN_6G(7115, 233),
149 };
150
151 static struct ieee80211_rate rtw89_bitrates[] = {
152 { .bitrate = 10, .hw_value = 0x00, },
153 { .bitrate = 20, .hw_value = 0x01, },
154 { .bitrate = 55, .hw_value = 0x02, },
155 { .bitrate = 110, .hw_value = 0x03, },
156 { .bitrate = 60, .hw_value = 0x04, },
157 { .bitrate = 90, .hw_value = 0x05, },
158 { .bitrate = 120, .hw_value = 0x06, },
159 { .bitrate = 180, .hw_value = 0x07, },
160 { .bitrate = 240, .hw_value = 0x08, },
161 { .bitrate = 360, .hw_value = 0x09, },
162 { .bitrate = 480, .hw_value = 0x0a, },
163 { .bitrate = 540, .hw_value = 0x0b, },
164 };
165
166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
167 {
168 .max = 1,
169 .types = BIT(NL80211_IFTYPE_STATION),
170 },
171 {
172 .max = 1,
173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
174 BIT(NL80211_IFTYPE_P2P_GO) |
175 BIT(NL80211_IFTYPE_AP),
176 },
177 };
178
179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
180 {
181 .max = 1,
182 .types = BIT(NL80211_IFTYPE_STATION),
183 },
184 {
185 .max = 1,
186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
187 BIT(NL80211_IFTYPE_P2P_GO),
188 },
189 };
190
191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
192 {
193 .limits = rtw89_iface_limits,
194 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
195 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
196 .num_different_channels = 1,
197 },
198 {
199 .limits = rtw89_iface_limits_mcc,
200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
201 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
202 .num_different_channels = 2,
203 },
204 };
205
206 #define RTW89_6GHZ_SPAN_HEAD 6145
207 #define RTW89_6GHZ_SPAN_IDX(center_freq) \
208 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2)
209
210 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \
211 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \
212 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \
213 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \
214 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \
215 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \
216 }
217
218 /* Since 6GHz subbands are not edge aligned, some cases span two subbands.
219 * In the following, we describe each of them with rtw89_6ghz_span.
220 */
221 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = {
222 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H),
223 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H),
224 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H),
225 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L),
226 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L),
227 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L),
228 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H),
229 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H),
230 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8),
231 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8),
232 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8),
233 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8),
234 };
235
236 const struct rtw89_6ghz_span *
rtw89_get_6ghz_span(struct rtw89_dev * rtwdev,u32 center_freq)237 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq)
238 {
239 int idx;
240
241 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) {
242 idx = RTW89_6GHZ_SPAN_IDX(center_freq);
243 /* To decrease size of rtw89_overlapping_6ghz[],
244 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs
245 * to make first span as index 0 of the table. So, if center
246 * frequency is less than the first one, it will get netative.
247 */
248 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz))
249 return &rtw89_overlapping_6ghz[idx];
250 }
251
252 return NULL;
253 }
254
rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)255 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate)
256 {
257 struct ieee80211_rate rate;
258
259 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) {
260 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate);
261 return false;
262 }
263
264 rate = rtw89_bitrates[rpt_rate];
265 *bitrate = rate.bitrate;
266
267 return true;
268 }
269
270 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
271 .band = NL80211_BAND_2GHZ,
272 .channels = rtw89_channels_2ghz,
273 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
274 .bitrates = rtw89_bitrates,
275 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
276 .ht_cap = {0},
277 .vht_cap = {0},
278 };
279
280 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
281 .band = NL80211_BAND_5GHZ,
282 .channels = rtw89_channels_5ghz,
283 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
284
285 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
286 .bitrates = rtw89_bitrates + 4,
287 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
288 .ht_cap = {0},
289 .vht_cap = {0},
290 };
291
292 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
293 .band = NL80211_BAND_6GHZ,
294 .channels = rtw89_channels_6ghz,
295 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
296
297 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
298 .bitrates = rtw89_bitrates + 4,
299 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
300 };
301
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)302 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
303 struct rtw89_traffic_stats *stats,
304 struct sk_buff *skb, bool tx)
305 {
306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
307
308 if (tx && ieee80211_is_assoc_req(hdr->frame_control))
309 rtw89_wow_parse_akm(rtwdev, skb);
310
311 if (!ieee80211_is_data(hdr->frame_control))
312 return;
313
314 if (is_broadcast_ether_addr(hdr->addr1) ||
315 is_multicast_ether_addr(hdr->addr1))
316 return;
317
318 if (tx) {
319 stats->tx_cnt++;
320 stats->tx_unicast += skb->len;
321 } else {
322 stats->rx_cnt++;
323 stats->rx_unicast += skb->len;
324 }
325 }
326
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)327 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
328 {
329 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
330 NL80211_CHAN_NO_HT);
331 }
332
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)333 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
334 struct rtw89_chan *chan)
335 {
336 struct ieee80211_channel *channel = chandef->chan;
337 enum nl80211_chan_width width = chandef->width;
338 u32 primary_freq, center_freq;
339 u8 center_chan;
340 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
341 u32 offset;
342 u8 band;
343
344 center_chan = channel->hw_value;
345 primary_freq = channel->center_freq;
346 center_freq = chandef->center_freq1;
347
348 switch (width) {
349 case NL80211_CHAN_WIDTH_20_NOHT:
350 case NL80211_CHAN_WIDTH_20:
351 bandwidth = RTW89_CHANNEL_WIDTH_20;
352 break;
353 case NL80211_CHAN_WIDTH_40:
354 bandwidth = RTW89_CHANNEL_WIDTH_40;
355 if (primary_freq > center_freq) {
356 center_chan -= 2;
357 } else {
358 center_chan += 2;
359 }
360 break;
361 case NL80211_CHAN_WIDTH_80:
362 case NL80211_CHAN_WIDTH_160:
363 bandwidth = nl_to_rtw89_bandwidth(width);
364 if (primary_freq > center_freq) {
365 offset = (primary_freq - center_freq - 10) / 20;
366 center_chan -= 2 + offset * 4;
367 } else {
368 offset = (center_freq - primary_freq - 10) / 20;
369 center_chan += 2 + offset * 4;
370 }
371 break;
372 default:
373 center_chan = 0;
374 break;
375 }
376
377 switch (channel->band) {
378 default:
379 case NL80211_BAND_2GHZ:
380 band = RTW89_BAND_2G;
381 break;
382 case NL80211_BAND_5GHZ:
383 band = RTW89_BAND_5G;
384 break;
385 case NL80211_BAND_6GHZ:
386 band = RTW89_BAND_6G;
387 break;
388 }
389
390 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
391 }
392
__rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)393 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev,
394 const struct rtw89_chan *chan,
395 enum rtw89_phy_idx phy_idx)
396 {
397 const struct rtw89_chip_info *chip = rtwdev->chip;
398 bool entity_active;
399
400 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
401 if (!entity_active)
402 return;
403
404 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
405 }
406
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)407 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
408 {
409 const struct rtw89_chan *chan;
410
411 chan = rtw89_mgnt_chan_get(rtwdev, 0);
412 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
413
414 if (!rtwdev->support_mlo)
415 return;
416
417 chan = rtw89_mgnt_chan_get(rtwdev, 1);
418 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
419 }
420
__rtw89_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)421 static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
422 const struct rtw89_chan *chan,
423 enum rtw89_mac_idx mac_idx,
424 enum rtw89_phy_idx phy_idx)
425 {
426 const struct rtw89_chip_info *chip = rtwdev->chip;
427 const struct rtw89_chan_rcd *chan_rcd;
428 struct rtw89_channel_help_params bak;
429 bool entity_active;
430
431 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
432
433 chan_rcd = rtw89_chan_rcd_get_by_chan(chan);
434
435 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
436
437 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
438
439 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
440
441 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
442
443 if (!entity_active || chan_rcd->band_changed) {
444 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
445 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan);
446 }
447
448 rtw89_set_entity_state(rtwdev, phy_idx, true);
449 }
450
rtw89_set_channel(struct rtw89_dev * rtwdev)451 int rtw89_set_channel(struct rtw89_dev *rtwdev)
452 {
453 const struct rtw89_chan *chan;
454 enum rtw89_entity_mode mode;
455
456 mode = rtw89_entity_recalc(rtwdev);
457 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) {
458 WARN(1, "Invalid ent mode: %d\n", mode);
459 return -EINVAL;
460 }
461
462 chan = rtw89_mgnt_chan_get(rtwdev, 0);
463 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
464
465 if (!rtwdev->support_mlo)
466 return 0;
467
468 chan = rtw89_mgnt_chan_get(rtwdev, 1);
469 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1);
470
471 return 0;
472 }
473
474 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)475 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
476 struct sk_buff *skb)
477 {
478 struct ieee80211_hdr *hdr = (void *)skb->data;
479 __le16 fc = hdr->frame_control;
480
481 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
482 return RTW89_CORE_TX_TYPE_MGMT;
483
484 return RTW89_CORE_TX_TYPE_DATA;
485 }
486
487 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)488 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
489 struct rtw89_core_tx_request *tx_req,
490 enum btc_pkt_type pkt_type)
491 {
492 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
493 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
494 struct ieee80211_link_sta *link_sta;
495 struct sk_buff *skb = tx_req->skb;
496 struct rtw89_sta *rtwsta;
497 u8 ampdu_num;
498 u8 tid;
499
500 if (pkt_type == PACKET_EAPOL) {
501 desc_info->bk = true;
502 return;
503 }
504
505 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
506 return;
507
508 if (!rtwsta_link) {
509 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
510 return;
511 }
512
513 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
514 rtwsta = rtwsta_link->rtwsta;
515
516 rcu_read_lock();
517
518 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
519 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
520 rtwsta->ampdu_params[tid].agg_num :
521 4 << link_sta->ht_cap.ampdu_factor) - 1);
522
523 desc_info->agg_en = true;
524 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density;
525 desc_info->ampdu_num = ampdu_num;
526
527 rcu_read_unlock();
528 }
529
530 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)531 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
532 struct rtw89_core_tx_request *tx_req)
533 {
534 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
535 const struct rtw89_chip_info *chip = rtwdev->chip;
536 const struct rtw89_sec_cam_entry *sec_cam;
537 struct ieee80211_tx_info *info;
538 struct ieee80211_key_conf *key;
539 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
540 struct sk_buff *skb = tx_req->skb;
541 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
542 u8 sec_cam_idx;
543 u64 pn64;
544
545 info = IEEE80211_SKB_CB(skb);
546 key = info->control.hw_key;
547 sec_cam_idx = key->hw_key_idx;
548 sec_cam = cam_info->sec_entries[sec_cam_idx];
549 if (!sec_cam) {
550 rtw89_warn(rtwdev, "sec cam entry is empty\n");
551 return;
552 }
553
554 switch (key->cipher) {
555 case WLAN_CIPHER_SUITE_WEP40:
556 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
557 break;
558 case WLAN_CIPHER_SUITE_WEP104:
559 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
560 break;
561 case WLAN_CIPHER_SUITE_TKIP:
562 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
563 break;
564 case WLAN_CIPHER_SUITE_CCMP:
565 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
566 break;
567 case WLAN_CIPHER_SUITE_CCMP_256:
568 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
569 break;
570 case WLAN_CIPHER_SUITE_GCMP:
571 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
572 break;
573 case WLAN_CIPHER_SUITE_GCMP_256:
574 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
575 break;
576 default:
577 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
578 return;
579 }
580
581 desc_info->sec_en = true;
582 desc_info->sec_keyid = key->keyidx;
583 desc_info->sec_type = sec_type;
584 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
585
586 if (!chip->hw_sec_hdr)
587 return;
588
589 pn64 = atomic64_inc_return(&key->tx_pn);
590 desc_info->sec_seq[0] = pn64;
591 desc_info->sec_seq[1] = pn64 >> 8;
592 desc_info->sec_seq[2] = pn64 >> 16;
593 desc_info->sec_seq[3] = pn64 >> 24;
594 desc_info->sec_seq[4] = pn64 >> 32;
595 desc_info->sec_seq[5] = pn64 >> 40;
596 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
597 }
598
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)599 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
600 struct rtw89_core_tx_request *tx_req,
601 const struct rtw89_chan *chan)
602 {
603 struct sk_buff *skb = tx_req->skb;
604 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
605 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
606 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
607 struct ieee80211_vif *vif = tx_info->control.vif;
608 struct ieee80211_bss_conf *bss_conf;
609 u16 lowest_rate;
610 u16 rate;
611
612 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
613 (vif && vif->p2p))
614 lowest_rate = RTW89_HW_RATE_OFDM6;
615 else if (chan->band_type == RTW89_BAND_2G)
616 lowest_rate = RTW89_HW_RATE_CCK1;
617 else
618 lowest_rate = RTW89_HW_RATE_OFDM6;
619
620 if (!rtwvif_link)
621 return lowest_rate;
622
623 rcu_read_lock();
624
625 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
626 if (!bss_conf->basic_rates || !rtwsta_link) {
627 rate = lowest_rate;
628 goto out;
629 }
630
631 rate = __ffs(bss_conf->basic_rates) + lowest_rate;
632
633 out:
634 rcu_read_unlock();
635
636 return rate;
637 }
638
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)639 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
640 struct rtw89_core_tx_request *tx_req)
641 {
642 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
643 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
644
645 if (!rtwsta_link)
646 return rtwvif_link->mac_id;
647
648 return rtwsta_link->mac_id;
649 }
650
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)651 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
652 struct rtw89_tx_desc_info *desc_info,
653 struct sk_buff *skb)
654 {
655 struct ieee80211_hdr *hdr = (void *)skb->data;
656 __le16 fc = hdr->frame_control;
657
658 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
659 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
660 }
661
662 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)663 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
664 struct rtw89_core_tx_request *tx_req)
665 {
666 const struct rtw89_chip_info *chip = rtwdev->chip;
667 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
668 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
669 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
670 rtwvif_link->chanctx_idx);
671 struct sk_buff *skb = tx_req->skb;
672 u8 qsel, ch_dma;
673
674 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
675 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
676
677 desc_info->qsel = qsel;
678 desc_info->ch_dma = ch_dma;
679 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
680 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
681 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
682 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
683
684 /* fixed data rate for mgmt frames */
685 desc_info->en_wd_info = true;
686 desc_info->use_rate = true;
687 desc_info->dis_data_fb = true;
688 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
689
690 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
691 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
692 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
693 }
694
695 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
696 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
697 desc_info->data_rate, chan->channel, chan->band_type,
698 chan->band_width);
699 }
700
701 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)702 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
703 struct rtw89_core_tx_request *tx_req)
704 {
705 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
706
707 desc_info->is_bmc = false;
708 desc_info->wd_page = false;
709 desc_info->ch_dma = RTW89_DMA_H2C;
710 }
711
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)712 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
713 const struct rtw89_chan *chan)
714 {
715 static const u8 rtw89_bandwidth_to_om[] = {
716 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
717 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
718 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
719 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
720 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
721 };
722 const struct rtw89_chip_info *chip = rtwdev->chip;
723 struct rtw89_hal *hal = &rtwdev->hal;
724 u8 om_bandwidth;
725
726 if (!chip->dis_2g_40m_ul_ofdma ||
727 chan->band_type != RTW89_BAND_2G ||
728 chan->band_width != RTW89_CHANNEL_WIDTH_40)
729 return;
730
731 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
732 rtw89_bandwidth_to_om[chan->band_width] : 0;
733 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
734 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
735 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
736 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
737 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
738 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
739 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
740 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
741 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
742 }
743
744 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)745 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
746 struct rtw89_core_tx_request *tx_req,
747 enum btc_pkt_type pkt_type)
748 {
749 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
750 struct sk_buff *skb = tx_req->skb;
751 struct ieee80211_hdr *hdr = (void *)skb->data;
752 struct ieee80211_link_sta *link_sta;
753 __le16 fc = hdr->frame_control;
754
755 /* AP IOT issue with EAPoL, ARP and DHCP */
756 if (pkt_type < PACKET_MAX)
757 return false;
758
759 if (!rtwsta_link)
760 return false;
761
762 rcu_read_lock();
763
764 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
765 if (!link_sta->he_cap.has_he) {
766 rcu_read_unlock();
767 return false;
768 }
769
770 rcu_read_unlock();
771
772 if (!ieee80211_is_data_qos(fc))
773 return false;
774
775 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
776 return false;
777
778 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
779 return false;
780
781 return true;
782 }
783
784 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)785 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
786 struct rtw89_core_tx_request *tx_req)
787 {
788 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
789 struct sk_buff *skb = tx_req->skb;
790 struct ieee80211_hdr *hdr = (void *)skb->data;
791 __le16 fc = hdr->frame_control;
792 void *data;
793 __le32 *htc;
794 u8 *qc;
795 int hdr_len;
796
797 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
798 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
799 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
800
801 hdr = data;
802 htc = data + hdr_len;
803 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
804 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template :
805 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
806 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
807
808 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
809 qc[0] |= IEEE80211_QOS_CTL_EOSP;
810 }
811
812 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)813 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
814 struct rtw89_core_tx_request *tx_req,
815 enum btc_pkt_type pkt_type)
816 {
817 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
818 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
819
820 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
821 goto desc_bk;
822
823 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
824
825 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
826 desc_info->a_ctrl_bsr = true;
827
828 desc_bk:
829 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr)
830 return;
831
832 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr;
833 desc_info->bk = true;
834 }
835
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)836 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
837 struct rtw89_core_tx_request *tx_req)
838 {
839 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
840 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
841 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
842 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
843 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx;
844 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
845 struct ieee80211_link_sta *link_sta;
846 u16 lowest_rate;
847 u16 rate;
848
849 if (rate_pattern->enable)
850 return rate_pattern->rate;
851
852 if (vif->p2p)
853 lowest_rate = RTW89_HW_RATE_OFDM6;
854 else if (chan->band_type == RTW89_BAND_2G)
855 lowest_rate = RTW89_HW_RATE_CCK1;
856 else
857 lowest_rate = RTW89_HW_RATE_OFDM6;
858
859 if (!rtwsta_link)
860 return lowest_rate;
861
862 rcu_read_lock();
863
864 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
865 if (!link_sta->supp_rates[chan->band_type]) {
866 rate = lowest_rate;
867 goto out;
868 }
869
870 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate;
871
872 out:
873 rcu_read_unlock();
874
875 return rate;
876 }
877
878 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)879 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
880 struct rtw89_core_tx_request *tx_req)
881 {
882 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
883 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
884 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
885 struct sk_buff *skb = tx_req->skb;
886 u8 tid, tid_indicate;
887 u8 qsel, ch_dma;
888
889 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
890 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
891 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
892 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
893
894 desc_info->ch_dma = ch_dma;
895 desc_info->tid_indicate = tid_indicate;
896 desc_info->qsel = qsel;
897 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
898 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
899 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
900 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false;
901 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false;
902
903 /* enable wd_info for AMPDU */
904 desc_info->en_wd_info = true;
905
906 if (IEEE80211_SKB_CB(skb)->control.hw_key)
907 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
908
909 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
910 }
911
912 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)913 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
914 struct rtw89_core_tx_request *tx_req)
915 {
916 struct sk_buff *skb = tx_req->skb;
917 struct udphdr *udphdr;
918
919 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
920 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work);
921 return PACKET_EAPOL;
922 }
923
924 if (skb->protocol == htons(ETH_P_ARP)) {
925 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work);
926 return PACKET_ARP;
927 }
928
929 if (skb->protocol == htons(ETH_P_IP) &&
930 ip_hdr(skb)->protocol == IPPROTO_UDP) {
931 udphdr = udp_hdr(skb);
932 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
933 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
934 skb->len > 282) {
935 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work);
936 return PACKET_DHCP;
937 }
938 }
939
940 if (skb->protocol == htons(ETH_P_IP) &&
941 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
942 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work);
943 return PACKET_ICMP;
944 }
945
946 return PACKET_MAX;
947 }
948
949 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)950 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
951 struct rtw89_core_tx_request *tx_req)
952 {
953 const struct rtw89_chip_info *chip = rtwdev->chip;
954
955 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
956 return;
957
958 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
959 return;
960
961 if (chip->chip_id != RTL8852C &&
962 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT)
963 return;
964
965 rtw89_mac_notify_wake(rtwdev);
966 }
967
968 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)969 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
970 struct rtw89_core_tx_request *tx_req)
971 {
972 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
973 struct sk_buff *skb = tx_req->skb;
974 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
975 struct ieee80211_hdr *hdr = (void *)skb->data;
976 struct rtw89_addr_cam_entry *addr_cam;
977 enum rtw89_core_tx_type tx_type;
978 enum btc_pkt_type pkt_type;
979 bool upd_wlan_hdr = false;
980 bool is_bmc;
981 u16 seq;
982
983 if (tx_req->sta)
984 desc_info->mlo = tx_req->sta->mlo;
985 else if (tx_req->vif)
986 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif);
987
988 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
989 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
990 tx_type = rtw89_core_get_tx_type(rtwdev, skb);
991 tx_req->tx_type = tx_type;
992
993 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
994 tx_req->rtwsta_link);
995 if (addr_cam->valid && desc_info->mlo)
996 upd_wlan_hdr = true;
997 }
998 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
999 is_multicast_ether_addr(hdr->addr1));
1000
1001 desc_info->seq = seq;
1002 desc_info->pkt_size = skb->len;
1003 desc_info->is_bmc = is_bmc;
1004 desc_info->wd_page = true;
1005 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
1006 desc_info->upd_wlan_hdr = upd_wlan_hdr;
1007
1008 switch (tx_req->tx_type) {
1009 case RTW89_CORE_TX_TYPE_MGMT:
1010 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
1011 break;
1012 case RTW89_CORE_TX_TYPE_DATA:
1013 rtw89_core_tx_update_data_info(rtwdev, tx_req);
1014 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
1015 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
1016 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
1017 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
1018 break;
1019 case RTW89_CORE_TX_TYPE_FWCMD:
1020 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
1021 break;
1022 }
1023 }
1024
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)1025 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
1026 {
1027 u8 ch_dma;
1028
1029 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
1030
1031 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
1032 }
1033
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,int qsel,unsigned int timeout)1034 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1035 int qsel, unsigned int timeout)
1036 {
1037 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1038 struct rtw89_tx_wait_info *wait;
1039 unsigned long time_left;
1040 int ret = 0;
1041
1042 wait = kzalloc(sizeof(*wait), GFP_KERNEL);
1043 if (!wait) {
1044 rtw89_core_tx_kick_off(rtwdev, qsel);
1045 return 0;
1046 }
1047
1048 init_completion(&wait->completion);
1049 rcu_assign_pointer(skb_data->wait, wait);
1050
1051 rtw89_core_tx_kick_off(rtwdev, qsel);
1052 time_left = wait_for_completion_timeout(&wait->completion,
1053 msecs_to_jiffies(timeout));
1054 if (time_left == 0)
1055 ret = -ETIMEDOUT;
1056 else if (!wait->tx_done)
1057 ret = -EAGAIN;
1058
1059 rcu_assign_pointer(skb_data->wait, NULL);
1060 kfree_rcu(wait, rcu_head);
1061
1062 return ret;
1063 }
1064
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1065 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1066 struct sk_buff *skb, bool fwdl)
1067 {
1068 struct rtw89_core_tx_request tx_req = {0};
1069 u32 cnt;
1070 int ret;
1071
1072 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1073 rtw89_debug(rtwdev, RTW89_DBG_FW,
1074 "ignore h2c due to power is off with firmware state=%d\n",
1075 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1076 dev_kfree_skb(skb);
1077 return 0;
1078 }
1079
1080 tx_req.skb = skb;
1081 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1082 if (fwdl)
1083 tx_req.desc_info.fw_dl = true;
1084
1085 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1086
1087 if (!fwdl)
1088 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1089
1090 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1091 if (cnt == 0) {
1092 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1093 return -ENOSPC;
1094 }
1095
1096 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1097 if (ret) {
1098 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1099 return ret;
1100 }
1101 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1102
1103 return 0;
1104 }
1105
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1106 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1107 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1108 {
1109 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1110 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1111 struct rtw89_core_tx_request tx_req = {0};
1112 struct rtw89_sta_link *rtwsta_link = NULL;
1113 struct rtw89_vif_link *rtwvif_link;
1114 int ret;
1115
1116 /* By default, driver writes tx via the link on HW-0. And then,
1117 * according to links' status, HW can change tx to another link.
1118 */
1119
1120 if (rtwsta) {
1121 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1122 if (unlikely(!rtwsta_link)) {
1123 rtw89_err(rtwdev, "tx: find no sta link on HW-0\n");
1124 return -ENOLINK;
1125 }
1126 }
1127
1128 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
1129 if (unlikely(!rtwvif_link)) {
1130 rtw89_err(rtwdev, "tx: find no vif link on HW-0\n");
1131 return -ENOLINK;
1132 }
1133
1134 tx_req.skb = skb;
1135 tx_req.vif = vif;
1136 tx_req.sta = sta;
1137 tx_req.rtwvif_link = rtwvif_link;
1138 tx_req.rtwsta_link = rtwsta_link;
1139
1140 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true);
1141 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true);
1142 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1143 rtw89_core_tx_wake(rtwdev, &tx_req);
1144
1145 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1146 if (ret) {
1147 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1148 return ret;
1149 }
1150
1151 if (qsel)
1152 *qsel = tx_req.desc_info.qsel;
1153
1154 return 0;
1155 }
1156
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1157 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1158 {
1159 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1160 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1161 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1162 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1163 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1164 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1165 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1166 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1167
1168 return cpu_to_le32(dword);
1169 }
1170
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1171 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1172 {
1173 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1174 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1175 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1176 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1177 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1178 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1179
1180 return cpu_to_le32(dword);
1181 }
1182
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1183 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1184 {
1185 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1186 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1187 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1188
1189 return cpu_to_le32(dword);
1190 }
1191
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1192 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1193 {
1194 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1195 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1196 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1197 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1198
1199 return cpu_to_le32(dword);
1200 }
1201
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1202 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1203 {
1204 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1205 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1206 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1207
1208 return cpu_to_le32(dword);
1209 }
1210
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1211 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1212 {
1213 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1214 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1215
1216 return cpu_to_le32(dword);
1217 }
1218
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1219 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1220 {
1221 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1222 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1223 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1224 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1225
1226 return cpu_to_le32(dword);
1227 }
1228
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1229 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1230 {
1231 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1232 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1233
1234 return cpu_to_le32(dword);
1235 }
1236
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1237 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1238 {
1239 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1240 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1241 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1242 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1243 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1244 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1245
1246 return cpu_to_le32(dword);
1247 }
1248
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1249 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1250 {
1251 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1252 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1253 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1254 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1255 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1256 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1257
1258 return cpu_to_le32(dword);
1259 }
1260
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1261 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1262 {
1263 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1264 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1265 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1266 desc_info->data_retry_lowest_rate);
1267
1268 return cpu_to_le32(dword);
1269 }
1270
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1271 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1272 {
1273 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1274 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1275 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1276 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1277
1278 return cpu_to_le32(dword);
1279 }
1280
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1281 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1282 {
1283 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1284 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1285 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1286
1287 return cpu_to_le32(dword);
1288 }
1289
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1290 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1291 {
1292 bool rts_en = !desc_info->is_bmc;
1293 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1294 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1295
1296 return cpu_to_le32(dword);
1297 }
1298
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1299 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1300 struct rtw89_tx_desc_info *desc_info,
1301 void *txdesc)
1302 {
1303 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1304 struct rtw89_txwd_info *txwd_info;
1305
1306 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1307 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1308 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1309
1310 if (!desc_info->en_wd_info)
1311 return;
1312
1313 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1314 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1315 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1316 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1317 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1318
1319 }
1320 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1321
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1322 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1323 struct rtw89_tx_desc_info *desc_info,
1324 void *txdesc)
1325 {
1326 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1327 struct rtw89_txwd_info *txwd_info;
1328
1329 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1330 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1331 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1332 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1333 if (desc_info->sec_en) {
1334 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1335 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1336 }
1337 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1338
1339 if (!desc_info->en_wd_info)
1340 return;
1341
1342 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1343 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1344 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1345 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1346 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1347 }
1348 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1349
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1350 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1351 {
1352 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1353 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1354 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1355 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1356 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1357
1358 return cpu_to_le32(dword);
1359 }
1360
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1361 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1362 {
1363 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1364 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1365 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1366
1367 return cpu_to_le32(dword);
1368 }
1369
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1370 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1371 {
1372 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1373 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1374 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1375 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1376 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1377 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1378
1379 return cpu_to_le32(dword);
1380 }
1381
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1382 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1383 {
1384 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq);
1385
1386 return cpu_to_le32(dword);
1387 }
1388
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1389 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1390 {
1391 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1392 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1393
1394 return cpu_to_le32(dword);
1395 }
1396
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1397 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1398 {
1399 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1400 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1401 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1402 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1403
1404 return cpu_to_le32(dword);
1405 }
1406
rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info * desc_info)1407 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info)
1408 {
1409 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr);
1410
1411 return cpu_to_le32(dword);
1412 }
1413
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1414 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1415 {
1416 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1417 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1418 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1419 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1420
1421 return cpu_to_le32(dword);
1422 }
1423
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1424 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1425 {
1426 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1427 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1428 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1429 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port);
1430
1431 return cpu_to_le32(dword);
1432 }
1433
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1434 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1435 {
1436 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1437 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1438 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1439 desc_info->data_retry_lowest_rate);
1440
1441 return cpu_to_le32(dword);
1442 }
1443
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1444 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1445 {
1446 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1447 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1448 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1449
1450 return cpu_to_le32(dword);
1451 }
1452
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1453 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1454 {
1455 bool rts_en = !desc_info->is_bmc;
1456 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1457 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1458
1459 return cpu_to_le32(dword);
1460 }
1461
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1462 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1463 struct rtw89_tx_desc_info *desc_info,
1464 void *txdesc)
1465 {
1466 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1467 struct rtw89_txwd_info_v2 *txwd_info;
1468
1469 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1470 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1471 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1472 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1473 if (desc_info->sec_en) {
1474 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1475 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1476 }
1477 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1478 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1479
1480 if (!desc_info->en_wd_info)
1481 return;
1482
1483 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1484 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1485 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1486 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1487 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1488 }
1489 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1490
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1491 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1492 {
1493 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1494 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1495 RTW89_CORE_RX_TYPE_FWDL :
1496 RTW89_CORE_RX_TYPE_H2C);
1497
1498 return cpu_to_le32(dword);
1499 }
1500
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1501 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1502 struct rtw89_tx_desc_info *desc_info,
1503 void *txdesc)
1504 {
1505 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1506
1507 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1508 }
1509 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1510
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1511 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1512 {
1513 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1514 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1515 RTW89_CORE_RX_TYPE_FWDL :
1516 RTW89_CORE_RX_TYPE_H2C);
1517
1518 return cpu_to_le32(dword);
1519 }
1520
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1521 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1522 struct rtw89_tx_desc_info *desc_info,
1523 void *txdesc)
1524 {
1525 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1526
1527 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1528 }
1529 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1530
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1531 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1532 struct sk_buff *skb,
1533 struct rtw89_rx_phy_ppdu *phy_ppdu)
1534 {
1535 const struct rtw89_chip_info *chip = rtwdev->chip;
1536 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1537 const struct rtw89_rxinfo_user *user;
1538 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1539 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1540 bool rx_cnt_valid = false;
1541 bool invalid = false;
1542 u8 plcp_size = 0;
1543 u8 *phy_sts;
1544 u8 usr_num;
1545 int i;
1546
1547 if (chip_gen == RTW89_CHIP_BE) {
1548 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1549 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1550 }
1551
1552 if (invalid)
1553 return -EINVAL;
1554
1555 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1556 if (chip_gen == RTW89_CHIP_BE) {
1557 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1558 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1559 } else {
1560 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1561 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1562 }
1563 if (usr_num > chip->ppdu_max_usr) {
1564 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1565 usr_num);
1566 return -EINVAL;
1567 }
1568
1569 for (i = 0; i < usr_num; i++) {
1570 user = &rxinfo->user[i];
1571 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1572 continue;
1573 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1574 * by hardware, so update mac_id by rxinfo_user[].mac_id.
1575 */
1576 if (chip_gen == RTW89_CHIP_BE)
1577 phy_ppdu->mac_id =
1578 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1579 phy_ppdu->has_data =
1580 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1581 phy_ppdu->has_bcn =
1582 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN);
1583 break;
1584 }
1585
1586 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1587 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1588 /* 8-byte alignment */
1589 if (usr_num & BIT(0))
1590 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1591 if (rx_cnt_valid)
1592 phy_sts += rx_cnt_size;
1593 phy_sts += plcp_size;
1594
1595 if (phy_sts > skb->data + skb->len)
1596 return -EINVAL;
1597
1598 phy_ppdu->buf = phy_sts;
1599 phy_ppdu->len = skb->data + skb->len - phy_sts;
1600
1601 return 0;
1602 }
1603
rtw89_get_data_rate_nss(struct rtw89_dev * rtwdev,u16 data_rate)1604 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate)
1605 {
1606 u8 data_rate_mode;
1607
1608 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1609 switch (data_rate_mode) {
1610 case DATA_RATE_MODE_NON_HT:
1611 return 1;
1612 case DATA_RATE_MODE_HT:
1613 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1;
1614 case DATA_RATE_MODE_VHT:
1615 case DATA_RATE_MODE_HE:
1616 case DATA_RATE_MODE_EHT:
1617 return rtw89_get_data_nss(rtwdev, data_rate) + 1;
1618 default:
1619 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1620 return 0;
1621 }
1622 }
1623
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1624 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1625 struct ieee80211_sta *sta)
1626 {
1627 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1628 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
1629 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1630 struct rtw89_hal *hal = &rtwdev->hal;
1631 struct rtw89_sta_link *rtwsta_link;
1632 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
1633 u8 ant_pos = U8_MAX;
1634 u8 evm_pos = 0;
1635 int i;
1636
1637 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
1638 * enabling multiple active links, we should determine the right link.
1639 */
1640 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1641 if (unlikely(!rtwsta_link))
1642 return;
1643
1644 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
1645 return;
1646
1647 if (hal->ant_diversity && hal->antenna_rx) {
1648 ant_pos = __ffs(hal->antenna_rx);
1649 evm_pos = ant_pos;
1650 }
1651
1652 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg);
1653
1654 if (ant_pos < ant_num) {
1655 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]);
1656 } else {
1657 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1658 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]);
1659 }
1660
1661 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) {
1662 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr);
1663 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) {
1664 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min);
1665 } else {
1666 ewma_evm_add(&rtwsta_link->evm_min[evm_pos],
1667 phy_ppdu->ofdm.evm_min);
1668 ewma_evm_add(&rtwsta_link->evm_max[evm_pos],
1669 phy_ppdu->ofdm.evm_max);
1670 }
1671 }
1672 }
1673
1674 #define VAR_LEN 0xff
1675 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)1676 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
1677 const struct rtw89_phy_sts_iehdr *iehdr)
1678 {
1679 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = {
1680 [RTW89_CHIP_AX] = {
1681 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1682 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1683 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1684 },
1685 [RTW89_CHIP_BE] = {
1686 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1687 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1688 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1689 },
1690 };
1691 const u8 *physts_ie_len_tab;
1692 u16 ie_len;
1693 u8 ie;
1694
1695 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen];
1696
1697 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1698 if (physts_ie_len_tab[ie] != VAR_LEN)
1699 ie_len = physts_ie_len_tab[ie];
1700 else
1701 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
1702
1703 return ie_len;
1704 }
1705
rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1706 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
1707 const struct rtw89_phy_sts_iehdr *iehdr,
1708 struct rtw89_rx_phy_ppdu *phy_ppdu)
1709 {
1710 const struct rtw89_phy_sts_ie01_v2 *ie;
1711 u8 *rpl_fd = phy_ppdu->rpl_fd;
1712
1713 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
1714 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
1715 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
1716 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
1717 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);
1718
1719 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
1720 }
1721
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1722 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
1723 const struct rtw89_phy_sts_iehdr *iehdr,
1724 struct rtw89_rx_phy_ppdu *phy_ppdu)
1725 {
1726 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
1727 s16 cfo;
1728 u32 t;
1729
1730 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
1731
1732 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
1733 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
1734 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
1735 }
1736
1737 if (!phy_ppdu->hdr_2_en)
1738 phy_ppdu->rx_path_en =
1739 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);
1740
1741 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
1742 return;
1743
1744 if (!phy_ppdu->to_self)
1745 return;
1746
1747 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
1748 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
1749 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
1750 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
1751 phy_ppdu->ofdm.has = true;
1752
1753 /* sign conversion for S(12,2) */
1754 if (rtwdev->chip->cfo_src_fd) {
1755 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
1756 cfo = sign_extend32(t, 11);
1757 } else {
1758 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
1759 cfo = sign_extend32(t, 11);
1760 }
1761
1762 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
1763
1764 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1765 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
1766 }
1767
rtw89_core_parse_phy_status_ie00(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1768 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
1769 const struct rtw89_phy_sts_iehdr *iehdr,
1770 struct rtw89_rx_phy_ppdu *phy_ppdu)
1771 {
1772 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
1773 u16 tmp_rpl;
1774
1775 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
1776 phy_ppdu->rpl_avg = tmp_rpl >> 1;
1777 }
1778
rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1779 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
1780 const struct rtw89_phy_sts_iehdr *iehdr,
1781 struct rtw89_rx_phy_ppdu *phy_ppdu)
1782 {
1783 const struct rtw89_phy_sts_ie00_v2 *ie;
1784 u8 *rpl_path = phy_ppdu->rpl_path;
1785 u16 tmp_rpl[RF_PATH_MAX];
1786 u8 i;
1787
1788 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
1789 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
1790 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
1791 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
1792 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);
1793
1794 for (i = 0; i < RF_PATH_MAX; i++)
1795 rpl_path[i] = tmp_rpl[i] >> 1;
1796 }
1797
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1798 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
1799 const struct rtw89_phy_sts_iehdr *iehdr,
1800 struct rtw89_rx_phy_ppdu *phy_ppdu)
1801 {
1802 u8 ie;
1803
1804 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1805
1806 switch (ie) {
1807 case RTW89_PHYSTS_IE00_CMN_CCK:
1808 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
1809 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1810 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
1811 break;
1812 case RTW89_PHYSTS_IE01_CMN_OFDM:
1813 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
1814 break;
1815 default:
1816 break;
1817 }
1818
1819 return 0;
1820 }
1821
rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu * phy_ppdu)1822 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
1823 {
1824 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;
1825
1826 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
1827 }
1828
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1829 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
1830 {
1831 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1832 u8 *rssi = phy_ppdu->rssi;
1833
1834 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
1835 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
1836 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
1837 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
1838 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
1839 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
1840
1841 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
1842 if (phy_ppdu->hdr_2_en)
1843 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
1844 }
1845
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1846 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
1847 struct rtw89_rx_phy_ppdu *phy_ppdu)
1848 {
1849 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1850 u32 len_from_header;
1851 bool physts_valid;
1852
1853 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
1854 if (!physts_valid)
1855 return -EINVAL;
1856
1857 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
1858
1859 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1860 len_from_header += PHY_STS_HDR_LEN;
1861
1862 if (len_from_header != phy_ppdu->len) {
1863 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
1864 return -EINVAL;
1865 }
1866 rtw89_core_update_phy_ppdu(phy_ppdu);
1867
1868 return 0;
1869 }
1870
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1871 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
1872 struct rtw89_rx_phy_ppdu *phy_ppdu)
1873 {
1874 u16 ie_len;
1875 void *pos, *end;
1876
1877 /* mark invalid reports and bypass them */
1878 if (phy_ppdu->ie < RTW89_CCK_PKT)
1879 return -EINVAL;
1880
1881 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
1882 end = phy_ppdu->buf + phy_ppdu->len;
1883 while (pos < end) {
1884 const struct rtw89_phy_sts_iehdr *iehdr = pos;
1885
1886 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
1887 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
1888 pos += ie_len;
1889 if (pos > end || ie_len == 0) {
1890 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1891 "phy status parse failed\n");
1892 return -EINVAL;
1893 }
1894 }
1895
1896 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
1897 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
1898
1899 return 0;
1900 }
1901
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1902 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
1903 struct rtw89_rx_phy_ppdu *phy_ppdu)
1904 {
1905 int ret;
1906
1907 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
1908 if (ret)
1909 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
1910 else
1911 phy_ppdu->valid = true;
1912
1913 ieee80211_iterate_stations_atomic(rtwdev->hw,
1914 rtw89_core_rx_process_phy_ppdu_iter,
1915 phy_ppdu);
1916 }
1917
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)1918 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
1919 u8 desc_info_gi,
1920 bool rx_status)
1921 {
1922 switch (desc_info_gi) {
1923 case RTW89_GILTF_SGI_4XHE08:
1924 case RTW89_GILTF_2XHE08:
1925 case RTW89_GILTF_1XHE08:
1926 return NL80211_RATE_INFO_HE_GI_0_8;
1927 case RTW89_GILTF_2XHE16:
1928 case RTW89_GILTF_1XHE16:
1929 return NL80211_RATE_INFO_HE_GI_1_6;
1930 case RTW89_GILTF_LGI_4XHE32:
1931 return NL80211_RATE_INFO_HE_GI_3_2;
1932 default:
1933 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
1934 if (rx_status)
1935 return NL80211_RATE_INFO_HE_GI_3_2;
1936 return U8_MAX;
1937 }
1938 }
1939
rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)1940 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev,
1941 u8 desc_info_gi,
1942 bool rx_status)
1943 {
1944 switch (desc_info_gi) {
1945 case RTW89_GILTF_SGI_4XHE08:
1946 case RTW89_GILTF_2XHE08:
1947 case RTW89_GILTF_1XHE08:
1948 return NL80211_RATE_INFO_EHT_GI_0_8;
1949 case RTW89_GILTF_2XHE16:
1950 case RTW89_GILTF_1XHE16:
1951 return NL80211_RATE_INFO_EHT_GI_1_6;
1952 case RTW89_GILTF_LGI_4XHE32:
1953 return NL80211_RATE_INFO_EHT_GI_3_2;
1954 default:
1955 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
1956 if (rx_status)
1957 return NL80211_RATE_INFO_EHT_GI_3_2;
1958 return U8_MAX;
1959 }
1960 }
1961
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)1962 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
1963 u8 desc_info_gi,
1964 bool rx_status, bool eht)
1965 {
1966 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) :
1967 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status);
1968 }
1969
1970 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)1971 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
1972 bool eht)
1973 {
1974 if (eht)
1975 return status->eht.gi == gi_ltf;
1976
1977 return status->he_gi == gi_ltf;
1978 }
1979
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)1980 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
1981 struct rtw89_rx_desc_info *desc_info,
1982 struct ieee80211_rx_status *status)
1983 {
1984 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1985 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
1986 bool eht = false;
1987 u16 data_rate;
1988 bool ret;
1989
1990 data_rate = desc_info->data_rate;
1991 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1992 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1993 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
1994 /* rate_idx is still hardware value here */
1995 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
1996 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
1997 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
1998 data_rate_mode == DATA_RATE_MODE_HE ||
1999 data_rate_mode == DATA_RATE_MODE_EHT) {
2000 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2001 } else {
2002 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2003 }
2004
2005 eht = data_rate_mode == DATA_RATE_MODE_EHT;
2006 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2007 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
2008 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
2009 status->rate_idx == rate_idx &&
2010 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
2011 status->bw == bw;
2012
2013 return ret;
2014 }
2015
2016 struct rtw89_vif_rx_stats_iter_data {
2017 struct rtw89_dev *rtwdev;
2018 struct rtw89_rx_phy_ppdu *phy_ppdu;
2019 struct rtw89_rx_desc_info *desc_info;
2020 struct sk_buff *skb;
2021 const u8 *bssid;
2022 };
2023
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf,struct sk_buff * skb)2024 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
2025 struct rtw89_vif_link *rtwvif_link,
2026 struct ieee80211_bss_conf *bss_conf,
2027 struct sk_buff *skb)
2028 {
2029 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
2030 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
2031 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
2032 u8 *pos, *end, type, tf_bw;
2033 u16 aid, tf_rua;
2034
2035 if (!ether_addr_equal(bss_conf->bssid, tf->ta) ||
2036 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION ||
2037 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK)
2038 return;
2039
2040 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
2041 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
2042 return;
2043
2044 end = (u8 *)tf + skb->len;
2045 pos = tf->variable;
2046
2047 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
2048 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
2049 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
2050 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
2051 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2052 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
2053 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
2054 tf_rua, tf_bw);
2055
2056 if (aid == RTW89_TF_PAD)
2057 break;
2058
2059 if (aid == vif->cfg.aid) {
2060 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
2061
2062 rtwvif->stats.rx_tf_acc++;
2063 rtwdev->stats.rx_tf_acc++;
2064 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
2065 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
2066 rtwvif_link->pwr_diff_en = true;
2067 break;
2068 }
2069
2070 pos += RTW89_TF_BASIC_USER_INFO_SZ;
2071 }
2072 }
2073
rtw89_cancel_6ghz_probe_work(struct work_struct * work)2074 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work)
2075 {
2076 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2077 cancel_6ghz_probe_work);
2078 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2079 struct rtw89_pktofld_info *info;
2080
2081 mutex_lock(&rtwdev->mutex);
2082
2083 if (!rtwdev->scanning)
2084 goto out;
2085
2086 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2087 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
2088 continue;
2089
2090 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2091
2092 /* Don't delete/free info from pkt_list at this moment. Let it
2093 * be deleted/freed in rtw89_release_pkt_list() after scanning,
2094 * since if during scanning, pkt_list is accessed in bottom half.
2095 */
2096 }
2097
2098 out:
2099 mutex_unlock(&rtwdev->mutex);
2100 }
2101
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)2102 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
2103 struct sk_buff *skb)
2104 {
2105 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2106 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2107 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2108 struct rtw89_pktofld_info *info;
2109 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
2110 bool queue_work = false;
2111
2112 if (rx_status->band != NL80211_BAND_6GHZ)
2113 return;
2114
2115 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
2116
2117 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2118 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
2119 info->cancel = true;
2120 queue_work = true;
2121 continue;
2122 }
2123
2124 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
2125 continue;
2126
2127 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
2128 info->cancel = true;
2129 queue_work = true;
2130 }
2131 }
2132
2133 if (queue_work)
2134 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work);
2135 }
2136
rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link * rtwvif_link,struct ieee80211_hdr * hdr,size_t len)2137 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link,
2138 struct ieee80211_hdr *hdr, size_t len)
2139 {
2140 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
2141
2142 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
2143 return;
2144
2145 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
2146 }
2147
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)2148 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
2149 struct ieee80211_vif *vif)
2150 {
2151 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
2152 struct rtw89_dev *rtwdev = iter_data->rtwdev;
2153 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
2154 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2155 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2156 struct sk_buff *skb = iter_data->skb;
2157 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2158 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
2159 struct ieee80211_bss_conf *bss_conf;
2160 struct rtw89_vif_link *rtwvif_link;
2161 const u8 *bssid = iter_data->bssid;
2162
2163 if (rtwdev->scanning &&
2164 (ieee80211_is_beacon(hdr->frame_control) ||
2165 ieee80211_is_probe_resp(hdr->frame_control)))
2166 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
2167
2168 rcu_read_lock();
2169
2170 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2171 * enabling multiple active links, we should determine the right link.
2172 */
2173 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
2174 if (unlikely(!rtwvif_link))
2175 goto out;
2176
2177 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
2178 if (!bss_conf->bssid)
2179 goto out;
2180
2181 if (ieee80211_is_trigger(hdr->frame_control)) {
2182 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb);
2183 goto out;
2184 }
2185
2186 if (!ether_addr_equal(bss_conf->bssid, bssid))
2187 goto out;
2188
2189 if (ieee80211_is_beacon(hdr->frame_control)) {
2190 if (vif->type == NL80211_IFTYPE_STATION &&
2191 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
2192 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len);
2193 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
2194 }
2195 pkt_stat->beacon_nr++;
2196
2197 if (phy_ppdu)
2198 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg);
2199
2200 pkt_stat->beacon_rate = desc_info->data_rate;
2201 }
2202
2203 if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
2204 goto out;
2205
2206 if (desc_info->data_rate < RTW89_HW_RATE_NR)
2207 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
2208
2209 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false);
2210
2211 out:
2212 rcu_read_unlock();
2213 }
2214
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2215 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
2216 struct rtw89_rx_phy_ppdu *phy_ppdu,
2217 struct rtw89_rx_desc_info *desc_info,
2218 struct sk_buff *skb)
2219 {
2220 struct rtw89_vif_rx_stats_iter_data iter_data;
2221
2222 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false);
2223
2224 iter_data.rtwdev = rtwdev;
2225 iter_data.phy_ppdu = phy_ppdu;
2226 iter_data.desc_info = desc_info;
2227 iter_data.skb = skb;
2228 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
2229 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
2230 }
2231
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)2232 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
2233 struct ieee80211_rx_status *status)
2234 {
2235 const struct rtw89_chan_rcd *rcd =
2236 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0);
2237 u16 chan = rcd->prev_primary_channel;
2238 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
2239
2240 if (status->band != NL80211_BAND_2GHZ &&
2241 status->encoding == RX_ENC_LEGACY &&
2242 status->rate_idx < RTW89_HW_RATE_OFDM6) {
2243 status->freq = ieee80211_channel_to_frequency(chan, band);
2244 status->band = band;
2245 }
2246 }
2247
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)2248 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
2249 {
2250 if (rx_status->band == NL80211_BAND_2GHZ ||
2251 rx_status->encoding != RX_ENC_LEGACY)
2252 return;
2253
2254 /* Some control frames' freq(ACKs in this case) are reported wrong due
2255 * to FW notify timing, set to lowest rate to prevent overflow.
2256 */
2257 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
2258 rx_status->rate_idx = 0;
2259 return;
2260 }
2261
2262 /* No 4 CCK rates for non-2G */
2263 rx_status->rate_idx -= 4;
2264 }
2265
2266 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)2267 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
2268 struct ieee80211_rx_status *rx_status,
2269 struct rtw89_rx_phy_ppdu *phy_ppdu)
2270 {
2271 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2272 return;
2273
2274 if (!phy_ppdu)
2275 return;
2276
2277 if (phy_ppdu->ldpc)
2278 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2279 if (phy_ppdu->stbc)
2280 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
2281 }
2282
2283 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
2284 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
2285 [RATE_INFO_BW_5] = U8_MAX,
2286 [RATE_INFO_BW_10] = U8_MAX,
2287 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
2288 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
2289 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
2290 [RATE_INFO_BW_HE_RU] = U8_MAX,
2291 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
2292 [RATE_INFO_BW_EHT_RU] = U8_MAX,
2293 };
2294
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2295 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
2296 struct sk_buff *skb,
2297 struct ieee80211_rx_status *rx_status)
2298 {
2299 struct ieee80211_radiotap_eht_usig *usig;
2300 struct ieee80211_radiotap_eht *eht;
2301 struct ieee80211_radiotap_tlv *tlv;
2302 int eht_len = struct_size(eht, user_info, 1);
2303 int usig_len = sizeof(*usig);
2304 int len;
2305 u8 bw;
2306
2307 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
2308 sizeof(*tlv) + ALIGN(usig_len, 4);
2309
2310 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
2311 skb_reset_mac_header(skb);
2312
2313 /* EHT */
2314 tlv = skb_push(skb, len);
2315 memset(tlv, 0, len);
2316 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
2317 tlv->len = cpu_to_le16(eht_len);
2318
2319 eht = (struct ieee80211_radiotap_eht *)tlv->data;
2320 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
2321 eht->data[0] =
2322 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
2323
2324 eht->user_info[0] =
2325 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
2326 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
2327 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
2328 eht->user_info[0] |=
2329 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
2330 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
2331 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
2332 eht->user_info[0] |=
2333 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
2334
2335 /* U-SIG */
2336 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
2337 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
2338 tlv->len = cpu_to_le16(usig_len);
2339
2340 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
2341 return;
2342
2343 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
2344 if (bw == U8_MAX)
2345 return;
2346
2347 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
2348 usig->common =
2349 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
2350 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
2351 }
2352
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2353 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
2354 struct sk_buff *skb,
2355 struct ieee80211_rx_status *rx_status)
2356 {
2357 static const struct ieee80211_radiotap_he known_he = {
2358 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2359 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
2360 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
2361 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2362 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2363 };
2364 struct ieee80211_radiotap_he *he;
2365
2366 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2367 return;
2368
2369 if (rx_status->encoding == RX_ENC_HE) {
2370 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
2371 he = skb_push(skb, sizeof(*he));
2372 *he = known_he;
2373 } else if (rx_status->encoding == RX_ENC_EHT) {
2374 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
2375 }
2376 }
2377
rtw89_core_validate_rx_signal(struct ieee80211_rx_status * rx_status)2378 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status)
2379 {
2380 if (!rx_status->signal)
2381 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2382 }
2383
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)2384 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
2385 struct rtw89_rx_phy_ppdu *phy_ppdu,
2386 struct rtw89_rx_desc_info *desc_info,
2387 struct sk_buff *skb_ppdu,
2388 struct ieee80211_rx_status *rx_status)
2389 {
2390 struct napi_struct *napi = &rtwdev->napi;
2391
2392 /* In low power mode, napi isn't scheduled. Receive it to netif. */
2393 if (unlikely(!napi_is_scheduled(napi)))
2394 napi = NULL;
2395
2396 rtw89_core_hw_to_sband_rate(rx_status);
2397 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
2398 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
2399 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
2400 rtw89_core_validate_rx_signal(rx_status);
2401
2402 /* In low power mode, it does RX in thread context. */
2403 local_bh_disable();
2404 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
2405 local_bh_enable();
2406 rtwdev->napi_budget_countdown--;
2407 }
2408
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2409 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
2410 struct rtw89_rx_phy_ppdu *phy_ppdu,
2411 struct rtw89_rx_desc_info *desc_info,
2412 struct sk_buff *skb)
2413 {
2414 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2415 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
2416 struct sk_buff *skb_ppdu = NULL, *tmp;
2417 struct ieee80211_rx_status *rx_status;
2418
2419 if (curr > RTW89_MAX_PPDU_CNT)
2420 return;
2421
2422 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
2423 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
2424 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2425 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
2426 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
2427 rtw89_correct_cck_chan(rtwdev, rx_status);
2428 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
2429 }
2430 }
2431
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2432 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
2433 struct rtw89_rx_desc_info *desc_info,
2434 struct sk_buff *skb)
2435 {
2436 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
2437 .len = skb->len,
2438 .to_self = desc_info->addr1_match,
2439 .rate = desc_info->data_rate,
2440 .mac_id = desc_info->mac_id};
2441 int ret;
2442
2443 if (desc_info->mac_info_valid) {
2444 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
2445 if (ret)
2446 goto out;
2447 }
2448
2449 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
2450 if (ret)
2451 goto out;
2452
2453 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
2454
2455 out:
2456 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
2457 dev_kfree_skb_any(skb);
2458 }
2459
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2460 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
2461 struct rtw89_rx_desc_info *desc_info,
2462 struct sk_buff *skb)
2463 {
2464 switch (desc_info->pkt_type) {
2465 case RTW89_CORE_RX_TYPE_C2H:
2466 rtw89_fw_c2h_irqsafe(rtwdev, skb);
2467 break;
2468 case RTW89_CORE_RX_TYPE_PPDU_STAT:
2469 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
2470 break;
2471 default:
2472 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
2473 desc_info->pkt_type);
2474 dev_kfree_skb_any(skb);
2475 break;
2476 }
2477 }
2478
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2479 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
2480 struct rtw89_rx_desc_info *desc_info,
2481 u8 *data, u32 data_offset)
2482 {
2483 const struct rtw89_chip_info *chip = rtwdev->chip;
2484 struct rtw89_rxdesc_short *rxd_s;
2485 struct rtw89_rxdesc_long *rxd_l;
2486 u8 shift_len, drv_info_len;
2487
2488 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
2489 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
2490 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
2491 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
2492 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
2493 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
2494 if (chip->chip_id == RTL8852C)
2495 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
2496 else
2497 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
2498 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
2499 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
2500 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
2501 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
2502 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
2503 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
2504 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
2505 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
2506 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
2507 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
2508 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
2509 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
2510
2511 shift_len = desc_info->shift << 1; /* 2-byte unit */
2512 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2513 desc_info->offset = data_offset + shift_len + drv_info_len;
2514 if (desc_info->long_rxdesc)
2515 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
2516 else
2517 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
2518 desc_info->ready = true;
2519
2520 if (!desc_info->long_rxdesc)
2521 return;
2522
2523 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
2524 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
2525 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
2526 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
2527 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
2528 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
2529 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
2530 }
2531 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
2532
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2533 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
2534 struct rtw89_rx_desc_info *desc_info,
2535 u8 *data, u32 data_offset)
2536 {
2537 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
2538 struct rtw89_rxdesc_short_v2 *rxd_s;
2539 struct rtw89_rxdesc_long_v2 *rxd_l;
2540 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
2541
2542 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
2543
2544 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
2545 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
2546 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
2547 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
2548 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
2549 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
2550 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
2551 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
2552 desc_info->mac_info_valid = true;
2553
2554 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
2555 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
2556 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
2557
2558 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
2559 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
2560 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
2561 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
2562 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
2563
2564 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
2565 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
2566 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
2567 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
2568 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
2569
2570 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
2571
2572 shift_len = desc_info->shift << 1; /* 2-byte unit */
2573 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2574 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
2575 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
2576 desc_info->offset = data_offset + shift_len + drv_info_len +
2577 phy_rtp_len + hdr_cnv_len;
2578
2579 if (desc_info->long_rxdesc)
2580 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
2581 else
2582 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
2583 desc_info->ready = true;
2584
2585 if (phy_rtp_len == sizeof(*rxd_rpt)) {
2586 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
2587 desc_info->rxd_len);
2588 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
2589 }
2590
2591 if (!desc_info->long_rxdesc)
2592 return;
2593
2594 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
2595
2596 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
2597 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
2598 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
2599 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
2600
2601 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
2602 }
2603 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
2604
2605 struct rtw89_core_iter_rx_status {
2606 struct rtw89_dev *rtwdev;
2607 struct ieee80211_rx_status *rx_status;
2608 struct rtw89_rx_desc_info *desc_info;
2609 u8 mac_id;
2610 };
2611
2612 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)2613 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
2614 {
2615 struct rtw89_core_iter_rx_status *iter_data =
2616 (struct rtw89_core_iter_rx_status *)data;
2617 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
2618 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2619 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2620 struct rtw89_sta_link *rtwsta_link;
2621 u8 mac_id = iter_data->mac_id;
2622
2623 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2624 * enabling multiple active links, we should determine the right link.
2625 */
2626 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
2627 if (unlikely(!rtwsta_link))
2628 return;
2629
2630 if (mac_id != rtwsta_link->mac_id)
2631 return;
2632
2633 rtwsta_link->rx_status = *rx_status;
2634 rtwsta_link->rx_hw_rate = desc_info->data_rate;
2635 }
2636
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2637 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
2638 struct rtw89_rx_desc_info *desc_info,
2639 struct ieee80211_rx_status *rx_status)
2640 {
2641 struct rtw89_core_iter_rx_status iter_data;
2642
2643 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
2644 return;
2645
2646 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
2647 return;
2648
2649 iter_data.rtwdev = rtwdev;
2650 iter_data.rx_status = rx_status;
2651 iter_data.desc_info = desc_info;
2652 iter_data.mac_id = desc_info->mac_id;
2653 ieee80211_iterate_stations_atomic(rtwdev->hw,
2654 rtw89_core_stats_sta_rx_status_iter,
2655 &iter_data);
2656 }
2657
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2658 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
2659 struct rtw89_rx_desc_info *desc_info,
2660 struct ieee80211_rx_status *rx_status)
2661 {
2662 const struct cfg80211_chan_def *chandef =
2663 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0);
2664 u16 data_rate;
2665 u8 data_rate_mode;
2666 bool eht = false;
2667 u8 gi;
2668
2669 /* currently using single PHY */
2670 rx_status->freq = chandef->chan->center_freq;
2671 rx_status->band = chandef->chan->band;
2672
2673 if (rtwdev->scanning &&
2674 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
2675 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
2676 u8 chan = cur->primary_channel;
2677 u8 band = cur->band_type;
2678 enum nl80211_band nl_band;
2679
2680 nl_band = rtw89_hw_to_nl80211_band(band);
2681 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
2682 rx_status->band = nl_band;
2683 }
2684
2685 if (desc_info->icv_err || desc_info->crc32_err)
2686 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2687
2688 if (desc_info->hw_dec &&
2689 !(desc_info->sw_dec || desc_info->icv_err))
2690 rx_status->flag |= RX_FLAG_DECRYPTED;
2691
2692 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2693
2694 data_rate = desc_info->data_rate;
2695 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2696 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2697 rx_status->encoding = RX_ENC_LEGACY;
2698 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2699 /* convert rate_idx after we get the correct band */
2700 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2701 rx_status->encoding = RX_ENC_HT;
2702 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2703 if (desc_info->gi_ltf)
2704 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2705 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
2706 rx_status->encoding = RX_ENC_VHT;
2707 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2708 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2709 if (desc_info->gi_ltf)
2710 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2711 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
2712 rx_status->encoding = RX_ENC_HE;
2713 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2714 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2715 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
2716 rx_status->encoding = RX_ENC_EHT;
2717 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2718 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2719 eht = true;
2720 } else {
2721 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2722 }
2723
2724 /* he_gi is used to match ppdu, so we always fill it. */
2725 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
2726 if (eht)
2727 rx_status->eht.gi = gi;
2728 else
2729 rx_status->he_gi = gi;
2730 rx_status->flag |= RX_FLAG_MACTIME_START;
2731 rx_status->mactime = desc_info->free_run_cnt;
2732
2733 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
2734 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
2735 }
2736
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)2737 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
2738 {
2739 const struct rtw89_chip_info *chip = rtwdev->chip;
2740
2741 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
2742 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
2743 return RTW89_PS_MODE_NONE;
2744
2745 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
2746 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
2747 return RTW89_PS_MODE_PWR_GATED;
2748
2749 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
2750 return RTW89_PS_MODE_CLK_GATED;
2751
2752 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
2753 return RTW89_PS_MODE_RFOFF;
2754
2755 return RTW89_PS_MODE_NONE;
2756 }
2757
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)2758 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
2759 struct rtw89_rx_desc_info *desc_info)
2760 {
2761 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2762 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2763 struct ieee80211_rx_status *rx_status;
2764 struct sk_buff *skb_ppdu, *tmp;
2765
2766 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
2767 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
2768 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2769 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
2770 }
2771 }
2772
2773 static
rtw89_core_rx_pkt_hdl(struct rtw89_dev * rtwdev,const struct sk_buff * skb,const struct rtw89_rx_desc_info * desc)2774 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb,
2775 const struct rtw89_rx_desc_info *desc)
2776 {
2777 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2778 struct rtw89_sta_link *rtwsta_link;
2779 struct ieee80211_sta *sta;
2780 struct rtw89_sta *rtwsta;
2781 u8 macid = desc->mac_id;
2782
2783 if (!refcount_read(&rtwdev->refcount_ap_info))
2784 return;
2785
2786 rcu_read_lock();
2787
2788 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid);
2789 if (!rtwsta_link)
2790 goto out;
2791
2792 rtwsta = rtwsta_link->rtwsta;
2793 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags))
2794 goto out;
2795
2796 sta = rtwsta_to_sta(rtwsta);
2797 if (ieee80211_is_pspoll(hdr->frame_control))
2798 ieee80211_sta_pspoll(sta);
2799 else if (ieee80211_has_pm(hdr->frame_control) &&
2800 (ieee80211_is_data_qos(hdr->frame_control) ||
2801 ieee80211_is_qos_nullfunc(hdr->frame_control)))
2802 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr));
2803
2804 out:
2805 rcu_read_unlock();
2806 }
2807
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2808 void rtw89_core_rx(struct rtw89_dev *rtwdev,
2809 struct rtw89_rx_desc_info *desc_info,
2810 struct sk_buff *skb)
2811 {
2812 struct ieee80211_rx_status *rx_status;
2813 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2814 u8 ppdu_cnt = desc_info->ppdu_cnt;
2815 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2816
2817 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
2818 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
2819 return;
2820 }
2821
2822 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
2823 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
2824 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
2825 }
2826
2827 rx_status = IEEE80211_SKB_RXCB(skb);
2828 memset(rx_status, 0, sizeof(*rx_status));
2829 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status);
2830 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info);
2831 if (desc_info->long_rxdesc &&
2832 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
2833 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
2834 else
2835 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
2836 }
2837 EXPORT_SYMBOL(rtw89_core_rx);
2838
rtw89_core_napi_start(struct rtw89_dev * rtwdev)2839 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
2840 {
2841 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2842 return;
2843
2844 napi_enable(&rtwdev->napi);
2845 }
2846 EXPORT_SYMBOL(rtw89_core_napi_start);
2847
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)2848 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
2849 {
2850 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2851 return;
2852
2853 napi_synchronize(&rtwdev->napi);
2854 napi_disable(&rtwdev->napi);
2855 }
2856 EXPORT_SYMBOL(rtw89_core_napi_stop);
2857
rtw89_core_napi_init(struct rtw89_dev * rtwdev)2858 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
2859 {
2860 rtwdev->netdev = alloc_netdev_dummy(0);
2861 if (!rtwdev->netdev)
2862 return -ENOMEM;
2863
2864 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
2865 rtwdev->hci.ops->napi_poll);
2866 return 0;
2867 }
2868 EXPORT_SYMBOL(rtw89_core_napi_init);
2869
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)2870 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
2871 {
2872 rtw89_core_napi_stop(rtwdev);
2873 netif_napi_del(&rtwdev->napi);
2874 free_netdev(rtwdev->netdev);
2875 }
2876 EXPORT_SYMBOL(rtw89_core_napi_deinit);
2877
rtw89_core_ba_work(struct work_struct * work)2878 static void rtw89_core_ba_work(struct work_struct *work)
2879 {
2880 struct rtw89_dev *rtwdev =
2881 container_of(work, struct rtw89_dev, ba_work);
2882 struct rtw89_txq *rtwtxq, *tmp;
2883 int ret;
2884
2885 spin_lock_bh(&rtwdev->ba_lock);
2886 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2887 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2888 struct ieee80211_sta *sta = txq->sta;
2889 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2890 u8 tid = txq->tid;
2891
2892 if (!sta) {
2893 rtw89_warn(rtwdev, "cannot start BA without sta\n");
2894 goto skip_ba_work;
2895 }
2896
2897 if (rtwsta->disassoc) {
2898 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2899 "cannot start BA with disassoc sta\n");
2900 goto skip_ba_work;
2901 }
2902
2903 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
2904 if (ret) {
2905 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2906 "failed to setup BA session for %pM:%2d: %d\n",
2907 sta->addr, tid, ret);
2908 if (ret == -EINVAL)
2909 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
2910 }
2911 skip_ba_work:
2912 list_del_init(&rtwtxq->list);
2913 }
2914 spin_unlock_bh(&rtwdev->ba_lock);
2915 }
2916
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2917 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
2918 struct ieee80211_sta *sta)
2919 {
2920 struct rtw89_txq *rtwtxq, *tmp;
2921
2922 spin_lock_bh(&rtwdev->ba_lock);
2923 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2924 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2925
2926 if (sta == txq->sta)
2927 list_del_init(&rtwtxq->list);
2928 }
2929 spin_unlock_bh(&rtwdev->ba_lock);
2930 }
2931
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2932 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
2933 struct ieee80211_sta *sta)
2934 {
2935 struct rtw89_txq *rtwtxq, *tmp;
2936
2937 spin_lock_bh(&rtwdev->ba_lock);
2938 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2939 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2940
2941 if (sta == txq->sta) {
2942 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2943 list_del_init(&rtwtxq->list);
2944 }
2945 }
2946 spin_unlock_bh(&rtwdev->ba_lock);
2947 }
2948
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2949 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
2950 struct ieee80211_sta *sta)
2951 {
2952 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2953 struct sk_buff *skb, *tmp;
2954
2955 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
2956 skb_unlink(skb, &rtwsta->roc_queue);
2957 dev_kfree_skb_any(skb);
2958 }
2959 }
2960
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)2961 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
2962 struct rtw89_txq *rtwtxq)
2963 {
2964 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2965 struct ieee80211_sta *sta = txq->sta;
2966 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2967
2968 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
2969 return;
2970
2971 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
2972 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2973 return;
2974
2975 spin_lock_bh(&rtwdev->ba_lock);
2976 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2977 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
2978 spin_unlock_bh(&rtwdev->ba_lock);
2979
2980 ieee80211_stop_tx_ba_session(sta, txq->tid);
2981 cancel_delayed_work(&rtwdev->forbid_ba_work);
2982 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
2983 RTW89_FORBID_BA_TIMER);
2984 }
2985
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)2986 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
2987 struct rtw89_txq *rtwtxq,
2988 struct sk_buff *skb)
2989 {
2990 struct ieee80211_hw *hw = rtwdev->hw;
2991 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2992 struct ieee80211_sta *sta = txq->sta;
2993 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2994
2995 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2996 return;
2997
2998 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
2999 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
3000 return;
3001 }
3002
3003 if (unlikely(!sta))
3004 return;
3005
3006 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
3007 return;
3008
3009 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
3010 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
3011 return;
3012 }
3013
3014 spin_lock_bh(&rtwdev->ba_lock);
3015 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
3016 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
3017 ieee80211_queue_work(hw, &rtwdev->ba_work);
3018 }
3019 spin_unlock_bh(&rtwdev->ba_lock);
3020 }
3021
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)3022 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
3023 struct rtw89_txq *rtwtxq,
3024 unsigned long frame_cnt,
3025 unsigned long byte_cnt)
3026 {
3027 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3028 struct ieee80211_vif *vif = txq->vif;
3029 struct ieee80211_sta *sta = txq->sta;
3030 struct sk_buff *skb;
3031 unsigned long i;
3032 int ret;
3033
3034 rcu_read_lock();
3035 for (i = 0; i < frame_cnt; i++) {
3036 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
3037 if (!skb) {
3038 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
3039 goto out;
3040 }
3041 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
3042 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
3043 if (ret) {
3044 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
3045 ieee80211_free_txskb(rtwdev->hw, skb);
3046 break;
3047 }
3048 }
3049 out:
3050 rcu_read_unlock();
3051 }
3052
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)3053 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
3054 {
3055 u8 qsel, ch_dma;
3056
3057 qsel = rtw89_core_get_qsel(rtwdev, tid);
3058 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
3059
3060 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
3061 }
3062
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)3063 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
3064 struct ieee80211_txq *txq,
3065 unsigned long *frame_cnt,
3066 bool *sched_txq, bool *reinvoke)
3067 {
3068 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3069 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta);
3070 struct rtw89_sta_link *rtwsta_link;
3071
3072 if (!rtwsta)
3073 return false;
3074
3075 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
3076 if (unlikely(!rtwsta_link)) {
3077 rtw89_err(rtwdev, "agg wait: find no link on HW-0\n");
3078 return false;
3079 }
3080
3081 if (rtwsta_link->max_agg_wait <= 0)
3082 return false;
3083
3084 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
3085 return false;
3086
3087 if (*frame_cnt > 1) {
3088 *frame_cnt -= 1;
3089 *sched_txq = true;
3090 *reinvoke = true;
3091 rtwtxq->wait_cnt = 1;
3092 return false;
3093 }
3094
3095 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) {
3096 *reinvoke = true;
3097 rtwtxq->wait_cnt++;
3098 return true;
3099 }
3100
3101 rtwtxq->wait_cnt = 0;
3102 return false;
3103 }
3104
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)3105 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
3106 {
3107 struct ieee80211_hw *hw = rtwdev->hw;
3108 struct ieee80211_txq *txq;
3109 struct rtw89_vif *rtwvif;
3110 struct rtw89_txq *rtwtxq;
3111 unsigned long frame_cnt;
3112 unsigned long byte_cnt;
3113 u32 tx_resource;
3114 bool sched_txq;
3115
3116 ieee80211_txq_schedule_start(hw, ac);
3117 while ((txq = ieee80211_next_txq(hw, ac))) {
3118 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3119 rtwvif = vif_to_rtwvif(txq->vif);
3120
3121 if (rtwvif->offchan) {
3122 ieee80211_return_txq(hw, txq, true);
3123 continue;
3124 }
3125 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
3126 sched_txq = false;
3127
3128 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
3129 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
3130 ieee80211_return_txq(hw, txq, true);
3131 continue;
3132 }
3133 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
3134 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
3135 ieee80211_return_txq(hw, txq, sched_txq);
3136 if (frame_cnt != 0)
3137 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
3138
3139 /* bound of tx_resource could get stuck due to burst traffic */
3140 if (frame_cnt == tx_resource)
3141 *reinvoke = true;
3142 }
3143 ieee80211_txq_schedule_end(hw, ac);
3144 }
3145
rtw89_ips_work(struct work_struct * work)3146 static void rtw89_ips_work(struct work_struct *work)
3147 {
3148 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3149 ips_work);
3150 mutex_lock(&rtwdev->mutex);
3151 rtw89_enter_ips_by_hwflags(rtwdev);
3152 mutex_unlock(&rtwdev->mutex);
3153 }
3154
rtw89_core_txq_work(struct work_struct * w)3155 static void rtw89_core_txq_work(struct work_struct *w)
3156 {
3157 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
3158 bool reinvoke = false;
3159 u8 ac;
3160
3161 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
3162 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
3163
3164 if (reinvoke) {
3165 /* reinvoke to process the last frame */
3166 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
3167 }
3168 }
3169
rtw89_core_txq_reinvoke_work(struct work_struct * w)3170 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
3171 {
3172 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3173 txq_reinvoke_work.work);
3174
3175 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3176 }
3177
rtw89_forbid_ba_work(struct work_struct * w)3178 static void rtw89_forbid_ba_work(struct work_struct *w)
3179 {
3180 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3181 forbid_ba_work.work);
3182 struct rtw89_txq *rtwtxq, *tmp;
3183
3184 spin_lock_bh(&rtwdev->ba_lock);
3185 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
3186 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3187 list_del_init(&rtwtxq->list);
3188 }
3189 spin_unlock_bh(&rtwdev->ba_lock);
3190 }
3191
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)3192 static void rtw89_core_sta_pending_tx_iter(void *data,
3193 struct ieee80211_sta *sta)
3194 {
3195 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3196 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3197 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
3198 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3199 struct rtw89_vif_link *target = data;
3200 struct rtw89_vif_link *rtwvif_link;
3201 struct sk_buff *skb, *tmp;
3202 unsigned int link_id;
3203 int qsel, ret;
3204
3205 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3206 if (rtwvif_link->chanctx_idx == target->chanctx_idx)
3207 goto bottom;
3208
3209 return;
3210
3211 bottom:
3212 if (skb_queue_len(&rtwsta->roc_queue) == 0)
3213 return;
3214
3215 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
3216 skb_unlink(skb, &rtwsta->roc_queue);
3217
3218 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3219 if (ret) {
3220 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
3221 dev_kfree_skb_any(skb);
3222 } else {
3223 rtw89_core_tx_kick_off(rtwdev, qsel);
3224 }
3225 }
3226 }
3227
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)3228 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
3229 struct rtw89_vif_link *rtwvif_link)
3230 {
3231 ieee80211_iterate_stations_atomic(rtwdev->hw,
3232 rtw89_core_sta_pending_tx_iter,
3233 rtwvif_link);
3234 }
3235
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool qos,bool ps)3236 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev,
3237 struct rtw89_vif_link *rtwvif_link, bool qos, bool ps)
3238 {
3239 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3240 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1;
3241 struct ieee80211_sta *sta;
3242 struct ieee80211_hdr *hdr;
3243 struct sk_buff *skb;
3244 int ret, qsel;
3245
3246 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
3247 return 0;
3248
3249 rcu_read_lock();
3250 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr);
3251 if (!sta) {
3252 ret = -EINVAL;
3253 goto out;
3254 }
3255
3256 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos);
3257 if (!skb) {
3258 ret = -ENOMEM;
3259 goto out;
3260 }
3261
3262 hdr = (struct ieee80211_hdr *)skb->data;
3263 if (ps)
3264 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
3265
3266 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3267 if (ret) {
3268 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
3269 dev_kfree_skb_any(skb);
3270 goto out;
3271 }
3272
3273 rcu_read_unlock();
3274
3275 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel,
3276 RTW89_ROC_TX_TIMEOUT);
3277 out:
3278 rcu_read_unlock();
3279
3280 return ret;
3281 }
3282
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3283 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3284 {
3285 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3286 struct ieee80211_hw *hw = rtwdev->hw;
3287 struct rtw89_roc *roc = &rtwvif->roc;
3288 struct rtw89_vif_link *rtwvif_link;
3289 struct cfg80211_chan_def roc_chan;
3290 struct rtw89_vif *tmp_vif;
3291 u32 reg;
3292 int ret;
3293
3294 lockdep_assert_held(&rtwdev->mutex);
3295
3296 rtw89_leave_ips_by_hwflags(rtwdev);
3297 rtw89_leave_lps(rtwdev);
3298
3299 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3300 if (unlikely(!rtwvif_link)) {
3301 rtw89_err(rtwdev, "roc start: find no link on HW-%u\n",
3302 RTW89_ROC_BY_LINK_INDEX);
3303 return;
3304 }
3305
3306 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC);
3307
3308 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true);
3309 if (ret)
3310 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3311 "roc send null-1 failed: %d\n", ret);
3312
3313 rtw89_for_each_rtwvif(rtwdev, tmp_vif) {
3314 struct rtw89_vif_link *tmp_link;
3315 unsigned int link_id;
3316
3317 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) {
3318 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) {
3319 tmp_vif->offchan = true;
3320 break;
3321 }
3322 }
3323 }
3324
3325 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
3326 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, &roc_chan);
3327 rtw89_set_channel(rtwdev);
3328
3329 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
3330 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
3331
3332 ieee80211_ready_on_channel(hw);
3333 cancel_delayed_work(&rtwvif->roc.roc_work);
3334 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work,
3335 msecs_to_jiffies(rtwvif->roc.duration));
3336 }
3337
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3338 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3339 {
3340 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3341 struct ieee80211_hw *hw = rtwdev->hw;
3342 struct rtw89_roc *roc = &rtwvif->roc;
3343 struct rtw89_vif_link *rtwvif_link;
3344 struct rtw89_vif *tmp_vif;
3345 u32 reg;
3346 int ret;
3347
3348 lockdep_assert_held(&rtwdev->mutex);
3349
3350 ieee80211_remain_on_channel_expired(hw);
3351
3352 rtw89_leave_ips_by_hwflags(rtwdev);
3353 rtw89_leave_lps(rtwdev);
3354
3355 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3356 if (unlikely(!rtwvif_link)) {
3357 rtw89_err(rtwdev, "roc end: find no link on HW-%u\n",
3358 RTW89_ROC_BY_LINK_INDEX);
3359 return;
3360 }
3361
3362 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
3363 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
3364
3365 roc->state = RTW89_ROC_IDLE;
3366 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, NULL);
3367 rtw89_chanctx_proceed(rtwdev, NULL);
3368 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false);
3369 if (ret)
3370 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3371 "roc send null-0 failed: %d\n", ret);
3372
3373 rtw89_for_each_rtwvif(rtwdev, tmp_vif)
3374 tmp_vif->offchan = false;
3375
3376 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link);
3377 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3378
3379 if (hw->conf.flags & IEEE80211_CONF_IDLE)
3380 ieee80211_queue_delayed_work(hw, &roc->roc_work,
3381 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
3382 }
3383
rtw89_roc_work(struct work_struct * work)3384 void rtw89_roc_work(struct work_struct *work)
3385 {
3386 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
3387 roc.roc_work.work);
3388 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3389 struct rtw89_roc *roc = &rtwvif->roc;
3390
3391 mutex_lock(&rtwdev->mutex);
3392
3393 switch (roc->state) {
3394 case RTW89_ROC_IDLE:
3395 rtw89_enter_ips_by_hwflags(rtwdev);
3396 break;
3397 case RTW89_ROC_MGMT:
3398 case RTW89_ROC_NORMAL:
3399 rtw89_roc_end(rtwdev, rtwvif);
3400 break;
3401 default:
3402 break;
3403 }
3404
3405 mutex_unlock(&rtwdev->mutex);
3406 }
3407
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)3408 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
3409 u32 throughput, u64 cnt)
3410 {
3411 if (cnt < 100)
3412 return RTW89_TFC_IDLE;
3413 if (throughput > 50)
3414 return RTW89_TFC_HIGH;
3415 if (throughput > 10)
3416 return RTW89_TFC_MID;
3417 if (throughput > 2)
3418 return RTW89_TFC_LOW;
3419 return RTW89_TFC_ULTRA_LOW;
3420 }
3421
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3422 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
3423 struct rtw89_traffic_stats *stats)
3424 {
3425 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
3426 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
3427
3428 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT);
3429 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT);
3430
3431 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
3432 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
3433
3434 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
3435 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
3436 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
3437 stats->tx_cnt);
3438 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
3439 stats->rx_cnt);
3440 stats->tx_avg_len = stats->tx_cnt ?
3441 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
3442 stats->rx_avg_len = stats->rx_cnt ?
3443 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
3444
3445 stats->tx_unicast = 0;
3446 stats->rx_unicast = 0;
3447 stats->tx_cnt = 0;
3448 stats->rx_cnt = 0;
3449 stats->rx_tf_periodic = stats->rx_tf_acc;
3450 stats->rx_tf_acc = 0;
3451
3452 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
3453 return true;
3454
3455 return false;
3456 }
3457
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)3458 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
3459 {
3460 struct rtw89_vif_link *rtwvif_link;
3461 struct rtw89_vif *rtwvif;
3462 unsigned int link_id;
3463 bool tfc_changed;
3464
3465 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats);
3466
3467 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3468 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats);
3469
3470 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3471 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link);
3472 }
3473
3474 return tfc_changed;
3475 }
3476
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)3477 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
3478 {
3479 struct ieee80211_vif *vif;
3480 struct rtw89_vif *rtwvif;
3481
3482 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3483 if (rtwvif->tdls_peer)
3484 continue;
3485 if (rtwvif->offchan)
3486 continue;
3487
3488 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE ||
3489 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE)
3490 continue;
3491
3492 vif = rtwvif_to_vif(rtwvif);
3493
3494 if (!(vif->type == NL80211_IFTYPE_STATION ||
3495 vif->type == NL80211_IFTYPE_P2P_CLIENT))
3496 continue;
3497
3498 rtw89_enter_lps(rtwdev, rtwvif, true);
3499 }
3500 }
3501
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)3502 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
3503 {
3504 enum rtw89_entity_mode mode;
3505
3506 mode = rtw89_get_entity_mode(rtwdev);
3507 if (mode == RTW89_ENTITY_MODE_MCC)
3508 return;
3509
3510 rtw89_chip_rfk_track(rtwdev);
3511 }
3512
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf)3513 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
3514 struct rtw89_vif_link *rtwvif_link,
3515 struct ieee80211_bss_conf *bss_conf)
3516 {
3517 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
3518
3519 if (mode == RTW89_ENTITY_MODE_MCC)
3520 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
3521 else
3522 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf);
3523 }
3524
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3525 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3526 struct rtw89_traffic_stats *stats)
3527 {
3528 stats->tx_unicast = 0;
3529 stats->rx_unicast = 0;
3530 stats->tx_cnt = 0;
3531 stats->rx_cnt = 0;
3532 ewma_tp_init(&stats->tx_ewma_tp);
3533 ewma_tp_init(&stats->rx_ewma_tp);
3534 }
3535
rtw89_track_work(struct work_struct * work)3536 static void rtw89_track_work(struct work_struct *work)
3537 {
3538 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3539 track_work.work);
3540 bool tfc_changed;
3541
3542 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
3543 return;
3544
3545 mutex_lock(&rtwdev->mutex);
3546
3547 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
3548 goto out;
3549
3550 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
3551 RTW89_TRACK_WORK_PERIOD);
3552
3553 tfc_changed = rtw89_traffic_stats_track(rtwdev);
3554 if (rtwdev->scanning)
3555 goto out;
3556
3557 rtw89_leave_lps(rtwdev);
3558
3559 if (tfc_changed) {
3560 rtw89_hci_recalc_int_mit(rtwdev);
3561 rtw89_btc_ntfy_wl_sta(rtwdev);
3562 }
3563 rtw89_mac_bf_monitor_track(rtwdev);
3564 rtw89_phy_stat_track(rtwdev);
3565 rtw89_phy_env_monitor_track(rtwdev);
3566 rtw89_phy_dig(rtwdev);
3567 rtw89_core_rfk_track(rtwdev);
3568 rtw89_phy_ra_update(rtwdev);
3569 rtw89_phy_cfo_track(rtwdev);
3570 rtw89_phy_tx_path_div_track(rtwdev);
3571 rtw89_phy_antdiv_track(rtwdev);
3572 rtw89_phy_ul_tb_ctrl_track(rtwdev);
3573 rtw89_phy_edcca_track(rtwdev);
3574 rtw89_tas_track(rtwdev);
3575 rtw89_chanctx_track(rtwdev);
3576 rtw89_core_rfkill_poll(rtwdev, false);
3577
3578 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
3579 rtw89_enter_lps_track(rtwdev);
3580
3581 out:
3582 mutex_unlock(&rtwdev->mutex);
3583 }
3584
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)3585 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
3586 {
3587 unsigned long bit;
3588
3589 bit = find_first_zero_bit(addr, size);
3590 if (bit < size)
3591 set_bit(bit, addr);
3592
3593 return bit;
3594 }
3595
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)3596 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
3597 {
3598 clear_bit(bit, addr);
3599 }
3600
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)3601 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
3602 {
3603 bitmap_zero(addr, nbits);
3604 }
3605
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3606 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
3607 struct rtw89_sta_link *rtwsta_link, u8 tid,
3608 u8 *cam_idx)
3609 {
3610 const struct rtw89_chip_info *chip = rtwdev->chip;
3611 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3612 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3613 u8 idx;
3614 int i;
3615
3616 lockdep_assert_held(&rtwdev->mutex);
3617
3618 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
3619 if (idx == chip->bacam_num) {
3620 /* allocate a static BA CAM to tid=0/5, so replace the existing
3621 * one if BA CAM is full. Hardware will process the original tid
3622 * automatically.
3623 */
3624 if (tid != 0 && tid != 5)
3625 return -ENOSPC;
3626
3627 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
3628 tmp = &cam_info->ba_cam_entry[i];
3629 if (tmp->tid == 0 || tmp->tid == 5)
3630 continue;
3631
3632 idx = i;
3633 entry = tmp;
3634 list_del(&entry->list);
3635 break;
3636 }
3637
3638 if (!entry)
3639 return -ENOSPC;
3640 } else {
3641 entry = &cam_info->ba_cam_entry[idx];
3642 }
3643
3644 entry->tid = tid;
3645 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list);
3646
3647 *cam_idx = idx;
3648
3649 return 0;
3650 }
3651
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3652 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
3653 struct rtw89_sta_link *rtwsta_link, u8 tid,
3654 u8 *cam_idx)
3655 {
3656 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3657 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3658 u8 idx;
3659
3660 lockdep_assert_held(&rtwdev->mutex);
3661
3662 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) {
3663 if (entry->tid != tid)
3664 continue;
3665
3666 idx = entry - cam_info->ba_cam_entry;
3667 list_del(&entry->list);
3668
3669 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
3670 *cam_idx = idx;
3671 return 0;
3672 }
3673
3674 return -ENOENT;
3675 }
3676
3677 #define RTW89_TYPE_MAPPING(_type) \
3678 case NL80211_IFTYPE_ ## _type: \
3679 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
3680 break
rtw89_vif_type_mapping(struct rtw89_vif_link * rtwvif_link,bool assoc)3681 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc)
3682 {
3683 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3684 const struct ieee80211_bss_conf *bss_conf;
3685
3686 switch (vif->type) {
3687 case NL80211_IFTYPE_STATION:
3688 if (vif->p2p)
3689 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
3690 else
3691 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION;
3692 break;
3693 case NL80211_IFTYPE_AP:
3694 if (vif->p2p)
3695 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
3696 else
3697 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP;
3698 break;
3699 RTW89_TYPE_MAPPING(ADHOC);
3700 RTW89_TYPE_MAPPING(MONITOR);
3701 RTW89_TYPE_MAPPING(MESH_POINT);
3702 default:
3703 WARN_ON(1);
3704 break;
3705 }
3706
3707 switch (vif->type) {
3708 case NL80211_IFTYPE_AP:
3709 case NL80211_IFTYPE_MESH_POINT:
3710 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE;
3711 rtwvif_link->self_role = RTW89_SELF_ROLE_AP;
3712 break;
3713 case NL80211_IFTYPE_ADHOC:
3714 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC;
3715 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3716 break;
3717 case NL80211_IFTYPE_STATION:
3718 if (assoc) {
3719 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA;
3720
3721 rcu_read_lock();
3722 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
3723 rtwvif_link->trigger = bss_conf->he_support;
3724 rcu_read_unlock();
3725 } else {
3726 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK;
3727 rtwvif_link->trigger = false;
3728 }
3729 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3730 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
3731 break;
3732 case NL80211_IFTYPE_MONITOR:
3733 break;
3734 default:
3735 WARN_ON(1);
3736 break;
3737 }
3738 }
3739
rtw89_core_sta_link_add(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3740 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
3741 struct rtw89_vif_link *rtwvif_link,
3742 struct rtw89_sta_link *rtwsta_link)
3743 {
3744 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3745 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3746 struct rtw89_hal *hal = &rtwdev->hal;
3747 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3748 int i;
3749 int ret;
3750
3751 rtwsta_link->prev_rssi = 0;
3752 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list);
3753 ewma_rssi_init(&rtwsta_link->avg_rssi);
3754 ewma_snr_init(&rtwsta_link->avg_snr);
3755 ewma_evm_init(&rtwsta_link->evm_1ss);
3756 for (i = 0; i < ant_num; i++) {
3757 ewma_rssi_init(&rtwsta_link->rssi[i]);
3758 ewma_evm_init(&rtwsta_link->evm_min[i]);
3759 ewma_evm_init(&rtwsta_link->evm_max[i]);
3760 }
3761
3762 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3763 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
3764 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true);
3765 if (ret)
3766 return ret;
3767
3768 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3769 BTC_ROLE_MSTS_STA_CONN_START);
3770 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
3771 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3772 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false);
3773 if (ret) {
3774 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
3775 return ret;
3776 }
3777
3778 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
3779 RTW89_ROLE_CREATE);
3780 if (ret) {
3781 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3782 return ret;
3783 }
3784
3785 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3786 if (ret)
3787 return ret;
3788
3789 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3790 if (ret)
3791 return ret;
3792 }
3793
3794 return 0;
3795 }
3796
rtw89_core_sta_link_disassoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3797 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
3798 struct rtw89_vif_link *rtwvif_link,
3799 struct rtw89_sta_link *rtwsta_link)
3800 {
3801 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3802
3803 rtw89_assoc_link_clr(rtwsta_link);
3804
3805 if (vif->type == NL80211_IFTYPE_STATION)
3806 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false);
3807
3808 return 0;
3809 }
3810
rtw89_core_sta_link_disconnect(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3811 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
3812 struct rtw89_vif_link *rtwvif_link,
3813 struct rtw89_sta_link *rtwsta_link)
3814 {
3815 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3816 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3817 int ret;
3818
3819 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true);
3820 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link);
3821
3822 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
3823 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam);
3824 if (sta->tdls)
3825 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam);
3826
3827 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3828 rtw89_vif_type_mapping(rtwvif_link, false);
3829 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true);
3830 }
3831
3832 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3833 if (ret) {
3834 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3835 return ret;
3836 }
3837
3838 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true);
3839 if (ret) {
3840 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3841 return ret;
3842 }
3843
3844 /* update cam aid mac_id net_type */
3845 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3846 if (ret) {
3847 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3848 return ret;
3849 }
3850
3851 return ret;
3852 }
3853
rtw89_sta_link_can_er(struct rtw89_dev * rtwdev,struct ieee80211_bss_conf * bss_conf,struct ieee80211_link_sta * link_sta)3854 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev,
3855 struct ieee80211_bss_conf *bss_conf,
3856 struct ieee80211_link_sta *link_sta)
3857 {
3858 if (!bss_conf->he_support ||
3859 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)
3860 return false;
3861
3862 if (rtwdev->chip->chip_id == RTL8852C &&
3863 rtw89_sta_link_has_su_mu_4xhe08(link_sta) &&
3864 !rtw89_sta_link_has_er_su_4xhe08(link_sta))
3865 return false;
3866
3867 return true;
3868 }
3869
rtw89_core_sta_link_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3870 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
3871 struct rtw89_vif_link *rtwvif_link,
3872 struct rtw89_sta_link *rtwsta_link)
3873 {
3874 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3875 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3876 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
3877 rtwsta_link);
3878 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
3879 rtwvif_link->chanctx_idx);
3880 struct ieee80211_link_sta *link_sta;
3881 int ret;
3882
3883 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3884 if (sta->tdls) {
3885 rcu_read_lock();
3886
3887 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3888 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam,
3889 link_sta->addr);
3890 if (ret) {
3891 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
3892 rcu_read_unlock();
3893 return ret;
3894 }
3895
3896 rcu_read_unlock();
3897 }
3898
3899 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam);
3900 if (ret) {
3901 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
3902 return ret;
3903 }
3904 }
3905
3906 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3907 if (ret) {
3908 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3909 return ret;
3910 }
3911
3912 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false);
3913 if (ret) {
3914 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3915 return ret;
3916 }
3917
3918 /* update cam aid mac_id net_type */
3919 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3920 if (ret) {
3921 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3922 return ret;
3923 }
3924
3925 rtw89_phy_ra_assoc(rtwdev, rtwsta_link);
3926 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
3927 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false);
3928
3929 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3930 struct ieee80211_bss_conf *bss_conf;
3931
3932 rcu_read_lock();
3933
3934 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
3935 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3936 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta);
3937
3938 rcu_read_unlock();
3939
3940 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3941 BTC_ROLE_MSTS_STA_CONN_END);
3942 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan);
3943 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link);
3944
3945 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id);
3946 if (ret) {
3947 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
3948 return ret;
3949 }
3950
3951 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
3952 }
3953
3954 rtw89_assoc_link_set(rtwsta_link);
3955 return ret;
3956 }
3957
rtw89_core_sta_link_remove(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3958 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
3959 struct rtw89_vif_link *rtwvif_link,
3960 struct rtw89_sta_link *rtwsta_link)
3961 {
3962 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3963 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3964 int ret;
3965
3966 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3967 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false);
3968 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3969 BTC_ROLE_MSTS_STA_DIS_CONN);
3970 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3971 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
3972 RTW89_ROLE_REMOVE);
3973 if (ret) {
3974 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3975 return ret;
3976 }
3977 }
3978
3979 return 0;
3980 }
3981
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)3982 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3983 struct ieee80211_sta *sta,
3984 struct cfg80211_tid_cfg *tid_conf)
3985 {
3986 struct ieee80211_txq *txq;
3987 struct rtw89_txq *rtwtxq;
3988 u32 mask = tid_conf->mask;
3989 u8 tids = tid_conf->tids;
3990 int tids_nbit = BITS_PER_BYTE;
3991 int i;
3992
3993 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
3994 if (!tids)
3995 break;
3996
3997 if (!(tids & BIT(0)))
3998 continue;
3999
4000 txq = sta->txq[i];
4001 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4002
4003 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
4004 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
4005 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4006 } else {
4007 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
4008 ieee80211_stop_tx_ba_session(sta, txq->tid);
4009 spin_lock_bh(&rtwdev->ba_lock);
4010 list_del_init(&rtwtxq->list);
4011 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4012 spin_unlock_bh(&rtwdev->ba_lock);
4013 }
4014 }
4015
4016 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
4017 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
4018 sta->max_amsdu_subframes = 0;
4019 else
4020 sta->max_amsdu_subframes = 1;
4021 }
4022 }
4023 }
4024
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)4025 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
4026 struct ieee80211_sta *sta,
4027 struct cfg80211_tid_config *tid_config)
4028 {
4029 int i;
4030
4031 for (i = 0; i < tid_config->n_tid_conf; i++)
4032 _rtw89_core_set_tid_config(rtwdev, sta,
4033 &tid_config->tid_conf[i]);
4034 }
4035
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)4036 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
4037 struct ieee80211_sta_ht_cap *ht_cap)
4038 {
4039 static const __le16 highest[RF_PATH_MAX] = {
4040 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
4041 };
4042 struct rtw89_hal *hal = &rtwdev->hal;
4043 u8 nss = hal->rx_nss;
4044 int i;
4045
4046 ht_cap->ht_supported = true;
4047 ht_cap->cap = 0;
4048 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
4049 IEEE80211_HT_CAP_MAX_AMSDU |
4050 IEEE80211_HT_CAP_TX_STBC |
4051 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
4052 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
4053 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4054 IEEE80211_HT_CAP_DSSSCCK40 |
4055 IEEE80211_HT_CAP_SGI_40;
4056 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
4057 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
4058 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
4059 for (i = 0; i < nss; i++)
4060 ht_cap->mcs.rx_mask[i] = 0xFF;
4061 ht_cap->mcs.rx_mask[4] = 0x01;
4062 ht_cap->mcs.rx_highest = highest[nss - 1];
4063 }
4064
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)4065 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
4066 struct ieee80211_sta_vht_cap *vht_cap)
4067 {
4068 static const __le16 highest_bw80[RF_PATH_MAX] = {
4069 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
4070 };
4071 static const __le16 highest_bw160[RF_PATH_MAX] = {
4072 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
4073 };
4074 const struct rtw89_chip_info *chip = rtwdev->chip;
4075 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
4076 highest_bw160 : highest_bw80;
4077 struct rtw89_hal *hal = &rtwdev->hal;
4078 u16 tx_mcs_map = 0, rx_mcs_map = 0;
4079 u8 sts_cap = 3;
4080 int i;
4081
4082 for (i = 0; i < 8; i++) {
4083 if (i < hal->tx_nss)
4084 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
4085 else
4086 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
4087 if (i < hal->rx_nss)
4088 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
4089 else
4090 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
4091 }
4092
4093 vht_cap->vht_supported = true;
4094 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
4095 IEEE80211_VHT_CAP_SHORT_GI_80 |
4096 IEEE80211_VHT_CAP_RXSTBC_1 |
4097 IEEE80211_VHT_CAP_HTC_VHT |
4098 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
4099 0;
4100 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
4101 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
4102 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
4103 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
4104 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
4105 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4106 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
4107 IEEE80211_VHT_CAP_SHORT_GI_160;
4108 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
4109 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
4110 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
4111 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
4112
4113 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
4114 vht_cap->vht_mcs.tx_highest |=
4115 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
4116 }
4117
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)4118 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
4119 enum nl80211_band band,
4120 enum nl80211_iftype iftype,
4121 struct ieee80211_sband_iftype_data *iftype_data)
4122 {
4123 const struct rtw89_chip_info *chip = rtwdev->chip;
4124 struct rtw89_hal *hal = &rtwdev->hal;
4125 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
4126 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
4127 struct ieee80211_sta_he_cap *he_cap;
4128 int nss = hal->rx_nss;
4129 u8 *mac_cap_info;
4130 u8 *phy_cap_info;
4131 u16 mcs_map = 0;
4132 int i;
4133
4134 for (i = 0; i < 8; i++) {
4135 if (i < nss)
4136 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
4137 else
4138 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
4139 }
4140
4141 he_cap = &iftype_data->he_cap;
4142 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
4143 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
4144
4145 he_cap->has_he = true;
4146 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
4147 if (iftype == NL80211_IFTYPE_STATION)
4148 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
4149 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
4150 IEEE80211_HE_MAC_CAP2_BSR;
4151 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
4152 if (iftype == NL80211_IFTYPE_AP)
4153 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
4154 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
4155 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
4156 if (iftype == NL80211_IFTYPE_STATION)
4157 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
4158 if (band == NL80211_BAND_2GHZ) {
4159 phy_cap_info[0] =
4160 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
4161 } else {
4162 phy_cap_info[0] =
4163 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
4164 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4165 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
4166 }
4167 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
4168 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
4169 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
4170 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
4171 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
4172 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
4173 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
4174 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
4175 if (iftype == NL80211_IFTYPE_STATION)
4176 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
4177 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
4178 if (iftype == NL80211_IFTYPE_AP)
4179 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
4180 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
4181 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
4182 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4183 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
4184 phy_cap_info[5] = no_ng16 ? 0 :
4185 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
4186 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
4187 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
4188 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
4189 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
4190 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
4191 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
4192 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
4193 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
4194 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
4195 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
4196 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
4197 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4198 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
4199 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
4200 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
4201 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
4202 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
4203 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
4204 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
4205 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
4206 if (iftype == NL80211_IFTYPE_STATION)
4207 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
4208 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
4209 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
4210 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
4211 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
4212 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
4213 }
4214
4215 if (band == NL80211_BAND_6GHZ) {
4216 __le16 capa;
4217
4218 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
4219 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
4220 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
4221 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
4222 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
4223 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
4224 iftype_data->he_6ghz_capa.capa = capa;
4225 }
4226 }
4227
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)4228 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
4229 enum nl80211_band band,
4230 enum nl80211_iftype iftype,
4231 struct ieee80211_sband_iftype_data *iftype_data)
4232 {
4233 const struct rtw89_chip_info *chip = rtwdev->chip;
4234 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
4235 struct ieee80211_eht_mcs_nss_supp *eht_nss;
4236 struct ieee80211_sta_eht_cap *eht_cap;
4237 struct rtw89_hal *hal = &rtwdev->hal;
4238 bool support_mcs_12_13 = true;
4239 bool support_320mhz = false;
4240 u8 val, val_mcs13;
4241 int sts = 8;
4242
4243 if (chip->chip_gen == RTW89_CHIP_AX)
4244 return;
4245
4246 if (hal->no_mcs_12_13)
4247 support_mcs_12_13 = false;
4248
4249 if (band == NL80211_BAND_6GHZ &&
4250 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
4251 support_320mhz = true;
4252
4253 eht_cap = &iftype_data->eht_cap;
4254 eht_cap_elem = &eht_cap->eht_cap_elem;
4255 eht_nss = &eht_cap->eht_mcs_nss_supp;
4256
4257 eht_cap->has_eht = true;
4258
4259 eht_cap_elem->mac_cap_info[0] =
4260 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
4261 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
4262 eht_cap_elem->mac_cap_info[1] = 0;
4263
4264 eht_cap_elem->phy_cap_info[0] =
4265 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
4266 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
4267 if (support_320mhz)
4268 eht_cap_elem->phy_cap_info[0] |=
4269 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
4270
4271 eht_cap_elem->phy_cap_info[0] |=
4272 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
4273 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
4274 eht_cap_elem->phy_cap_info[1] =
4275 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
4276 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
4277 u8_encode_bits(sts - 1,
4278 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
4279 if (support_320mhz)
4280 eht_cap_elem->phy_cap_info[1] |=
4281 u8_encode_bits(sts - 1,
4282 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
4283
4284 eht_cap_elem->phy_cap_info[2] = 0;
4285
4286 eht_cap_elem->phy_cap_info[3] =
4287 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
4288 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
4289 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
4290 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
4291
4292 eht_cap_elem->phy_cap_info[4] =
4293 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
4294 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
4295
4296 eht_cap_elem->phy_cap_info[5] =
4297 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
4298 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
4299
4300 eht_cap_elem->phy_cap_info[6] = 0;
4301 eht_cap_elem->phy_cap_info[7] = 0;
4302 eht_cap_elem->phy_cap_info[8] = 0;
4303
4304 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
4305 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
4306 val_mcs13 = support_mcs_12_13 ? val : 0;
4307
4308 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
4309 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
4310 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13;
4311 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
4312 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
4313 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13;
4314 if (support_320mhz) {
4315 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
4316 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
4317 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13;
4318 }
4319 }
4320
4321 #define RTW89_SBAND_IFTYPES_NR 2
4322
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)4323 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
4324 enum nl80211_band band,
4325 struct ieee80211_supported_band *sband)
4326 {
4327 struct ieee80211_sband_iftype_data *iftype_data;
4328 enum nl80211_iftype iftype;
4329 int idx = 0;
4330
4331 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL);
4332 if (!iftype_data)
4333 return;
4334
4335 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
4336 switch (iftype) {
4337 case NL80211_IFTYPE_STATION:
4338 case NL80211_IFTYPE_AP:
4339 break;
4340 default:
4341 continue;
4342 }
4343
4344 if (idx >= RTW89_SBAND_IFTYPES_NR) {
4345 rtw89_warn(rtwdev, "run out of iftype_data\n");
4346 break;
4347 }
4348
4349 iftype_data[idx].types_mask = BIT(iftype);
4350
4351 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
4352 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
4353
4354 idx++;
4355 }
4356
4357 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
4358 }
4359
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)4360 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
4361 {
4362 struct ieee80211_hw *hw = rtwdev->hw;
4363 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL;
4364 struct ieee80211_supported_band *sband_6ghz = NULL;
4365 u32 size = sizeof(struct ieee80211_supported_band);
4366 u8 support_bands = rtwdev->chip->support_bands;
4367
4368 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
4369 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL);
4370 if (!sband_2ghz)
4371 goto err;
4372 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap);
4373 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz);
4374 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz;
4375 }
4376
4377 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
4378 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL);
4379 if (!sband_5ghz)
4380 goto err;
4381 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap);
4382 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap);
4383 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz);
4384 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz;
4385 }
4386
4387 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
4388 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL);
4389 if (!sband_6ghz)
4390 goto err;
4391 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz);
4392 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz;
4393 }
4394
4395 return 0;
4396
4397 err:
4398 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4399 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4400 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4401 if (sband_2ghz)
4402 kfree((__force void *)sband_2ghz->iftype_data);
4403 if (sband_5ghz)
4404 kfree((__force void *)sband_5ghz->iftype_data);
4405 if (sband_6ghz)
4406 kfree((__force void *)sband_6ghz->iftype_data);
4407 kfree(sband_2ghz);
4408 kfree(sband_5ghz);
4409 kfree(sband_6ghz);
4410 return -ENOMEM;
4411 }
4412
rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)4413 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
4414 {
4415 struct ieee80211_hw *hw = rtwdev->hw;
4416
4417 if (hw->wiphy->bands[NL80211_BAND_2GHZ])
4418 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
4419 if (hw->wiphy->bands[NL80211_BAND_5GHZ])
4420 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
4421 if (hw->wiphy->bands[NL80211_BAND_6GHZ])
4422 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
4423 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
4424 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
4425 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
4426 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4427 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4428 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4429 }
4430
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)4431 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
4432 {
4433 int i;
4434
4435 for (i = 0; i < RTW89_PHY_MAX; i++)
4436 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
4437 for (i = 0; i < RTW89_PHY_MAX; i++)
4438 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
4439 }
4440
rtw89_core_update_beacon_work(struct work_struct * work)4441 void rtw89_core_update_beacon_work(struct work_struct *work)
4442 {
4443 struct rtw89_dev *rtwdev;
4444 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link,
4445 update_beacon_work);
4446
4447 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
4448 return;
4449
4450 rtwdev = rtwvif_link->rtwvif->rtwdev;
4451
4452 mutex_lock(&rtwdev->mutex);
4453 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
4454 mutex_unlock(&rtwdev->mutex);
4455 }
4456
rtw89_wait_for_cond(struct rtw89_wait_info * wait,unsigned int cond)4457 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
4458 {
4459 struct completion *cmpl = &wait->completion;
4460 unsigned long time_left;
4461 unsigned int cur;
4462
4463 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
4464 if (cur != RTW89_WAIT_COND_IDLE)
4465 return -EBUSY;
4466
4467 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
4468 if (time_left == 0) {
4469 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4470 return -ETIMEDOUT;
4471 }
4472
4473 if (wait->data.err)
4474 return -EFAULT;
4475
4476 return 0;
4477 }
4478
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)4479 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
4480 const struct rtw89_completion_data *data)
4481 {
4482 unsigned int cur;
4483
4484 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
4485 if (cur != cond)
4486 return;
4487
4488 wait->data = *data;
4489 complete(&wait->completion);
4490 }
4491
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)4492 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event)
4493 {
4494 u16 bt_req_len;
4495
4496 switch (event) {
4497 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
4498 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0);
4499 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4500 "coex updates BT req len to %d TU\n", bt_req_len);
4501 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
4502 break;
4503 default:
4504 if (event < NUM_OF_RTW89_BTC_HMSG)
4505 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4506 "unhandled BTC HMSG event: %d\n", event);
4507 else
4508 rtw89_warn(rtwdev,
4509 "unrecognized BTC HMSG event: %d\n", event);
4510 break;
4511 }
4512 }
4513
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)4514 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
4515 {
4516 const struct dmi_system_id *match;
4517 enum rtw89_quirks quirk;
4518
4519 if (!quirks)
4520 return;
4521
4522 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
4523 quirk = (uintptr_t)match->driver_data;
4524 if (quirk >= NUM_OF_RTW89_QUIRKS)
4525 continue;
4526
4527 set_bit(quirk, rtwdev->quirks);
4528 }
4529 }
4530 EXPORT_SYMBOL(rtw89_check_quirks);
4531
rtw89_core_start(struct rtw89_dev * rtwdev)4532 int rtw89_core_start(struct rtw89_dev *rtwdev)
4533 {
4534 int ret;
4535
4536 ret = rtw89_mac_init(rtwdev);
4537 if (ret) {
4538 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
4539 return ret;
4540 }
4541
4542 rtw89_btc_ntfy_poweron(rtwdev);
4543
4544 /* efuse process */
4545
4546 /* pre-config BB/RF, BB reset/RFC reset */
4547 ret = rtw89_chip_reset_bb_rf(rtwdev);
4548 if (ret)
4549 return ret;
4550
4551 rtw89_phy_init_bb_reg(rtwdev);
4552 rtw89_chip_bb_postinit(rtwdev);
4553 rtw89_phy_init_rf_reg(rtwdev, false);
4554
4555 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
4556
4557 rtw89_phy_dm_init(rtwdev);
4558
4559 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
4560 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true);
4561 rtw89_mac_update_rts_threshold(rtwdev);
4562
4563 rtw89_tas_reset(rtwdev);
4564
4565 ret = rtw89_hci_start(rtwdev);
4566 if (ret) {
4567 rtw89_err(rtwdev, "failed to start hci\n");
4568 return ret;
4569 }
4570
4571 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
4572 RTW89_TRACK_WORK_PERIOD);
4573
4574 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4575
4576 rtw89_chip_rfk_init_late(rtwdev);
4577 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
4578 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
4579 rtw89_fw_h2c_init_ba_cam(rtwdev);
4580
4581 return 0;
4582 }
4583
rtw89_core_stop(struct rtw89_dev * rtwdev)4584 void rtw89_core_stop(struct rtw89_dev *rtwdev)
4585 {
4586 struct rtw89_btc *btc = &rtwdev->btc;
4587
4588 /* Prvent to stop twice; enter_ips and ops_stop */
4589 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4590 return;
4591
4592 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
4593
4594 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4595
4596 mutex_unlock(&rtwdev->mutex);
4597
4598 cancel_work_sync(&rtwdev->c2h_work);
4599 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work);
4600 cancel_work_sync(&btc->eapol_notify_work);
4601 cancel_work_sync(&btc->arp_notify_work);
4602 cancel_work_sync(&btc->dhcp_notify_work);
4603 cancel_work_sync(&btc->icmp_notify_work);
4604 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
4605 cancel_delayed_work_sync(&rtwdev->track_work);
4606 cancel_delayed_work_sync(&rtwdev->chanctx_work);
4607 cancel_delayed_work_sync(&rtwdev->coex_act1_work);
4608 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work);
4609 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
4610 cancel_delayed_work_sync(&rtwdev->cfo_track_work);
4611 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
4612 cancel_delayed_work_sync(&rtwdev->antdiv_work);
4613
4614 mutex_lock(&rtwdev->mutex);
4615
4616 rtw89_btc_ntfy_poweroff(rtwdev);
4617 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4618 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4619 rtw89_hci_stop(rtwdev);
4620 rtw89_hci_deinit(rtwdev);
4621 rtw89_mac_pwr_off(rtwdev);
4622 rtw89_hci_reset(rtwdev);
4623 }
4624
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)4625 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
4626 {
4627 const struct rtw89_chip_info *chip = rtwdev->chip;
4628 u8 mac_id_num;
4629 u8 mac_id;
4630
4631 if (rtwdev->support_mlo)
4632 mac_id_num = chip->support_macid_num / chip->support_link_num;
4633 else
4634 mac_id_num = chip->support_macid_num;
4635
4636 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
4637 if (mac_id == mac_id_num)
4638 return RTW89_MAX_MAC_ID_NUM;
4639
4640 set_bit(mac_id, rtwdev->mac_id_map);
4641 return mac_id;
4642 }
4643
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)4644 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
4645 {
4646 clear_bit(mac_id, rtwdev->mac_id_map);
4647 }
4648
rtw89_init_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 mac_id,u8 port)4649 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4650 u8 mac_id, u8 port)
4651 {
4652 const struct rtw89_chip_info *chip = rtwdev->chip;
4653 u8 support_link_num = chip->support_link_num;
4654 u8 support_mld_num = 0;
4655 unsigned int link_id;
4656 u8 index;
4657
4658 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4659 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4660 rtwvif->links[link_id] = NULL;
4661
4662 rtwvif->rtwdev = rtwdev;
4663
4664 if (rtwdev->support_mlo) {
4665 rtwvif->links_inst_valid_num = support_link_num;
4666 support_mld_num = chip->support_macid_num / support_link_num;
4667 } else {
4668 rtwvif->links_inst_valid_num = 1;
4669 }
4670
4671 for (index = 0; index < rtwvif->links_inst_valid_num; index++) {
4672 struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
4673
4674 inst->rtwvif = rtwvif;
4675 inst->mac_id = mac_id + index * support_mld_num;
4676 inst->mac_idx = RTW89_MAC_0 + index;
4677 inst->phy_idx = RTW89_PHY_0 + index;
4678
4679 /* multi-link use the same port id on different HW bands */
4680 inst->port = port;
4681 }
4682 }
4683
rtw89_init_sta(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta,u8 mac_id)4684 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4685 struct rtw89_sta *rtwsta, u8 mac_id)
4686 {
4687 const struct rtw89_chip_info *chip = rtwdev->chip;
4688 u8 support_link_num = chip->support_link_num;
4689 u8 support_mld_num = 0;
4690 unsigned int link_id;
4691 u8 index;
4692
4693 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4694 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4695 rtwsta->links[link_id] = NULL;
4696
4697 rtwsta->rtwdev = rtwdev;
4698 rtwsta->rtwvif = rtwvif;
4699
4700 if (rtwdev->support_mlo) {
4701 rtwsta->links_inst_valid_num = support_link_num;
4702 support_mld_num = chip->support_macid_num / support_link_num;
4703 } else {
4704 rtwsta->links_inst_valid_num = 1;
4705 }
4706
4707 for (index = 0; index < rtwsta->links_inst_valid_num; index++) {
4708 struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
4709
4710 inst->rtwvif_link = &rtwvif->links_inst[index];
4711
4712 inst->rtwsta = rtwsta;
4713 inst->mac_id = mac_id + index * support_mld_num;
4714 }
4715 }
4716
rtw89_vif_set_link(struct rtw89_vif * rtwvif,unsigned int link_id)4717 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
4718 unsigned int link_id)
4719 {
4720 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4721 u8 index;
4722 int ret;
4723
4724 if (rtwvif_link)
4725 return rtwvif_link;
4726
4727 index = find_first_zero_bit(rtwvif->links_inst_map,
4728 rtwvif->links_inst_valid_num);
4729 if (index == rtwvif->links_inst_valid_num) {
4730 ret = -EBUSY;
4731 goto err;
4732 }
4733
4734 rtwvif_link = &rtwvif->links_inst[index];
4735 rtwvif_link->link_id = link_id;
4736
4737 set_bit(index, rtwvif->links_inst_map);
4738 rtwvif->links[link_id] = rtwvif_link;
4739 return rtwvif_link;
4740
4741 err:
4742 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n",
4743 link_id, ret);
4744 return NULL;
4745 }
4746
rtw89_vif_unset_link(struct rtw89_vif * rtwvif,unsigned int link_id)4747 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id)
4748 {
4749 struct rtw89_vif_link **container = &rtwvif->links[link_id];
4750 struct rtw89_vif_link *link = *container;
4751 u8 index;
4752
4753 if (!link)
4754 return;
4755
4756 index = rtw89_vif_link_inst_get_index(link);
4757 clear_bit(index, rtwvif->links_inst_map);
4758 *container = NULL;
4759 }
4760
rtw89_sta_set_link(struct rtw89_sta * rtwsta,unsigned int link_id)4761 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
4762 unsigned int link_id)
4763 {
4764 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4765 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4766 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id];
4767 u8 index;
4768 int ret;
4769
4770 if (rtwsta_link)
4771 return rtwsta_link;
4772
4773 if (!rtwvif_link) {
4774 ret = -ENOLINK;
4775 goto err;
4776 }
4777
4778 index = rtw89_vif_link_inst_get_index(rtwvif_link);
4779 if (test_bit(index, rtwsta->links_inst_map)) {
4780 ret = -EBUSY;
4781 goto err;
4782 }
4783
4784 rtwsta_link = &rtwsta->links_inst[index];
4785 rtwsta_link->link_id = link_id;
4786
4787 set_bit(index, rtwsta->links_inst_map);
4788 rtwsta->links[link_id] = rtwsta_link;
4789 return rtwsta_link;
4790
4791 err:
4792 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n",
4793 link_id, ret);
4794 return NULL;
4795 }
4796
rtw89_sta_unset_link(struct rtw89_sta * rtwsta,unsigned int link_id)4797 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id)
4798 {
4799 struct rtw89_sta_link **container = &rtwsta->links[link_id];
4800 struct rtw89_sta_link *link = *container;
4801 u8 index;
4802
4803 if (!link)
4804 return;
4805
4806 index = rtw89_sta_link_inst_get_index(link);
4807 clear_bit(index, rtwsta->links_inst_map);
4808 *container = NULL;
4809 }
4810
rtw89_core_init(struct rtw89_dev * rtwdev)4811 int rtw89_core_init(struct rtw89_dev *rtwdev)
4812 {
4813 struct rtw89_btc *btc = &rtwdev->btc;
4814 u8 band;
4815
4816 INIT_LIST_HEAD(&rtwdev->ba_list);
4817 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
4818 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
4819 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
4820 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
4821 if (!(rtwdev->chip->support_bands & BIT(band)))
4822 continue;
4823 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
4824 }
4825 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
4826 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
4827 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
4828 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work);
4829 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work);
4830 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
4831 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
4832 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
4833 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
4834 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
4835 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
4836 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
4837 if (!rtwdev->txq_wq)
4838 return -ENOMEM;
4839 spin_lock_init(&rtwdev->ba_lock);
4840 spin_lock_init(&rtwdev->rpwm_lock);
4841 mutex_init(&rtwdev->mutex);
4842 mutex_init(&rtwdev->rf_mutex);
4843 rtwdev->total_sta_assoc = 0;
4844
4845 rtw89_init_wait(&rtwdev->mcc.wait);
4846 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
4847 rtw89_init_wait(&rtwdev->wow.wait);
4848 rtw89_init_wait(&rtwdev->mac.ps_wait);
4849
4850 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
4851 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
4852 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
4853 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
4854
4855 skb_queue_head_init(&rtwdev->c2h_queue);
4856 rtw89_core_ppdu_sts_init(rtwdev);
4857 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
4858
4859 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
4860 rtwdev->dbcc_en = false;
4861 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
4862 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
4863
4864 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4865 rtwdev->dbcc_en = true;
4866 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
4867 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF;
4868 }
4869
4870 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
4871 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
4872 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
4873 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
4874
4875 init_completion(&rtwdev->fw.req.completion);
4876 init_completion(&rtwdev->rfk_wait.completion);
4877
4878 schedule_work(&rtwdev->load_firmware_work);
4879
4880 rtw89_ser_init(rtwdev);
4881 rtw89_entity_init(rtwdev);
4882 rtw89_tas_init(rtwdev);
4883 rtw89_phy_ant_gain_init(rtwdev);
4884
4885 return 0;
4886 }
4887 EXPORT_SYMBOL(rtw89_core_init);
4888
rtw89_core_deinit(struct rtw89_dev * rtwdev)4889 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
4890 {
4891 rtw89_ser_deinit(rtwdev);
4892 rtw89_unload_firmware(rtwdev);
4893 rtw89_fw_free_all_early_h2c(rtwdev);
4894
4895 destroy_workqueue(rtwdev->txq_wq);
4896 mutex_destroy(&rtwdev->rf_mutex);
4897 mutex_destroy(&rtwdev->mutex);
4898 }
4899 EXPORT_SYMBOL(rtw89_core_deinit);
4900
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const u8 * mac_addr,bool hw_scan)4901 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4902 const u8 *mac_addr, bool hw_scan)
4903 {
4904 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4905 rtwvif_link->chanctx_idx);
4906
4907 rtwdev->scanning = true;
4908 rtw89_leave_lps(rtwdev);
4909 if (hw_scan)
4910 rtw89_leave_ips_by_hwflags(rtwdev);
4911
4912 ether_addr_copy(rtwvif_link->mac_addr, mac_addr);
4913 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type);
4914 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true);
4915 rtw89_hci_recalc_int_mit(rtwdev);
4916 rtw89_phy_config_edcca(rtwdev, true);
4917
4918 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr);
4919 }
4920
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool hw_scan)4921 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
4922 struct rtw89_vif_link *rtwvif_link, bool hw_scan)
4923 {
4924 struct ieee80211_bss_conf *bss_conf;
4925
4926 if (!rtwvif_link)
4927 return;
4928
4929 rcu_read_lock();
4930
4931 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
4932 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr);
4933
4934 rcu_read_unlock();
4935
4936 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
4937
4938 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
4939 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx);
4940 rtw89_phy_config_edcca(rtwdev, false);
4941
4942 rtwdev->scanning = false;
4943 rtwdev->dig.bypass_dig = true;
4944 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
4945 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
4946 }
4947
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)4948 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
4949 {
4950 const struct rtw89_chip_info *chip = rtwdev->chip;
4951 int ret;
4952 u8 val;
4953 u8 cv;
4954
4955 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
4956 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
4957 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
4958 cv = CHIP_CAV;
4959 else
4960 cv = CHIP_CBV;
4961 }
4962
4963 rtwdev->hal.cv = cv;
4964
4965 if (rtw89_is_rtl885xb(rtwdev)) {
4966 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
4967 if (ret)
4968 return;
4969
4970 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
4971 }
4972 }
4973
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)4974 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
4975 {
4976 const struct rtw89_chip_info *chip = rtwdev->chip;
4977
4978 rtwdev->hal.support_cckpd =
4979 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
4980 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
4981 rtwdev->hal.support_igi =
4982 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
4983
4984 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks))
4985 rtwdev->hal.thermal_prot_th = chip->thermal_th[1];
4986 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks))
4987 rtwdev->hal.thermal_prot_th = chip->thermal_th[0];
4988 else
4989 rtwdev->hal.thermal_prot_th = 0;
4990 }
4991
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)4992 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
4993 {
4994 const struct rtw89_chip_info *chip = rtwdev->chip;
4995 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
4996 struct rtw89_efuse *efuse = &rtwdev->efuse;
4997 const struct rtw89_rfe_parms *sel;
4998 u8 rfe_type = efuse->rfe_type;
4999
5000 if (!conf) {
5001 sel = chip->dflt_parms;
5002 goto out;
5003 }
5004
5005 while (conf->rfe_parms) {
5006 if (rfe_type == conf->rfe_type) {
5007 sel = conf->rfe_parms;
5008 goto out;
5009 }
5010 conf++;
5011 }
5012
5013 sel = chip->dflt_parms;
5014
5015 out:
5016 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
5017 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
5018 }
5019
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)5020 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
5021 {
5022 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5023 int ret;
5024
5025 ret = rtw89_mac_partial_init(rtwdev, false);
5026 if (ret)
5027 return ret;
5028
5029 ret = mac->parse_efuse_map(rtwdev);
5030 if (ret)
5031 return ret;
5032
5033 ret = mac->parse_phycap_map(rtwdev);
5034 if (ret)
5035 return ret;
5036
5037 ret = rtw89_mac_setup_phycap(rtwdev);
5038 if (ret)
5039 return ret;
5040
5041 rtw89_core_setup_phycap(rtwdev);
5042
5043 rtw89_hci_mac_pre_deinit(rtwdev);
5044
5045 rtw89_mac_pwr_off(rtwdev);
5046
5047 return 0;
5048 }
5049
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)5050 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
5051 {
5052 rtw89_chip_fem_setup(rtwdev);
5053
5054 return 0;
5055 }
5056
rtw89_chip_has_rfkill(struct rtw89_dev * rtwdev)5057 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev)
5058 {
5059 return !!rtwdev->chip->rfkill_init;
5060 }
5061
rtw89_core_rfkill_init(struct rtw89_dev * rtwdev)5062 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev)
5063 {
5064 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init;
5065
5066 rtw89_write16_mask(rtwdev, regs->pinmux.addr,
5067 regs->pinmux.mask, regs->pinmux.data);
5068 rtw89_write16_mask(rtwdev, regs->mode.addr,
5069 regs->mode.mask, regs->mode.data);
5070 }
5071
rtw89_core_rfkill_get(struct rtw89_dev * rtwdev)5072 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev)
5073 {
5074 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get;
5075
5076 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask);
5077 }
5078
rtw89_rfkill_polling_init(struct rtw89_dev * rtwdev)5079 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev)
5080 {
5081 if (!rtw89_chip_has_rfkill(rtwdev))
5082 return;
5083
5084 rtw89_core_rfkill_init(rtwdev);
5085 rtw89_core_rfkill_poll(rtwdev, true);
5086 wiphy_rfkill_start_polling(rtwdev->hw->wiphy);
5087 }
5088
rtw89_rfkill_polling_deinit(struct rtw89_dev * rtwdev)5089 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev)
5090 {
5091 if (!rtw89_chip_has_rfkill(rtwdev))
5092 return;
5093
5094 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy);
5095 }
5096
rtw89_core_rfkill_poll(struct rtw89_dev * rtwdev,bool force)5097 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force)
5098 {
5099 bool prev, blocked;
5100
5101 if (!rtw89_chip_has_rfkill(rtwdev))
5102 return;
5103
5104 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
5105 blocked = rtw89_core_rfkill_get(rtwdev);
5106
5107 if (!force && prev == blocked)
5108 return;
5109
5110 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n",
5111 blocked ? "disable" : "enable");
5112
5113 if (blocked)
5114 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
5115 else
5116 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
5117
5118 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked);
5119 }
5120
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)5121 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
5122 {
5123 int ret;
5124
5125 rtw89_read_chip_ver(rtwdev);
5126
5127 ret = rtw89_wait_firmware_completion(rtwdev);
5128 if (ret) {
5129 rtw89_err(rtwdev, "failed to wait firmware completion\n");
5130 return ret;
5131 }
5132
5133 ret = rtw89_fw_recognize(rtwdev);
5134 if (ret) {
5135 rtw89_err(rtwdev, "failed to recognize firmware\n");
5136 return ret;
5137 }
5138
5139 ret = rtw89_chip_efuse_info_setup(rtwdev);
5140 if (ret)
5141 return ret;
5142
5143 ret = rtw89_fw_recognize_elements(rtwdev);
5144 if (ret) {
5145 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
5146 return ret;
5147 }
5148
5149 ret = rtw89_chip_board_info_setup(rtwdev);
5150 if (ret)
5151 return ret;
5152
5153 rtw89_core_setup_rfe_parms(rtwdev);
5154 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
5155
5156 return 0;
5157 }
5158 EXPORT_SYMBOL(rtw89_chip_info_setup);
5159
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5160 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5161 struct rtw89_vif_link *rtwvif_link)
5162 {
5163 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5164 const struct rtw89_chip_info *chip = rtwdev->chip;
5165 struct ieee80211_bss_conf *bss_conf;
5166
5167 rcu_read_lock();
5168
5169 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
5170 if (!bss_conf->he_support || !vif->cfg.assoc) {
5171 rcu_read_unlock();
5172 return;
5173 }
5174
5175 rcu_read_unlock();
5176
5177 if (chip->ops->set_txpwr_ul_tb_offset)
5178 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx);
5179 }
5180
rtw89_core_register_hw(struct rtw89_dev * rtwdev)5181 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
5182 {
5183 const struct rtw89_chip_info *chip = rtwdev->chip;
5184 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1;
5185 struct ieee80211_hw *hw = rtwdev->hw;
5186 struct rtw89_efuse *efuse = &rtwdev->efuse;
5187 struct rtw89_hal *hal = &rtwdev->hal;
5188 int ret;
5189 int tx_headroom = IEEE80211_HT_CTL_LEN;
5190
5191 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n);
5192 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n);
5193 hw->txq_data_size = sizeof(struct rtw89_txq);
5194 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
5195
5196 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
5197
5198 hw->extra_tx_headroom = tx_headroom;
5199 hw->queues = IEEE80211_NUM_ACS;
5200 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
5201 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
5202 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
5203
5204 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
5205 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
5206 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC;
5207
5208 ieee80211_hw_set(hw, SIGNAL_DBM);
5209 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5210 ieee80211_hw_set(hw, MFP_CAPABLE);
5211 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
5212 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5213 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
5214 ieee80211_hw_set(hw, TX_AMSDU);
5215 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
5216 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
5217 ieee80211_hw_set(hw, SUPPORTS_PS);
5218 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
5219 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
5220 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
5221 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
5222
5223 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5224 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
5225
5226 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
5227 ieee80211_hw_set(hw, CONNECTION_MONITOR);
5228
5229 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw))
5230 ieee80211_hw_set(hw, AP_LINK_PS);
5231
5232 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
5233 BIT(NL80211_IFTYPE_AP) |
5234 BIT(NL80211_IFTYPE_P2P_CLIENT) |
5235 BIT(NL80211_IFTYPE_P2P_GO);
5236
5237 if (hal->ant_diversity) {
5238 hw->wiphy->available_antennas_tx = 0x3;
5239 hw->wiphy->available_antennas_rx = 0x3;
5240 } else {
5241 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
5242 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
5243 }
5244
5245 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
5246 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
5247 WIPHY_FLAG_AP_UAPSD |
5248 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
5249
5250 if (!chip->support_rnr)
5251 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
5252
5253 if (chip->chip_gen == RTW89_CHIP_BE)
5254 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT;
5255
5256 if (rtwdev->support_mlo)
5257 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO;
5258
5259 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
5260
5261 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5262 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
5263
5264 #ifdef CONFIG_PM
5265 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
5266 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5267 #endif
5268
5269 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5270 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5271 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5272 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5273 hw->wiphy->max_remain_on_channel_duration = 1000;
5274
5275 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
5276 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
5277 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
5278
5279 ret = rtw89_core_set_supported_band(rtwdev);
5280 if (ret) {
5281 rtw89_err(rtwdev, "failed to set supported band\n");
5282 return ret;
5283 }
5284
5285 ret = rtw89_regd_setup(rtwdev);
5286 if (ret) {
5287 rtw89_err(rtwdev, "failed to set up regd\n");
5288 goto err_free_supported_band;
5289 }
5290
5291 hw->wiphy->sar_capa = &rtw89_sar_capa;
5292
5293 ret = ieee80211_register_hw(hw);
5294 if (ret) {
5295 rtw89_err(rtwdev, "failed to register hw\n");
5296 goto err_free_supported_band;
5297 }
5298
5299 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier);
5300 if (ret) {
5301 rtw89_err(rtwdev, "failed to init regd\n");
5302 goto err_unregister_hw;
5303 }
5304
5305 rtw89_rfkill_polling_init(rtwdev);
5306
5307 return 0;
5308
5309 err_unregister_hw:
5310 ieee80211_unregister_hw(hw);
5311 err_free_supported_band:
5312 rtw89_core_clr_supported_band(rtwdev);
5313
5314 return ret;
5315 }
5316
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)5317 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
5318 {
5319 struct ieee80211_hw *hw = rtwdev->hw;
5320
5321 rtw89_rfkill_polling_deinit(rtwdev);
5322 ieee80211_unregister_hw(hw);
5323 rtw89_core_clr_supported_band(rtwdev);
5324 }
5325
rtw89_core_register(struct rtw89_dev * rtwdev)5326 int rtw89_core_register(struct rtw89_dev *rtwdev)
5327 {
5328 int ret;
5329
5330 ret = rtw89_core_register_hw(rtwdev);
5331 if (ret) {
5332 rtw89_err(rtwdev, "failed to register core hw\n");
5333 return ret;
5334 }
5335
5336 rtw89_debugfs_init(rtwdev);
5337
5338 return 0;
5339 }
5340 EXPORT_SYMBOL(rtw89_core_register);
5341
rtw89_core_unregister(struct rtw89_dev * rtwdev)5342 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
5343 {
5344 rtw89_core_unregister_hw(rtwdev);
5345
5346 rtw89_debugfs_deinit(rtwdev);
5347 }
5348 EXPORT_SYMBOL(rtw89_core_unregister);
5349
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip,const struct rtw89_chip_variant * variant)5350 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5351 u32 bus_data_size,
5352 const struct rtw89_chip_info *chip,
5353 const struct rtw89_chip_variant *variant)
5354 {
5355 struct rtw89_fw_info early_fw = {};
5356 const struct firmware *firmware;
5357 struct ieee80211_hw *hw;
5358 struct rtw89_dev *rtwdev;
5359 struct ieee80211_ops *ops;
5360 u32 driver_data_size;
5361 int fw_format = -1;
5362 bool support_mlo;
5363 bool no_chanctx;
5364
5365 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
5366
5367 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
5368 if (!ops)
5369 goto err;
5370
5371 no_chanctx = chip->support_chanctx_num == 0 ||
5372 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
5373 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
5374
5375 if (no_chanctx) {
5376 ops->add_chanctx = ieee80211_emulate_add_chanctx;
5377 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
5378 ops->change_chanctx = ieee80211_emulate_change_chanctx;
5379 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
5380 ops->assign_vif_chanctx = NULL;
5381 ops->unassign_vif_chanctx = NULL;
5382 ops->remain_on_channel = NULL;
5383 ops->cancel_remain_on_channel = NULL;
5384 }
5385
5386 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
5387 hw = ieee80211_alloc_hw(driver_data_size, ops);
5388 if (!hw)
5389 goto err;
5390
5391 /* TODO: When driver MLO arch. is done, determine whether to support MLO
5392 * according to the following conditions.
5393 * 1. run with chanctx_ops
5394 * 2. chip->support_link_num != 0
5395 * 3. FW feature supports AP_LINK_PS
5396 */
5397 support_mlo = false;
5398
5399 hw->wiphy->iface_combinations = rtw89_iface_combs;
5400
5401 if (no_chanctx || chip->support_chanctx_num == 1)
5402 hw->wiphy->n_iface_combinations = 1;
5403 else
5404 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
5405
5406 rtwdev = hw->priv;
5407 rtwdev->hw = hw;
5408 rtwdev->dev = device;
5409 rtwdev->ops = ops;
5410 rtwdev->chip = chip;
5411 rtwdev->variant = variant;
5412 rtwdev->fw.req.firmware = firmware;
5413 rtwdev->fw.fw_format = fw_format;
5414 rtwdev->support_mlo = support_mlo;
5415
5416 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n",
5417 no_chanctx ? "without" : "with");
5418 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n",
5419 support_mlo ? "with" : "without");
5420
5421 return rtwdev;
5422
5423 err:
5424 kfree(ops);
5425 release_firmware(firmware);
5426 return NULL;
5427 }
5428 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
5429
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)5430 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
5431 {
5432 kfree(rtwdev->ops);
5433 kfree(rtwdev->rfe_data);
5434 release_firmware(rtwdev->fw.req.firmware);
5435 ieee80211_free_hw(rtwdev->hw);
5436 }
5437 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
5438
5439 MODULE_AUTHOR("Realtek Corporation");
5440 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
5441 MODULE_LICENSE("Dual BSD/GPL");
5442