1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright Fiona Klute <[email protected]> */
3
4 #include <linux/of_net.h>
5 #include "main.h"
6 #include "coex.h"
7 #include "debug.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rx.h"
12 #include "rtw8703b.h"
13 #include "rtw8703b_tables.h"
14 #include "rtw8723x.h"
15
16 #define BIT_MASK_TXQ_INIT (BIT(7))
17 #define WLAN_RL_VAL 0x3030
18 /* disable BAR */
19 #define WLAN_BAR_VAL 0x0201ffff
20 #define WLAN_PIFS_VAL 0
21 #define WLAN_RX_PKT_LIMIT 0x18
22 #define WLAN_SLOT_TIME 0x09
23 #define WLAN_SPEC_SIFS 0x100a
24 #define WLAN_MAX_AGG_NR 0x1f
25 #define WLAN_AMPDU_MAX_TIME 0x70
26
27 /* unit is 32us */
28 #define TBTT_PROHIBIT_SETUP_TIME 0x04
29 #define TBTT_PROHIBIT_HOLD_TIME 0x80
30 #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64
31
32 #define TRANS_SEQ_END \
33 0xFFFF, \
34 RTW_PWR_CUT_ALL_MSK, \
35 RTW_PWR_INTF_ALL_MSK, \
36 0, \
37 RTW_PWR_CMD_END, 0, 0
38
39 /* rssi in percentage % (dbm = % - 100) */
40 /* These are used to select simple signal quality levels, might need
41 * tweaking. Same for rf_para tables below.
42 */
43 static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30};
44 static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30};
45 static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} };
46
47 /* Actually decreasing wifi TX power/RX gain isn't implemented in
48 * rtw8703b, but hopefully adjusting the BT side helps.
49 */
50 static const struct coex_rf_para rf_para_tx_8703b[] = {
51 {0, 0, false, 7}, /* for normal */
52 {0, 10, false, 7}, /* for WL-CPT */
53 {1, 0, true, 4},
54 {1, 2, true, 4},
55 {1, 10, true, 4},
56 {1, 15, true, 4}
57 };
58
59 static const struct coex_rf_para rf_para_rx_8703b[] = {
60 {0, 0, false, 7}, /* for normal */
61 {0, 10, false, 7}, /* for WL-CPT */
62 {1, 0, true, 5},
63 {1, 2, true, 5},
64 {1, 10, true, 5},
65 {1, 15, true, 5}
66 };
67
68 static const u32 rtw8703b_ofdm_swing_table[] = {
69 0x0b40002d, /* 0, -15.0dB */
70 0x0c000030, /* 1, -14.5dB */
71 0x0cc00033, /* 2, -14.0dB */
72 0x0d800036, /* 3, -13.5dB */
73 0x0e400039, /* 4, -13.0dB */
74 0x0f00003c, /* 5, -12.5dB */
75 0x10000040, /* 6, -12.0dB */
76 0x11000044, /* 7, -11.5dB */
77 0x12000048, /* 8, -11.0dB */
78 0x1300004c, /* 9, -10.5dB */
79 0x14400051, /* 10, -10.0dB */
80 0x15800056, /* 11, -9.5dB */
81 0x16c0005b, /* 12, -9.0dB */
82 0x18000060, /* 13, -8.5dB */
83 0x19800066, /* 14, -8.0dB */
84 0x1b00006c, /* 15, -7.5dB */
85 0x1c800072, /* 16, -7.0dB */
86 0x1e400079, /* 17, -6.5dB */
87 0x20000080, /* 18, -6.0dB */
88 0x22000088, /* 19, -5.5dB */
89 0x24000090, /* 20, -5.0dB */
90 0x26000098, /* 21, -4.5dB */
91 0x288000a2, /* 22, -4.0dB */
92 0x2ac000ab, /* 23, -3.5dB */
93 0x2d4000b5, /* 24, -3.0dB */
94 0x300000c0, /* 25, -2.5dB */
95 0x32c000cb, /* 26, -2.0dB */
96 0x35c000d7, /* 27, -1.5dB */
97 0x390000e4, /* 28, -1.0dB */
98 0x3c8000f2, /* 29, -0.5dB */
99 0x40000100, /* 30, +0dB */
100 0x43c0010f, /* 31, +0.5dB */
101 0x47c0011f, /* 32, +1.0dB */
102 0x4c000130, /* 33, +1.5dB */
103 0x50800142, /* 34, +2.0dB */
104 0x55400155, /* 35, +2.5dB */
105 0x5a400169, /* 36, +3.0dB */
106 0x5fc0017f, /* 37, +3.5dB */
107 0x65400195, /* 38, +4.0dB */
108 0x6b8001ae, /* 39, +4.5dB */
109 0x71c001c7, /* 40, +5.0dB */
110 0x788001e2, /* 41, +5.5dB */
111 0x7f8001fe /* 42, +6.0dB */
112 };
113
114 static const u32 rtw8703b_cck_pwr_regs[] = {
115 0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29,
116 0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3,
117 };
118
119 static const u8 rtw8703b_cck_swing_table[][16] = {
120 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
122 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
124 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
126 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
128 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
130 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
132 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
134 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
136 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
138 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
140 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
142 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
144 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
146 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
148 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
150 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
152 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
154 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
156 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
158 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
160 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
162 };
163
164 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table)
165 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table)
166
167 static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = {
168 /* set up external crystal (XTAL) */
169 {REG_PAD_CTRL1 + 2,
170 RTW_PWR_CUT_ALL_MSK,
171 RTW_PWR_INTF_ALL_MSK,
172 RTW_PWR_ADDR_MAC,
173 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
174 /* set CLK_REQ to high active */
175 {0x0069,
176 RTW_PWR_CUT_ALL_MSK,
177 RTW_PWR_INTF_ALL_MSK,
178 RTW_PWR_ADDR_MAC,
179 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
180 /* unlock ISO/CLK/power control register */
181 {REG_RSV_CTRL,
182 RTW_PWR_CUT_ALL_MSK,
183 RTW_PWR_INTF_ALL_MSK,
184 RTW_PWR_ADDR_MAC,
185 RTW_PWR_CMD_WRITE, 0xff, 0},
186 {TRANS_SEQ_END},
187 };
188
189 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = {
190 {0x0005,
191 RTW_PWR_CUT_ALL_MSK,
192 RTW_PWR_INTF_ALL_MSK,
193 RTW_PWR_ADDR_MAC,
194 RTW_PWR_CMD_WRITE, BIT(7), 0},
195 {TRANS_SEQ_END},
196 };
197
198 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = {
199 {0x0023,
200 RTW_PWR_CUT_ALL_MSK,
201 RTW_PWR_INTF_SDIO_MSK,
202 RTW_PWR_ADDR_MAC,
203 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
204 {0x0007,
205 RTW_PWR_CUT_ALL_MSK,
206 RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK,
207 RTW_PWR_ADDR_MAC,
208 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
209 {0x0006,
210 RTW_PWR_CUT_ALL_MSK,
211 RTW_PWR_INTF_ALL_MSK,
212 RTW_PWR_ADDR_MAC,
213 RTW_PWR_CMD_WRITE, BIT(0), 0},
214 {0x0005,
215 RTW_PWR_CUT_ALL_MSK,
216 RTW_PWR_INTF_ALL_MSK,
217 RTW_PWR_ADDR_MAC,
218 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
219 {TRANS_SEQ_END},
220 };
221
222 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = {
223 {0x0020,
224 RTW_PWR_CUT_ALL_MSK,
225 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
226 RTW_PWR_ADDR_MAC,
227 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
228 {0x0067,
229 RTW_PWR_CUT_ALL_MSK,
230 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
231 RTW_PWR_ADDR_MAC,
232 RTW_PWR_CMD_WRITE, BIT(4), 0},
233 {0x0001,
234 RTW_PWR_CUT_ALL_MSK,
235 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
236 RTW_PWR_ADDR_MAC,
237 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
238 {0x0000,
239 RTW_PWR_CUT_ALL_MSK,
240 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
241 RTW_PWR_ADDR_MAC,
242 RTW_PWR_CMD_WRITE, BIT(5), 0},
243 {0x0005,
244 RTW_PWR_CUT_ALL_MSK,
245 RTW_PWR_INTF_ALL_MSK,
246 RTW_PWR_ADDR_MAC,
247 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
248 {0x0075,
249 RTW_PWR_CUT_ALL_MSK,
250 RTW_PWR_INTF_PCI_MSK,
251 RTW_PWR_ADDR_MAC,
252 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
253 {0x0004,
254 RTW_PWR_CUT_ALL_MSK,
255 RTW_PWR_INTF_PCI_MSK,
256 RTW_PWR_ADDR_MAC,
257 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
258 {0x0004,
259 RTW_PWR_CUT_ALL_MSK,
260 RTW_PWR_INTF_PCI_MSK,
261 RTW_PWR_ADDR_MAC,
262 RTW_PWR_CMD_WRITE, BIT(3), 0},
263 /* wait for power ready */
264 {0x0006,
265 RTW_PWR_CUT_ALL_MSK,
266 RTW_PWR_INTF_ALL_MSK,
267 RTW_PWR_ADDR_MAC,
268 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
269 {0x0075,
270 RTW_PWR_CUT_ALL_MSK,
271 RTW_PWR_INTF_PCI_MSK,
272 RTW_PWR_ADDR_MAC,
273 RTW_PWR_CMD_WRITE, BIT(0), 0},
274 {0x0006,
275 RTW_PWR_CUT_ALL_MSK,
276 RTW_PWR_INTF_ALL_MSK,
277 RTW_PWR_ADDR_MAC,
278 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
279 {0x0005,
280 RTW_PWR_CUT_ALL_MSK,
281 RTW_PWR_INTF_ALL_MSK,
282 RTW_PWR_ADDR_MAC,
283 RTW_PWR_CMD_WRITE, BIT(7), 0},
284 {0x0005,
285 RTW_PWR_CUT_ALL_MSK,
286 RTW_PWR_INTF_ALL_MSK,
287 RTW_PWR_ADDR_MAC,
288 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
289 {0x0005,
290 RTW_PWR_CUT_ALL_MSK,
291 RTW_PWR_INTF_ALL_MSK,
292 RTW_PWR_ADDR_MAC,
293 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
294 {0x0005,
295 RTW_PWR_CUT_ALL_MSK,
296 RTW_PWR_INTF_ALL_MSK,
297 RTW_PWR_ADDR_MAC,
298 RTW_PWR_CMD_POLLING, BIT(0), 0},
299 {0x0010,
300 RTW_PWR_CUT_ALL_MSK,
301 RTW_PWR_INTF_ALL_MSK,
302 RTW_PWR_ADDR_MAC,
303 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
304 {0x0049,
305 RTW_PWR_CUT_ALL_MSK,
306 RTW_PWR_INTF_ALL_MSK,
307 RTW_PWR_ADDR_MAC,
308 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
309 {0x0063,
310 RTW_PWR_CUT_ALL_MSK,
311 RTW_PWR_INTF_ALL_MSK,
312 RTW_PWR_ADDR_MAC,
313 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
314 {0x0062,
315 RTW_PWR_CUT_ALL_MSK,
316 RTW_PWR_INTF_ALL_MSK,
317 RTW_PWR_ADDR_MAC,
318 RTW_PWR_CMD_WRITE, BIT(1), 0},
319 {0x0058,
320 RTW_PWR_CUT_ALL_MSK,
321 RTW_PWR_INTF_ALL_MSK,
322 RTW_PWR_ADDR_MAC,
323 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
324 {0x005A,
325 RTW_PWR_CUT_ALL_MSK,
326 RTW_PWR_INTF_ALL_MSK,
327 RTW_PWR_ADDR_MAC,
328 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
329 {0x0068,
330 RTW_PWR_CUT_TEST_MSK,
331 RTW_PWR_INTF_ALL_MSK,
332 RTW_PWR_ADDR_MAC,
333 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
334 {0x0069,
335 RTW_PWR_CUT_ALL_MSK,
336 RTW_PWR_INTF_ALL_MSK,
337 RTW_PWR_ADDR_MAC,
338 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
339 {TRANS_SEQ_END},
340 };
341
342 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = {
343 {0x001f,
344 RTW_PWR_CUT_ALL_MSK,
345 RTW_PWR_INTF_ALL_MSK,
346 RTW_PWR_ADDR_MAC,
347 RTW_PWR_CMD_WRITE, 0xff, 0},
348 {0x0049,
349 RTW_PWR_CUT_ALL_MSK,
350 RTW_PWR_INTF_ALL_MSK,
351 RTW_PWR_ADDR_MAC,
352 RTW_PWR_CMD_WRITE, BIT(1), 0},
353 {0x0006,
354 RTW_PWR_CUT_ALL_MSK,
355 RTW_PWR_INTF_ALL_MSK,
356 RTW_PWR_ADDR_MAC,
357 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
358 {0x0005,
359 RTW_PWR_CUT_ALL_MSK,
360 RTW_PWR_INTF_ALL_MSK,
361 RTW_PWR_ADDR_MAC,
362 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
363 {0x0005,
364 RTW_PWR_CUT_ALL_MSK,
365 RTW_PWR_INTF_ALL_MSK,
366 RTW_PWR_ADDR_MAC,
367 RTW_PWR_CMD_POLLING, BIT(1), 0},
368 {0x0010,
369 RTW_PWR_CUT_ALL_MSK,
370 RTW_PWR_INTF_ALL_MSK,
371 RTW_PWR_ADDR_MAC,
372 RTW_PWR_CMD_WRITE, BIT(6), 0},
373 {0x0000,
374 RTW_PWR_CUT_ALL_MSK,
375 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
376 RTW_PWR_ADDR_MAC,
377 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
378 {0x0020,
379 RTW_PWR_CUT_ALL_MSK,
380 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
381 RTW_PWR_ADDR_MAC,
382 RTW_PWR_CMD_WRITE, BIT(0), 0},
383 {TRANS_SEQ_END},
384 };
385
386 static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = {
387 {REG_SYS_FUNC_EN + 1,
388 RTW_PWR_CUT_ALL_MSK,
389 RTW_PWR_INTF_SDIO_MSK,
390 RTW_PWR_ADDR_MAC,
391 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0},
392 /* reset MCU ready */
393 {REG_MCUFW_CTRL,
394 RTW_PWR_CUT_ALL_MSK,
395 RTW_PWR_INTF_SDIO_MSK,
396 RTW_PWR_ADDR_MAC,
397 RTW_PWR_CMD_WRITE, 0xff, 0},
398 /* reset MCU IO wrapper */
399 {REG_RSV_CTRL + 1,
400 RTW_PWR_CUT_ALL_MSK,
401 RTW_PWR_INTF_SDIO_MSK,
402 RTW_PWR_ADDR_MAC,
403 RTW_PWR_CMD_WRITE, BIT(0), 0},
404 {REG_RSV_CTRL + 1,
405 RTW_PWR_CUT_ALL_MSK,
406 RTW_PWR_INTF_SDIO_MSK,
407 RTW_PWR_ADDR_MAC,
408 RTW_PWR_CMD_WRITE, BIT(0), 1},
409 {TRANS_SEQ_END},
410 };
411
412 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = {
413 {0x0301,
414 RTW_PWR_CUT_ALL_MSK,
415 RTW_PWR_INTF_ALL_MSK,
416 RTW_PWR_ADDR_MAC,
417 RTW_PWR_CMD_WRITE, 0xff, 0xff},
418 {0x0522,
419 RTW_PWR_CUT_ALL_MSK,
420 RTW_PWR_INTF_ALL_MSK,
421 RTW_PWR_ADDR_MAC,
422 RTW_PWR_CMD_WRITE, 0xff, 0xff},
423 {0x05f8,
424 RTW_PWR_CUT_ALL_MSK,
425 RTW_PWR_INTF_ALL_MSK,
426 RTW_PWR_ADDR_MAC,
427 RTW_PWR_CMD_POLLING, 0xff, 0},
428 {0x05f9,
429 RTW_PWR_CUT_ALL_MSK,
430 RTW_PWR_INTF_ALL_MSK,
431 RTW_PWR_ADDR_MAC,
432 RTW_PWR_CMD_POLLING, 0xff, 0},
433 {0x05fa,
434 RTW_PWR_CUT_ALL_MSK,
435 RTW_PWR_INTF_ALL_MSK,
436 RTW_PWR_ADDR_MAC,
437 RTW_PWR_CMD_POLLING, 0xff, 0},
438 {0x05fb,
439 RTW_PWR_CUT_ALL_MSK,
440 RTW_PWR_INTF_ALL_MSK,
441 RTW_PWR_ADDR_MAC,
442 RTW_PWR_CMD_POLLING, 0xff, 0},
443 {0x0002,
444 RTW_PWR_CUT_ALL_MSK,
445 RTW_PWR_INTF_ALL_MSK,
446 RTW_PWR_ADDR_MAC,
447 RTW_PWR_CMD_WRITE, BIT(0), 0},
448 {0x0002,
449 RTW_PWR_CUT_ALL_MSK,
450 RTW_PWR_INTF_ALL_MSK,
451 RTW_PWR_ADDR_MAC,
452 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
453 {0x0002,
454 RTW_PWR_CUT_ALL_MSK,
455 RTW_PWR_INTF_ALL_MSK,
456 RTW_PWR_ADDR_MAC,
457 RTW_PWR_CMD_WRITE, BIT(1), 0},
458 {0x0100,
459 RTW_PWR_CUT_ALL_MSK,
460 RTW_PWR_INTF_ALL_MSK,
461 RTW_PWR_ADDR_MAC,
462 RTW_PWR_CMD_WRITE, 0xff, 0x03},
463 {0x0101,
464 RTW_PWR_CUT_ALL_MSK,
465 RTW_PWR_INTF_ALL_MSK,
466 RTW_PWR_ADDR_MAC,
467 RTW_PWR_CMD_WRITE, BIT(1), 0},
468 {0x0093,
469 RTW_PWR_CUT_ALL_MSK,
470 RTW_PWR_INTF_SDIO_MSK,
471 RTW_PWR_ADDR_MAC,
472 RTW_PWR_CMD_WRITE, 0xff, 0},
473 {0x0553,
474 RTW_PWR_CUT_ALL_MSK,
475 RTW_PWR_INTF_ALL_MSK,
476 RTW_PWR_ADDR_MAC,
477 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
478 {TRANS_SEQ_END},
479 };
480
481 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8703b[] = {
482 trans_pre_enable_8703b,
483 trans_carddis_to_cardemu_8703b,
484 trans_cardemu_to_act_8703b,
485 NULL
486 };
487
488 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8703b[] = {
489 trans_act_to_lps_8703b,
490 trans_act_to_reset_mcu_8703b,
491 trans_act_to_cardemu_8703b,
492 trans_cardemu_to_carddis_8703b,
493 NULL
494 };
495
496 static const struct rtw_page_table page_table_8703b[] = {
497 {12, 2, 2, 0, 1},
498 {12, 2, 2, 0, 1},
499 {12, 2, 2, 0, 1},
500 {12, 2, 2, 0, 1},
501 {12, 2, 2, 0, 1},
502 };
503
504 static const struct rtw_rqpn rqpn_table_8703b[] = {
505 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
506 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
507 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
508 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
509 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
510 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
511 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
512 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
513 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
514 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
515 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
516 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
517 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
518 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
519 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
520 };
521
522 /* Default power index table for RTL8703B, used if EFUSE does not
523 * contain valid data. Replaces EFUSE data from offset 0x10 (start of
524 * txpwr_idx_table).
525 */
526 static const u8 rtw8703b_txpwr_idx_table[] = {
527 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
528 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02
529 };
530
try_mac_from_devicetree(struct rtw_dev * rtwdev)531 static void try_mac_from_devicetree(struct rtw_dev *rtwdev)
532 {
533 struct device_node *node = rtwdev->dev->of_node;
534 struct rtw_efuse *efuse = &rtwdev->efuse;
535 int ret;
536
537 if (node) {
538 ret = of_get_mac_address(node, efuse->addr);
539 if (ret == 0) {
540 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
541 "got wifi mac address from DT: %pM\n",
542 efuse->addr);
543 }
544 }
545 }
546
547 #define DBG_EFUSE_FIX(rtwdev, name) \
548 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \
549 # name "=0x%x\n", rtwdev->efuse.name)
550
rtw8703b_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)551 static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
552 {
553 struct rtw_efuse *efuse = &rtwdev->efuse;
554 u8 *pwr = (u8 *)efuse->txpwr_idx_table;
555 bool valid = false;
556 int ret;
557
558 ret = rtw8723x_read_efuse(rtwdev, log_map);
559 if (ret != 0)
560 return ret;
561
562 if (!is_valid_ether_addr(efuse->addr))
563 try_mac_from_devicetree(rtwdev);
564
565 /* If TX power index table in EFUSE is invalid, fall back to
566 * built-in table.
567 */
568 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++)
569 if (pwr[i] != 0xff) {
570 valid = true;
571 break;
572 }
573 if (!valid) {
574 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++)
575 pwr[i] = rtw8703b_txpwr_idx_table[i];
576 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
577 "Replaced invalid EFUSE TX power index table.");
578 rtw8723x_debug_txpwr_limit(rtwdev,
579 efuse->txpwr_idx_table, 2);
580 }
581
582 /* Override invalid antenna settings. */
583 if (efuse->bt_setting == 0xff) {
584 /* shared antenna */
585 efuse->bt_setting |= BIT(0);
586 /* RF path A */
587 efuse->bt_setting &= ~BIT(6);
588 DBG_EFUSE_FIX(rtwdev, bt_setting);
589 }
590
591 /* Override invalid board options: The coex code incorrectly
592 * assumes that if bits 6 & 7 are set the board doesn't
593 * support coex. Regd is also derived from rf_board_option and
594 * should be 0 if there's no valid data.
595 */
596 if (efuse->rf_board_option == 0xff) {
597 efuse->regd = 0;
598 efuse->rf_board_option &= GENMASK(5, 0);
599 DBG_EFUSE_FIX(rtwdev, rf_board_option);
600 }
601
602 /* Override invalid crystal cap setting, default comes from
603 * vendor driver. Chip specific.
604 */
605 if (efuse->crystal_cap == 0xff) {
606 efuse->crystal_cap = 0x20;
607 DBG_EFUSE_FIX(rtwdev, crystal_cap);
608 }
609
610 return 0;
611 }
612
rtw8703b_pwrtrack_init(struct rtw_dev * rtwdev)613 static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev)
614 {
615 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
616 u8 path;
617
618 /* TODO: The vendor driver selects these using tables in
619 * halrf_powertracking_ce.c, functions are called
620 * get_swing_index and get_cck_swing_index. There the current
621 * fixed values are only the defaults in case no match is
622 * found.
623 */
624 dm_info->default_ofdm_index = 30;
625 dm_info->default_cck_index = 20;
626
627 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
628 ewma_thermal_init(&dm_info->avg_thermal[path]);
629 dm_info->delta_power_index[path] = 0;
630 }
631 dm_info->pwr_trk_triggered = false;
632 dm_info->pwr_trk_init_trigger = true;
633 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
634 dm_info->txagc_remnant_cck = 0;
635 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0;
636 }
637
rtw8703b_phy_set_param(struct rtw_dev * rtwdev)638 static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev)
639 {
640 u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
641
642 /* power on BB/RF domain */
643 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN,
644 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
645 rtw_write8_set(rtwdev, REG_RF_CTRL,
646 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
647 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780);
648 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
649
650 rtw_phy_load_tables(rtwdev);
651
652 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
653 /* 0xff is from vendor driver, rtw8723d uses
654 * BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet
655 * in Hi Queue Tx immediately". I wonder if setting all bits
656 * is really necessary.
657 */
658 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);
659 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN);
660
661 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
662 xtal_cap | (xtal_cap << 6));
663 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
664
665 /* Init EDCA */
666 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS);
667 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS);
668 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */
669 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */
670 /* TXOP */
671 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
672 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
673 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
674 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
675
676 /* Init retry */
677 rtw_write8(rtwdev, REG_ACKTO, 0x40);
678
679 /* Set up RX aggregation. sdio.c also sets DMA mode, but not
680 * the burst parameters.
681 */
682 rtw_write8(rtwdev, REG_RXDMA_MODE,
683 BIT_DMA_MODE |
684 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) |
685 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE));
686
687 /* Init beacon parameters */
688 rtw_write8(rtwdev, REG_BCN_CTRL,
689 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT);
690 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
691 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1,
692 TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
693 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2,
694 (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0)
695 | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
696
697 /* configure packet burst */
698 rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
699 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT);
700 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR);
701 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL);
702 rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT);
703 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME);
704
705 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
706 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL);
707 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL);
708 rtw_write16(rtwdev, REG_ATIMWND, 0x2);
709
710 rtw_phy_init(rtwdev);
711
712 if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) {
713 rtwdev->dm_info.rx_cck_agc_report_type = 1;
714 } else {
715 rtwdev->dm_info.rx_cck_agc_report_type = 0;
716 rtw_warn(rtwdev, "unexpected cck agc report type");
717 }
718
719 rtw8723x_lck(rtwdev);
720
721 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
722 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
723
724 rtw8703b_pwrtrack_init(rtwdev);
725 }
726
rtw8703b_check_spur_ov_thres(struct rtw_dev * rtwdev,u32 freq,u32 thres)727 static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev,
728 u32 freq, u32 thres)
729 {
730 bool ret = false;
731
732 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE);
733 rtw_write32(rtwdev, REG_PSDFN, freq);
734 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq);
735
736 msleep(30);
737 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres)
738 ret = true;
739
740 rtw_write32(rtwdev, REG_PSDFN, freq);
741 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE);
742
743 return ret;
744 }
745
rtw8703b_cfg_notch(struct rtw_dev * rtwdev,u8 channel,bool notch)746 static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch)
747 {
748 if (!notch) {
749 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
750 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
751 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
752 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
753 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
754 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
755 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
756 return;
757 }
758
759 switch (channel) {
760 case 5:
761 fallthrough;
762 case 13:
763 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
764 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
765 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000);
766 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
767 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
768 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
769 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
770 break;
771 case 6:
772 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4);
773 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
774 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600);
775 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
776 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
777 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
778 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
779 break;
780 case 7:
781 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3);
782 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
783 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
784 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
785 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
786 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000);
787 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
788 break;
789 case 8:
790 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa);
791 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
792 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
793 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
794 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
795 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380);
796 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
797 break;
798 case 14:
799 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
800 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
801 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
802 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
803 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
804 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000);
805 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
806 break;
807 default:
808 rtw_warn(rtwdev,
809 "Bug: Notch filter enable called for channel %u!",
810 channel);
811 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
812 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
813 break;
814 }
815 }
816
rtw8703b_spur_cal(struct rtw_dev * rtwdev,u8 channel)817 static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel)
818 {
819 bool notch;
820 u32 freq;
821
822 if (channel == 5) {
823 freq = FREQ_CH5;
824 } else if (channel == 6) {
825 freq = FREQ_CH6;
826 } else if (channel == 7) {
827 freq = FREQ_CH7;
828 } else if (channel == 8) {
829 freq = FREQ_CH8;
830 } else if (channel == 13) {
831 freq = FREQ_CH13;
832 } else if (channel == 14) {
833 freq = FREQ_CH14;
834 } else {
835 rtw8703b_cfg_notch(rtwdev, channel, false);
836 return;
837 }
838
839 notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES);
840 rtw8703b_cfg_notch(rtwdev, channel, notch);
841 }
842
rtw8703b_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)843 static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
844 {
845 u32 rf_cfgch_a;
846 u32 rf_cfgch_b;
847 /* default value for 20M */
848 u32 rf_rck = 0x00000C08;
849
850 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
851 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK);
852
853 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK;
854 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK;
855 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK);
856 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK);
857
858 rf_cfgch_a &= ~RFCFGCH_BW_MASK;
859 switch (bw) {
860 case RTW_CHANNEL_WIDTH_20:
861 rf_cfgch_a |= RFCFGCH_BW_20M;
862 break;
863 case RTW_CHANNEL_WIDTH_40:
864 rf_cfgch_a |= RFCFGCH_BW_40M;
865 rf_rck = 0x00000C4C;
866 break;
867 default:
868 break;
869 }
870
871 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a);
872 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b);
873
874 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck);
875 rtw8703b_spur_cal(rtwdev, channel);
876 }
877
878 #define CCK_DFIR_NR_8703B 2
879 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = {
880 [0] = {
881 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD },
882 { .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B },
883 },
884 [1] = {
885 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 },
886 { .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 },
887 },
888 };
889
rtw8703b_set_channel_bb(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)890 static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
891 u8 primary_ch_idx)
892 {
893 const struct rtw_backup_info *cck_dfir;
894 int i;
895
896 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
897
898 for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++)
899 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val);
900
901 switch (bw) {
902 case RTW_CHANNEL_WIDTH_20:
903 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
904 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
905 rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE,
906 GENMASK(31, 30), 0x0);
907 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000);
908 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000);
909 break;
910 case RTW_CHANNEL_WIDTH_40:
911 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
912 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
913 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000);
914 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000);
915 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,
916 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0);
917 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00,
918 primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1);
919
920 rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26),
921 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2);
922 break;
923 default:
924 break;
925 }
926 }
927
rtw8703b_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)928 static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel,
929 u8 bw, u8 primary_chan_idx)
930 {
931 rtw8703b_set_channel_rf(rtwdev, channel, bw);
932 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
933 rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
934 }
935
936 /* Not all indices are valid, based on available data. None of the
937 * known valid values are positive, so use 0x7f as "invalid".
938 */
939 #define LNA_IDX_INVALID 0x7f
940 static const s8 lna_gain_table[16] = {
941 -2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID,
942 -6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19,
943 -32, LNA_IDX_INVALID, -36, -42,
944 LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48,
945 };
946
get_cck_rx_pwr(struct rtw_dev * rtwdev,u8 lna_idx,u8 vga_idx)947 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
948 {
949 s8 lna_gain = 0;
950
951 if (lna_idx < ARRAY_SIZE(lna_gain_table))
952 lna_gain = lna_gain_table[lna_idx];
953
954 if (lna_gain >= 0) {
955 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
956 return -120;
957 }
958
959 return lna_gain - 2 * vga_idx;
960 }
961
query_phy_status_cck(struct rtw_dev * rtwdev,u8 * phy_raw,struct rtw_rx_pkt_stat * pkt_stat)962 static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw,
963 struct rtw_rx_pkt_stat *pkt_stat)
964 {
965 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw;
966 u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS;
967 u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS;
968 s8 rx_power;
969
970 if (rtwdev->dm_info.rx_cck_agc_report_type == 1)
971 lna_idx = FIELD_PREP(BIT_LNA_H_MASK,
972 phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT)
973 | FIELD_PREP(BIT_LNA_L_MASK, lna_idx);
974 else
975 lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx);
976 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
977
978 pkt_stat->rx_power[RF_PATH_A] = rx_power;
979 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
980 rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi;
981 pkt_stat->signal_power = rx_power;
982 }
983
query_phy_status_ofdm(struct rtw_dev * rtwdev,u8 * phy_raw,struct rtw_rx_pkt_stat * pkt_stat)984 static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw,
985 struct rtw_rx_pkt_stat *pkt_stat)
986 {
987 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw;
988 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
989 s8 val_s8;
990
991 val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F;
992 pkt_stat->rx_power[RF_PATH_A] = (val_s8 * 2) - 110;
993 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
994 pkt_stat->rx_snr[RF_PATH_A] = (s8)(phy_status->path_rxsnr[RF_PATH_A] / 2);
995
996 /* signal power reported by HW */
997 val_s8 = phy_status->cck_sig_qual_ofdm_pwdb_all >> 1;
998 pkt_stat->signal_power = (val_s8 & 0x7f) - 110;
999
1000 pkt_stat->rx_evm[RF_PATH_A] = phy_status->stream_rxevm[RF_PATH_A];
1001 pkt_stat->cfo_tail[RF_PATH_A] = phy_status->path_cfotail[RF_PATH_A];
1002
1003 dm_info->curr_rx_rate = pkt_stat->rate;
1004 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
1005 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1;
1006 /* convert to KHz (used only for debugfs) */
1007 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1;
1008
1009 /* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0
1010 * range. rx_evm_dbm needs the absolute (positive) value.
1011 */
1012 val_s8 = (s8)pkt_stat->rx_evm[RF_PATH_A];
1013 val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64);
1014 val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */
1015 dm_info->rx_evm_dbm[RF_PATH_A] = val_s8;
1016 }
1017
query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)1018 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1019 struct rtw_rx_pkt_stat *pkt_stat)
1020 {
1021 if (pkt_stat->rate <= DESC_RATE11M)
1022 query_phy_status_cck(rtwdev, phy_status, pkt_stat);
1023 else
1024 query_phy_status_ofdm(rtwdev, phy_status, pkt_stat);
1025 }
1026
1027 #define ADDA_ON_VAL_8703B 0x03c00014
1028
1029 static
rtw8703b_iqk_config_mac(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)1030 void rtw8703b_iqk_config_mac(struct rtw_dev *rtwdev,
1031 const struct rtw8723x_iqk_backup_regs *backup)
1032 {
1033 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F);
1034 for (int i = 1; i < RTW8723X_IQK_MAC8_REG_NUM; i++)
1035 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i],
1036 backup->mac8[i] & (~BIT(3)));
1037 }
1038
1039 #define IQK_LTE_WRITE_VAL_8703B 0x00007700
1040 #define IQK_DELAY_TIME_8703B 4
1041
rtw8703b_iqk_one_shot(struct rtw_dev * rtwdev,bool tx)1042 static void rtw8703b_iqk_one_shot(struct rtw_dev *rtwdev, bool tx)
1043 {
1044 u32 regval;
1045 ktime_t t;
1046 s64 dur;
1047 int ret;
1048
1049 /* enter IQK mode */
1050 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
1051 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B);
1052
1053 /* One shot, LOK & IQK */
1054 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000);
1055 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);
1056
1057 t = ktime_get();
1058 msleep(IQK_DELAY_TIME_8703B);
1059 ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000,
1060 100000, false, rtwdev,
1061 REG_IQK_RDY);
1062 dur = ktime_us_delta(ktime_get(), t);
1063
1064 if (ret)
1065 rtw_warn(rtwdev, "[IQK] %s timed out after %lldus!\n",
1066 tx ? "TX" : "RX", dur);
1067 else
1068 rtw_dbg(rtwdev, RTW_DBG_RFK,
1069 "[IQK] %s done after %lldus\n",
1070 tx ? "TX" : "RX", dur);
1071 }
1072
rtw8703b_iqk_txrx_path_post(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)1073 static void rtw8703b_iqk_txrx_path_post(struct rtw_dev *rtwdev,
1074 const struct rtw8723x_iqk_backup_regs *backup)
1075 {
1076 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup);
1077 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg);
1078
1079 /* leave IQK mode */
1080 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1081 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0);
1082 }
1083
rtw8703b_iqk_check_tx_failed(struct rtw_dev * rtwdev)1084 static u8 rtw8703b_iqk_check_tx_failed(struct rtw_dev *rtwdev)
1085 {
1086 s32 tx_x, tx_y;
1087 u32 tx_fail;
1088
1089 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",
1090 rtw_read32(rtwdev, REG_IQK_RES_RY));
1091 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",
1092 rtw_read32(rtwdev, REG_IQK_RES_TX),
1093 rtw_read32(rtwdev, REG_IQK_RES_TY));
1094 rtw_dbg(rtwdev, RTW_DBG_RFK,
1095 "[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n",
1096 rtw_read32(rtwdev, REG_IQK_RDY),
1097 rtw_read32(rtwdev, 0xe98));
1098
1099 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL);
1100 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
1101 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
1102
1103 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR)
1104 return IQK_TX_OK;
1105
1106 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A TX IQK failed\n");
1107
1108 return 0;
1109 }
1110
rtw8703b_iqk_check_rx_failed(struct rtw_dev * rtwdev)1111 static u8 rtw8703b_iqk_check_rx_failed(struct rtw_dev *rtwdev)
1112 {
1113 s32 rx_x, rx_y;
1114 u32 rx_fail;
1115
1116 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",
1117 rtw_read32(rtwdev, REG_IQK_RES_RX),
1118 rtw_read32(rtwdev, REG_IQK_RES_RY));
1119
1120 rtw_dbg(rtwdev, RTW_DBG_RFK,
1121 "[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n",
1122 rtw_read32(rtwdev, 0xea0),
1123 rtw_read32(rtwdev, 0xea8));
1124
1125 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL);
1126 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
1127 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
1128 rx_y = abs(iqkxy_to_s32(rx_y));
1129
1130 if (!rx_fail && rx_x != IQK_RX_X_ERR && rx_y != IQK_RX_Y_ERR &&
1131 rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER &&
1132 rx_y < IQK_RX_Y_LMT)
1133 return IQK_RX_OK;
1134
1135 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A RX IQK failed\n");
1136
1137 return 0;
1138 }
1139
rtw8703b_iqk_tx_path(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)1140 static u8 rtw8703b_iqk_tx_path(struct rtw_dev *rtwdev,
1141 const struct rtw8723x_iqk_backup_regs *backup)
1142 {
1143 u8 status;
1144
1145 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK!\n");
1146
1147 /* IQK setting */
1148 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
1149 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1150 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
1151 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
1152 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1153 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1154 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f);
1155 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);
1156 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);
1157 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);
1158
1159 /* LO calibration setting */
1160 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);
1161
1162 /* leave IQK mode */
1163 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);
1164
1165 /* PA, PAD setting */
1166 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);
1167 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7);
1168 rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400);
1169
1170 rtw8703b_iqk_one_shot(rtwdev, true);
1171 status = rtw8703b_iqk_check_tx_failed(rtwdev);
1172
1173 rtw8703b_iqk_txrx_path_post(rtwdev, backup);
1174
1175 return status;
1176 }
1177
rtw8703b_iqk_rx_path(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)1178 static u8 rtw8703b_iqk_rx_path(struct rtw_dev *rtwdev,
1179 const struct rtw8723x_iqk_backup_regs *backup)
1180 {
1181 u8 status;
1182 u32 tx_x, tx_y;
1183
1184 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 1!\n");
1185 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n",
1186 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
1187 rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000);
1188
1189 /* disable IQC mode */
1190 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1191
1192 /* IQK setting */
1193 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
1194 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1195
1196 /* path IQK setting */
1197 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
1198 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
1199 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1200 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1201 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f);
1202 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);
1203 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);
1204 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);
1205
1206 /* LOK setting */
1207 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);
1208
1209 /* RX IQK mode */
1210 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);
1211 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);
1212 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);
1213 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7);
1214
1215 rtw8703b_iqk_one_shot(rtwdev, true);
1216 /* leave IQK mode */
1217 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);
1218 status = rtw8703b_iqk_check_tx_failed(rtwdev);
1219
1220 if (!status)
1221 goto restore;
1222
1223 /* second round */
1224 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
1225 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
1226
1227 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y));
1228 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",
1229 rtw_read32(rtwdev, REG_TXIQK_11N),
1230 BIT_SET_TXIQK_11N(tx_x, tx_y));
1231
1232 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 2!\n");
1233 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n",
1234 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
1235
1236 /* IQK setting */
1237 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1238 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);
1239 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);
1240 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1241 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1242 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000);
1243 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f);
1244 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);
1245 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);
1246
1247 /* LO calibration setting */
1248 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);
1249
1250 /* leave IQK mode */
1251 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);
1252 /* modify RX IQK mode table */
1253 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);
1254 /* RF_RCK_OS, RF_TXPA_G1, RF_TXPA_G2 */
1255 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);
1256 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);
1257 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77);
1258
1259 /* PA, PAD setting */
1260 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);
1261 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5);
1262
1263 rtw8703b_iqk_one_shot(rtwdev, false);
1264 status |= rtw8703b_iqk_check_rx_failed(rtwdev);
1265
1266 restore:
1267 rtw8703b_iqk_txrx_path_post(rtwdev, backup);
1268
1269 return status;
1270 }
1271
1272 static
rtw8703b_iqk_one_round(struct rtw_dev * rtwdev,s32 result[][IQK_NR],u8 t,const struct rtw8723x_iqk_backup_regs * backup)1273 void rtw8703b_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t,
1274 const struct rtw8723x_iqk_backup_regs *backup)
1275 {
1276 u32 i;
1277 u8 a_ok;
1278
1279 rtw_dbg(rtwdev, RTW_DBG_RFK,
1280 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t);
1281
1282 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8703B);
1283 rtw8703b_iqk_config_mac(rtwdev, backup);
1284 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);
1285 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600);
1286 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);
1287 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000);
1288
1289 for (i = 0; i < PATH_IQK_RETRY; i++) {
1290 a_ok = rtw8703b_iqk_tx_path(rtwdev, backup);
1291 if (a_ok == IQK_TX_OK) {
1292 rtw_dbg(rtwdev, RTW_DBG_RFK,
1293 "[IQK] path A TX IQK success!\n");
1294 result[t][IQK_S1_TX_X] =
1295 rtw_read32_mask(rtwdev, REG_IQK_RES_TX,
1296 BIT_MASK_RES_TX);
1297 result[t][IQK_S1_TX_Y] =
1298 rtw_read32_mask(rtwdev, REG_IQK_RES_TY,
1299 BIT_MASK_RES_TY);
1300 break;
1301 }
1302
1303 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK fail!\n");
1304 result[t][IQK_S1_TX_X] = 0x100;
1305 result[t][IQK_S1_TX_Y] = 0x0;
1306 }
1307
1308 for (i = 0; i < PATH_IQK_RETRY; i++) {
1309 a_ok = rtw8703b_iqk_rx_path(rtwdev, backup);
1310 if (a_ok == (IQK_TX_OK | IQK_RX_OK)) {
1311 rtw_dbg(rtwdev, RTW_DBG_RFK,
1312 "[IQK] path A RX IQK success!\n");
1313 result[t][IQK_S1_RX_X] =
1314 rtw_read32_mask(rtwdev, REG_IQK_RES_RX,
1315 BIT_MASK_RES_RX);
1316 result[t][IQK_S1_RX_Y] =
1317 rtw_read32_mask(rtwdev, REG_IQK_RES_RY,
1318 BIT_MASK_RES_RY);
1319 break;
1320 }
1321
1322 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK fail!\n");
1323 result[t][IQK_S1_RX_X] = 0x100;
1324 result[t][IQK_S1_RX_Y] = 0x0;
1325 }
1326
1327 if (a_ok == 0x0)
1328 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A IQK fail!\n");
1329
1330 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1331 mdelay(1);
1332 }
1333
1334 static
rtw8703b_iqk_fill_a_matrix(struct rtw_dev * rtwdev,const s32 result[])1335 void rtw8703b_iqk_fill_a_matrix(struct rtw_dev *rtwdev, const s32 result[])
1336 {
1337 u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16);
1338 s32 tx1_a, tx1_a_ext;
1339 s32 tx1_c, tx1_c_ext;
1340 s32 oldval_1;
1341 s32 x, y;
1342
1343 if (result[IQK_S1_TX_X] == 0)
1344 return;
1345
1346 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1347 BIT_MASK_TXIQ_ELM_D);
1348
1349 x = iqkxy_to_s32(result[IQK_S1_TX_X]);
1350 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext);
1351 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1352 BIT_MASK_TXIQ_ELM_A, tx1_a);
1353 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
1354 BIT_MASK_OFDM0_EXT_A, tx1_a_ext);
1355
1356 y = iqkxy_to_s32(result[IQK_S1_TX_Y]);
1357 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext);
1358 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1359 BIT_SET_TXIQ_ELM_C1(tx1_c));
1360 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1361 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c));
1362 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
1363 BIT_MASK_OFDM0_EXT_C, tx1_c_ext);
1364
1365 rtw_dbg(rtwdev, RTW_DBG_RFK,
1366 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",
1367 x, tx1_a, oldval_1);
1368 rtw_dbg(rtwdev, RTW_DBG_RFK,
1369 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);
1370
1371 if (result[IQK_S1_RX_X] == 0)
1372 return;
1373
1374 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_X, result[IQK_S1_RX_X]);
1375 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_Y1, result[IQK_S1_RX_Y]);
1376 rtw_write32(rtwdev, REG_A_RXIQI, tmp_rx_iqi);
1377 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2,
1378 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y]));
1379 }
1380
rtw8703b_phy_calibration(struct rtw_dev * rtwdev)1381 static void rtw8703b_phy_calibration(struct rtw_dev *rtwdev)
1382 {
1383 /* For some reason path A is called S1 and B S0 in shared
1384 * rtw88 calibration data.
1385 */
1386 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1387 struct rtw8723x_iqk_backup_regs backup;
1388 u8 final_candidate = IQK_ROUND_INVALID;
1389 s32 result[IQK_ROUND_SIZE][IQK_NR];
1390 bool good;
1391 u8 i, j;
1392
1393 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!\n");
1394
1395 memset(result, 0, sizeof(result));
1396
1397 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup);
1398 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup);
1399 rtw8723x_iqk_backup_regs(rtwdev, &backup);
1400
1401 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) {
1402 rtw8723x_iqk_config_path_ctrl(rtwdev);
1403 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B);
1404
1405 rtw8703b_iqk_one_round(rtwdev, result, i, &backup);
1406
1407 rtw_dbg(rtwdev, RTW_DBG_RFK,
1408 "[IQK] back to BB mode, load original values!\n");
1409 if (i > IQK_ROUND_0)
1410 rtw8723x_iqk_restore_regs(rtwdev, &backup);
1411 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup);
1412 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup);
1413
1414 for (j = IQK_ROUND_0; j < i; j++) {
1415 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i);
1416
1417 if (good) {
1418 final_candidate = j;
1419 rtw_dbg(rtwdev, RTW_DBG_RFK,
1420 "[IQK] cmp %d:%d final_candidate is %x\n",
1421 j, i, final_candidate);
1422 goto iqk_done;
1423 }
1424 }
1425 }
1426
1427 if (final_candidate == IQK_ROUND_INVALID) {
1428 s32 reg_tmp = 0;
1429
1430 for (i = 0; i < IQK_NR; i++)
1431 reg_tmp += result[IQK_ROUND_HYBRID][i];
1432
1433 if (reg_tmp != 0) {
1434 final_candidate = IQK_ROUND_HYBRID;
1435 } else {
1436 WARN(1, "IQK failed\n");
1437 goto out;
1438 }
1439 }
1440
1441 iqk_done:
1442 /* only path A is calibrated in rtl8703b */
1443 rtw8703b_iqk_fill_a_matrix(rtwdev, result[final_candidate]);
1444
1445 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X];
1446 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y];
1447 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X];
1448 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y];
1449 dm_info->iqk.done = true;
1450
1451 out:
1452 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg);
1453
1454 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n",
1455 final_candidate);
1456
1457 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++)
1458 rtw_dbg(rtwdev, RTW_DBG_RFK,
1459 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n",
1460 i,
1461 result[i][0], result[i][1], result[i][2], result[i][3],
1462 result[i][4], result[i][5], result[i][6], result[i][7],
1463 final_candidate == i ? "(final candidate)" : "");
1464
1465 rtw_dbg(rtwdev, RTW_DBG_RFK,
1466 "[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
1467 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE),
1468 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N),
1469 rtw_read32(rtwdev, REG_A_RXIQI),
1470 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N));
1471 rtw_dbg(rtwdev, RTW_DBG_RFK,
1472 "[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
1473 rtw_read32(rtwdev, REG_TXIQ_AB_S0),
1474 rtw_read32(rtwdev, REG_TXIQ_CD_S0),
1475 rtw_read32(rtwdev, REG_RXIQ_AB_S0));
1476
1477 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Finished.\n");
1478 }
1479
rtw8703b_set_iqk_matrix_by_result(struct rtw_dev * rtwdev,u32 ofdm_swing,u8 rf_path)1480 static void rtw8703b_set_iqk_matrix_by_result(struct rtw_dev *rtwdev,
1481 u32 ofdm_swing, u8 rf_path)
1482 {
1483 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1484 s32 ele_A, ele_D, ele_C;
1485 s32 ele_A_ext, ele_C_ext, ele_D_ext;
1486 s32 iqk_result_x;
1487 s32 iqk_result_y;
1488 s32 value32;
1489
1490 switch (rf_path) {
1491 default:
1492 case RF_PATH_A:
1493 iqk_result_x = dm_info->iqk.result.s1_x;
1494 iqk_result_y = dm_info->iqk.result.s1_y;
1495 break;
1496 case RF_PATH_B:
1497 iqk_result_x = dm_info->iqk.result.s0_x;
1498 iqk_result_y = dm_info->iqk.result.s0_y;
1499 break;
1500 }
1501
1502 /* new element D */
1503 ele_D = OFDM_SWING_D(ofdm_swing);
1504 iqk_mult(iqk_result_x, ele_D, &ele_D_ext);
1505 /* new element A */
1506 iqk_result_x = iqkxy_to_s32(iqk_result_x);
1507 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext);
1508 /* new element C */
1509 iqk_result_y = iqkxy_to_s32(iqk_result_y);
1510 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext);
1511
1512 switch (rf_path) {
1513 case RF_PATH_A:
1514 default:
1515 /* write new elements A, C, D, and element B is always 0 */
1516 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D);
1517 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32);
1518 value32 = BIT_SET_TXIQ_ELM_C1(ele_C);
1519 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1520 value32);
1521 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1522 value32 &= ~BIT_MASK_OFDM0_EXTS;
1523 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext);
1524 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1525 break;
1526
1527 case RF_PATH_B:
1528 /* write new elements A, C, D, and element B is always 0 */
1529 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D);
1530 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, value32);
1531 value32 = BIT_SET_TXIQ_ELM_C1(ele_C);
1532 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS,
1533 value32);
1534 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1535 value32 &= ~BIT_MASK_OFDM0_EXTS_B;
1536 value32 |= BIT_SET_OFDM0_EXTS_B(ele_A_ext, ele_C_ext, ele_D_ext);
1537 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1538 break;
1539 }
1540 }
1541
rtw8703b_set_iqk_matrix(struct rtw_dev * rtwdev,s8 ofdm_index,u8 rf_path)1542 static void rtw8703b_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index,
1543 u8 rf_path)
1544 {
1545 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1546 s32 value32;
1547 u32 ofdm_swing;
1548
1549 ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1);
1550
1551 ofdm_swing = rtw8703b_ofdm_swing_table[ofdm_index];
1552
1553 if (dm_info->iqk.done) {
1554 rtw8703b_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path);
1555 return;
1556 }
1557
1558 switch (rf_path) {
1559 case RF_PATH_A:
1560 default:
1561 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing);
1562 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1563 0x00);
1564
1565 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1566 value32 &= ~BIT_MASK_OFDM0_EXTS;
1567 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1568 break;
1569
1570 case RF_PATH_B:
1571 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, ofdm_swing);
1572 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS,
1573 0x00);
1574
1575 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1576 value32 &= ~BIT_MASK_OFDM0_EXTS_B;
1577 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1578 break;
1579 }
1580 }
1581
rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev * rtwdev,s8 swing_idx,s8 txagc_idx)1582 static void rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1583 s8 txagc_idx)
1584 {
1585 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1586
1587 dm_info->txagc_remnant_ofdm[RF_PATH_A] = txagc_idx;
1588
1589 /* Only path A is calibrated for rtl8703b */
1590 rtw8703b_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A);
1591 }
1592
rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev * rtwdev,s8 swing_idx,s8 txagc_idx)1593 static void rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1594 s8 txagc_idx)
1595 {
1596 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1597
1598 dm_info->txagc_remnant_cck = txagc_idx;
1599
1600 swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1);
1601
1602 BUILD_BUG_ON(ARRAY_SIZE(rtw8703b_cck_pwr_regs)
1603 != ARRAY_SIZE(rtw8703b_cck_swing_table[0]));
1604
1605 for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++)
1606 rtw_write8(rtwdev, rtw8703b_cck_pwr_regs[i],
1607 rtw8703b_cck_swing_table[swing_idx][i]);
1608 }
1609
rtw8703b_pwrtrack_set(struct rtw_dev * rtwdev,u8 path)1610 static void rtw8703b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1611 {
1612 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1613 struct rtw_hal *hal = &rtwdev->hal;
1614 u8 limit_ofdm;
1615 u8 limit_cck = 21;
1616 s8 final_ofdm_swing_index;
1617 s8 final_cck_swing_index;
1618
1619 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev);
1620
1621 final_ofdm_swing_index = dm_info->default_ofdm_index +
1622 dm_info->delta_power_index[path];
1623 final_cck_swing_index = dm_info->default_cck_index +
1624 dm_info->delta_power_index[path];
1625
1626 if (final_ofdm_swing_index > limit_ofdm)
1627 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm,
1628 final_ofdm_swing_index - limit_ofdm);
1629 else if (final_ofdm_swing_index < 0)
1630 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0,
1631 final_ofdm_swing_index);
1632 else
1633 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);
1634
1635 if (final_cck_swing_index > limit_cck)
1636 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, limit_cck,
1637 final_cck_swing_index - limit_cck);
1638 else if (final_cck_swing_index < 0)
1639 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0,
1640 final_cck_swing_index);
1641 else
1642 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);
1643
1644 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel);
1645 }
1646
rtw8703b_phy_pwrtrack(struct rtw_dev * rtwdev)1647 static void rtw8703b_phy_pwrtrack(struct rtw_dev *rtwdev)
1648 {
1649 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1650 struct rtw_swing_table swing_table;
1651 u8 thermal_value, delta, path;
1652 bool do_iqk = false;
1653
1654 rtw_phy_config_swing_table(rtwdev, &swing_table);
1655
1656 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1657 return;
1658
1659 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1660
1661 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1662
1663 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev);
1664
1665 if (do_iqk)
1666 rtw8723x_lck(rtwdev);
1667
1668 if (dm_info->pwr_trk_init_trigger)
1669 dm_info->pwr_trk_init_trigger = false;
1670 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1671 RF_PATH_A))
1672 goto iqk;
1673
1674 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1675
1676 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1677
1678 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1679 s8 delta_cur, delta_last;
1680
1681 delta_last = dm_info->delta_power_index[path];
1682 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table,
1683 path, RF_PATH_A, delta);
1684 if (delta_last == delta_cur)
1685 continue;
1686
1687 dm_info->delta_power_index[path] = delta_cur;
1688 rtw8703b_pwrtrack_set(rtwdev, path);
1689 }
1690
1691 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta);
1692
1693 iqk:
1694 if (do_iqk)
1695 rtw8703b_phy_calibration(rtwdev);
1696 }
1697
rtw8703b_pwr_track(struct rtw_dev * rtwdev)1698 static void rtw8703b_pwr_track(struct rtw_dev *rtwdev)
1699 {
1700 struct rtw_efuse *efuse = &rtwdev->efuse;
1701 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1702
1703 if (efuse->power_track_type != 0) {
1704 rtw_warn(rtwdev, "unsupported power track type");
1705 return;
1706 }
1707
1708 if (!dm_info->pwr_trk_triggered) {
1709 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1710 GENMASK(17, 16), 0x03);
1711 dm_info->pwr_trk_triggered = true;
1712 return;
1713 }
1714
1715 rtw8703b_phy_pwrtrack(rtwdev);
1716 dm_info->pwr_trk_triggered = false;
1717 }
1718
rtw8703b_coex_set_gnt_fix(struct rtw_dev * rtwdev)1719 static void rtw8703b_coex_set_gnt_fix(struct rtw_dev *rtwdev)
1720 {
1721 }
1722
rtw8703b_coex_set_gnt_debug(struct rtw_dev * rtwdev)1723 static void rtw8703b_coex_set_gnt_debug(struct rtw_dev *rtwdev)
1724 {
1725 }
1726
rtw8703b_coex_set_rfe_type(struct rtw_dev * rtwdev)1727 static void rtw8703b_coex_set_rfe_type(struct rtw_dev *rtwdev)
1728 {
1729 struct rtw_coex *coex = &rtwdev->coex;
1730 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1731
1732 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1733 coex_rfe->ant_switch_polarity = 0;
1734 coex_rfe->ant_switch_exist = false;
1735 coex_rfe->ant_switch_with_bt = false;
1736 coex_rfe->ant_switch_diversity = false;
1737 coex_rfe->wlg_at_btg = true;
1738
1739 /* disable LTE coex on wifi side */
1740 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
1741 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1742 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1743 }
1744
rtw8703b_coex_set_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)1745 static void rtw8703b_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1746 {
1747 }
1748
rtw8703b_coex_set_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)1749 static void rtw8703b_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1750 {
1751 }
1752
1753 static const u8 rtw8703b_pwrtrk_2gb_n[] = {
1754 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1755 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1756 };
1757
1758 static const u8 rtw8703b_pwrtrk_2gb_p[] = {
1759 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1760 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15
1761 };
1762
1763 static const u8 rtw8703b_pwrtrk_2ga_n[] = {
1764 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1765 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1766 };
1767
1768 static const u8 rtw8703b_pwrtrk_2ga_p[] = {
1769 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1770 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15
1771 };
1772
1773 static const u8 rtw8703b_pwrtrk_2g_cck_b_n[] = {
1774 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1775 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1776 };
1777
1778 static const u8 rtw8703b_pwrtrk_2g_cck_b_p[] = {
1779 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1780 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13
1781 };
1782
1783 static const u8 rtw8703b_pwrtrk_2g_cck_a_n[] = {
1784 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1785 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1786 };
1787
1788 static const u8 rtw8703b_pwrtrk_2g_cck_a_p[] = {
1789 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1790 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13
1791 };
1792
1793 static const s8 rtw8703b_pwrtrk_xtal_n[] = {
1794 0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3,
1795 -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1
1796 };
1797
1798 static const s8 rtw8703b_pwrtrk_xtal_p[] = {
1799 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1,
1800 -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30
1801 };
1802
1803 static const struct rtw_pwr_track_tbl rtw8703b_rtw_pwr_track_tbl = {
1804 .pwrtrk_2gb_n = rtw8703b_pwrtrk_2gb_n,
1805 .pwrtrk_2gb_p = rtw8703b_pwrtrk_2gb_p,
1806 .pwrtrk_2ga_n = rtw8703b_pwrtrk_2ga_n,
1807 .pwrtrk_2ga_p = rtw8703b_pwrtrk_2ga_p,
1808 .pwrtrk_2g_cckb_n = rtw8703b_pwrtrk_2g_cck_b_n,
1809 .pwrtrk_2g_cckb_p = rtw8703b_pwrtrk_2g_cck_b_p,
1810 .pwrtrk_2g_ccka_n = rtw8703b_pwrtrk_2g_cck_a_n,
1811 .pwrtrk_2g_ccka_p = rtw8703b_pwrtrk_2g_cck_a_p,
1812 .pwrtrk_xtal_n = rtw8703b_pwrtrk_xtal_n,
1813 .pwrtrk_xtal_p = rtw8703b_pwrtrk_xtal_p,
1814 };
1815
1816 static const struct rtw_rfe_def rtw8703b_rfe_defs[] = {
1817 [0] = { .phy_pg_tbl = &rtw8703b_bb_pg_tbl,
1818 .txpwr_lmt_tbl = &rtw8703b_txpwr_lmt_tbl,
1819 .pwr_track_tbl = &rtw8703b_rtw_pwr_track_tbl, },
1820 };
1821
1822 /* Shared-Antenna Coex Table */
1823 static const struct coex_table_para table_sant_8703b[] = {
1824 {0xffffffff, 0xffffffff}, /* case-0 */
1825 {0x55555555, 0x55555555},
1826 {0x66555555, 0x66555555},
1827 {0xaaaaaaaa, 0xaaaaaaaa},
1828 {0x5a5a5a5a, 0x5a5a5a5a},
1829 {0xfafafafa, 0xfafafafa}, /* case-5 */
1830 {0x6a5a5555, 0xaaaaaaaa},
1831 {0x6a5a56aa, 0x6a5a56aa},
1832 {0x6a5a5a5a, 0x6a5a5a5a},
1833 {0x66555555, 0x5a5a5a5a},
1834 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1835 {0x66555555, 0x6a5a5aaa},
1836 {0x66555555, 0x5a5a5aaa},
1837 {0x66555555, 0x6aaa5aaa},
1838 {0x66555555, 0xaaaa5aaa},
1839 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1840 {0xffff55ff, 0xfafafafa},
1841 {0xffff55ff, 0x6afa5afa},
1842 {0xaaffffaa, 0xfafafafa},
1843 {0xaa5555aa, 0x5a5a5a5a},
1844 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1845 {0xaa5555aa, 0xaaaaaaaa},
1846 {0xffffffff, 0x5a5a5a5a},
1847 {0xffffffff, 0x5a5a5a5a},
1848 {0xffffffff, 0x55555555},
1849 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1850 {0x55555555, 0x5a5a5a5a},
1851 {0x55555555, 0xaaaaaaaa},
1852 {0x55555555, 0x6a5a6a5a},
1853 {0x66556655, 0x66556655},
1854 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1855 {0xffffffff, 0x5aaa5aaa},
1856 {0x56555555, 0x5a5a5aaa},
1857 };
1858
1859 /* Shared-Antenna TDMA */
1860 static const struct coex_tdma_para tdma_sant_8703b[] = {
1861 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1862 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1863 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1864 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1865 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1866 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1867 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1868 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1869 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1870 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1871 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1872 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1873 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1874 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1875 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1876 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1877 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1878 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1879 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1880 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1881 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1882 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1883 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1884 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1885 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1886 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1887 { {0x51, 0x08, 0x03, 0x10, 0x50} },
1888 { {0x61, 0x08, 0x03, 0x11, 0x11} },
1889 };
1890
1891 static const struct rtw_chip_ops rtw8703b_ops = {
1892 .power_on = rtw_power_on,
1893 .power_off = rtw_power_off,
1894 .mac_init = rtw8723x_mac_init,
1895 .dump_fw_crash = NULL,
1896 .shutdown = NULL,
1897 .read_efuse = rtw8703b_read_efuse,
1898 .phy_set_param = rtw8703b_phy_set_param,
1899 .set_channel = rtw8703b_set_channel,
1900 .query_phy_status = query_phy_status,
1901 .read_rf = rtw_phy_read_rf_sipi,
1902 .write_rf = rtw_phy_write_rf_reg_sipi,
1903 .set_tx_power_index = rtw8723x_set_tx_power_index,
1904 .set_antenna = NULL,
1905 .cfg_ldo25 = rtw8723x_cfg_ldo25,
1906 .efuse_grant = rtw8723x_efuse_grant,
1907 .false_alarm_statistics = rtw8723x_false_alarm_statistics,
1908 .phy_calibration = rtw8703b_phy_calibration,
1909 .dpk_track = NULL,
1910 /* 8723d uses REG_CSRATIO to set dm_info.cck_pd_default, which
1911 * is used in its cck_pd_set function. According to comments
1912 * in the vendor driver code it doesn't exist in this chip
1913 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only
1914 * *written* to).
1915 */
1916 .cck_pd_set = NULL,
1917 .pwr_track = rtw8703b_pwr_track,
1918 .config_bfee = NULL,
1919 .set_gid_table = NULL,
1920 .cfg_csi_rate = NULL,
1921 .adaptivity_init = NULL,
1922 .adaptivity = NULL,
1923 .cfo_init = NULL,
1924 .cfo_track = NULL,
1925 .config_tx_path = NULL,
1926 .config_txrx_mode = NULL,
1927 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum,
1928
1929 /* for coex */
1930 .coex_set_init = rtw8723x_coex_cfg_init,
1931 .coex_set_ant_switch = NULL,
1932 .coex_set_gnt_fix = rtw8703b_coex_set_gnt_fix,
1933 .coex_set_gnt_debug = rtw8703b_coex_set_gnt_debug,
1934 .coex_set_rfe_type = rtw8703b_coex_set_rfe_type,
1935 .coex_set_wl_tx_power = rtw8703b_coex_set_wl_tx_power,
1936 .coex_set_wl_rx_gain = rtw8703b_coex_set_wl_rx_gain,
1937 };
1938
1939 const struct rtw_chip_info rtw8703b_hw_spec = {
1940 .ops = &rtw8703b_ops,
1941 .id = RTW_CHIP_TYPE_8703B,
1942
1943 .fw_name = "rtw88/rtw8703b_fw.bin",
1944 .wlan_cpu = RTW_WCPU_11N,
1945 .tx_pkt_desc_sz = 40,
1946 .tx_buf_desc_sz = 16,
1947 .rx_pkt_desc_sz = 24,
1948 .rx_buf_desc_sz = 8,
1949 .phy_efuse_size = 256,
1950 .log_efuse_size = 512,
1951 .ptct_efuse_size = 15,
1952 .txff_size = 32768,
1953 .rxff_size = 16384,
1954 .rsvd_drv_pg_num = 8,
1955 .band = RTW_BAND_2G,
1956 .page_size = TX_PAGE_SIZE,
1957 .csi_buf_pg_num = 0,
1958 .dig_min = 0x20,
1959 .txgi_factor = 1,
1960 .is_pwr_by_rate_dec = true,
1961 .rx_ldpc = false,
1962 .tx_stbc = false,
1963 .max_power_index = 0x3f,
1964 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1965 .usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */
1966 .hw_feature_report = true,
1967 .c2h_ra_report_size = 7,
1968 .old_datarate_fb_limit = true,
1969
1970 .path_div_supported = false,
1971 .ht_supported = true,
1972 .vht_supported = false,
1973 .lps_deep_mode_supported = 0,
1974
1975 .sys_func_en = 0xFD,
1976 .pwr_on_seq = card_enable_flow_8703b,
1977 .pwr_off_seq = card_disable_flow_8703b,
1978 .rqpn_table = rqpn_table_8703b,
1979 .prioq_addrs = &rtw8723x_common.prioq_addrs,
1980 .page_table = page_table_8703b,
1981 /* used only in pci.c, not needed for SDIO devices */
1982 .intf_table = NULL,
1983
1984 .dig = rtw8723x_common.dig,
1985 .dig_cck = rtw8723x_common.dig_cck,
1986
1987 .rf_sipi_addr = {0x840, 0x844},
1988 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr,
1989 .fix_rf_phy_num = 2,
1990 .ltecoex_addr = &rtw8723x_common.ltecoex_addr,
1991
1992 .mac_tbl = &rtw8703b_mac_tbl,
1993 .agc_tbl = &rtw8703b_agc_tbl,
1994 .bb_tbl = &rtw8703b_bb_tbl,
1995 .rf_tbl = {&rtw8703b_rf_a_tbl},
1996
1997 .rfe_defs = rtw8703b_rfe_defs,
1998 .rfe_defs_size = ARRAY_SIZE(rtw8703b_rfe_defs),
1999
2000 .iqk_threshold = 8,
2001
2002 /* WOWLAN firmware exists, but not implemented yet */
2003 .wow_fw_name = "rtw88/rtw8703b_wow_fw.bin",
2004 .wowlan_stub = NULL,
2005 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2006
2007 /* Vendor driver has a time-based format, converted from
2008 * 20180330
2009 */
2010 .coex_para_ver = 0x0133ed6a,
2011 .bt_desired_ver = 0x1c,
2012 .scbd_support = true,
2013 .new_scbd10_def = true,
2014 .ble_hid_profile_support = false,
2015 .wl_mimo_ps_support = false,
2016 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2017 .bt_rssi_type = COEX_BTRSSI_RATIO,
2018 .ant_isolation = 15,
2019 .rssi_tolerance = 2,
2020 .bt_rssi_step = bt_rssi_step_8703b,
2021 .wl_rssi_step = wl_rssi_step_8703b,
2022 /* sant -> shared antenna, nsant -> non-shared antenna
2023 * Not sure if 8703b versions with non-shard antenna even exist.
2024 */
2025 .table_sant_num = ARRAY_SIZE(table_sant_8703b),
2026 .table_sant = table_sant_8703b,
2027 .table_nsant_num = 0,
2028 .table_nsant = NULL,
2029 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8703b),
2030 .tdma_sant = tdma_sant_8703b,
2031 .tdma_nsant_num = 0,
2032 .tdma_nsant = NULL,
2033 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8703b),
2034 .wl_rf_para_tx = rf_para_tx_8703b,
2035 .wl_rf_para_rx = rf_para_rx_8703b,
2036 .bt_afh_span_bw20 = 0x20,
2037 .bt_afh_span_bw40 = 0x30,
2038 .afh_5g_num = ARRAY_SIZE(afh_5g_8703b),
2039 .afh_5g = afh_5g_8703b,
2040 /* REG_BTG_SEL doesn't seem to have a counterpart in the
2041 * vendor driver. Mathematically it's REG_PAD_CTRL1 + 3.
2042 *
2043 * It is used in the cardemu_to_act power sequence by though
2044 * (by address, 0x0067), comment: "0x67[0] = 0 to disable
2045 * BT_GPS_SEL pins" That seems to fit.
2046 */
2047 .btg_reg = NULL,
2048 /* These registers are used to read (and print) from if
2049 * CONFIG_RTW88_DEBUGFS is enabled.
2050 */
2051 .coex_info_hw_regs_num = 0,
2052 .coex_info_hw_regs = NULL,
2053 };
2054 EXPORT_SYMBOL(rtw8703b_hw_spec);
2055
2056 MODULE_FIRMWARE("rtw88/rtw8703b_fw.bin");
2057 MODULE_FIRMWARE("rtw88/rtw8703b_wow_fw.bin");
2058
2059 MODULE_AUTHOR("Fiona Klute <[email protected]>");
2060 MODULE_DESCRIPTION("Realtek 802.11n wireless 8703b driver");
2061 MODULE_LICENSE("Dual BSD/GPL");
2062