1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/spi/spi.h>
9 #include <linux/crc7.h>
10 #include <linux/crc-itu-t.h>
11 #include <linux/gpio/consumer.h>
12
13 #include "netdev.h"
14 #include "cfg80211.h"
15
16 #define SPI_MODALIAS "wilc1000_spi"
17
18 static bool enable_crc7; /* protect SPI commands with CRC7 */
19 module_param(enable_crc7, bool, 0644);
20 MODULE_PARM_DESC(enable_crc7,
21 "Enable CRC7 checksum to protect command transfers\n"
22 "\t\t\tagainst corruption during the SPI transfer.\n"
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
24 "\t\t\tof enabling this is small.");
25
26 static bool enable_crc16; /* protect SPI data with CRC16 */
27 module_param(enable_crc16, bool, 0644);
28 MODULE_PARM_DESC(enable_crc16,
29 "Enable CRC16 checksum to protect data transfers\n"
30 "\t\t\tagainst corruption during the SPI transfer.\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
32 "\t\t\tof enabling this may be substantial.");
33
34 /*
35 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or
36 * more zero bytes between the command response and the DATA Start tag
37 * (0xf3). This behavior appears to be undocumented in "ATWILC1000
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
39 * zero bytes when the SPI bus operates at 48MHz and none when it
40 * operates at 1MHz.
41 */
42 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8
43
44 struct wilc_spi {
45 bool isinit; /* true if wilc_spi_init was successful */
46 bool probing_crc; /* true if we're probing chip's CRC config */
47 bool crc7_enabled; /* true if crc7 is currently enabled */
48 bool crc16_enabled; /* true if crc16 is currently enabled */
49 struct wilc_gpios {
50 struct gpio_desc *enable; /* ENABLE GPIO or NULL */
51 struct gpio_desc *reset; /* RESET GPIO or NULL */
52 } gpios;
53 };
54
55 static const struct wilc_hif_func wilc_hif_spi;
56
57 static int wilc_spi_reset(struct wilc *wilc);
58 static int wilc_spi_configure_bus_protocol(struct wilc *wilc);
59 static int wilc_validate_chipid(struct wilc *wilc);
60
61 /********************************************
62 *
63 * Spi protocol Function
64 *
65 ********************************************/
66
67 #define CMD_DMA_WRITE 0xc1
68 #define CMD_DMA_READ 0xc2
69 #define CMD_INTERNAL_WRITE 0xc3
70 #define CMD_INTERNAL_READ 0xc4
71 #define CMD_TERMINATE 0xc5
72 #define CMD_REPEAT 0xc6
73 #define CMD_DMA_EXT_WRITE 0xc7
74 #define CMD_DMA_EXT_READ 0xc8
75 #define CMD_SINGLE_WRITE 0xc9
76 #define CMD_SINGLE_READ 0xca
77 #define CMD_RESET 0xcf
78
79 #define SPI_RETRY_MAX_LIMIT 10
80 #define SPI_ENABLE_VMM_RETRY_LIMIT 2
81
82 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
83 #define RSP_START_FIELD GENMASK(7, 4)
84 #define RSP_TYPE_FIELD GENMASK(3, 0)
85
86 /* SPI response values for the response fields: */
87 #define RSP_START_TAG 0xc
88 #define RSP_TYPE_FIRST_PACKET 0x1
89 #define RSP_TYPE_INNER_PACKET 0x2
90 #define RSP_TYPE_LAST_PACKET 0x3
91 #define RSP_STATE_NO_ERROR 0x00
92
93 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4)
94 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3)
95 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2)
96
97 /*
98 * The SPI data packet size may be any integer power of two in the
99 * range from 256 to 8192 bytes.
100 */
101 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */
102 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */
103
104 /*
105 * Select the data packet size (log2 of number of bytes): Use the
106 * maximum data packet size. We only retransmit complete packets, so
107 * there is no benefit from using smaller data packets.
108 */
109 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX
110 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ)
111
112 #define WILC_SPI_COMMAND_STAT_SUCCESS 0
113 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf)
114
115 struct wilc_spi_cmd {
116 u8 cmd_type;
117 union {
118 struct {
119 u8 addr[3];
120 u8 crc[];
121 } __packed simple_cmd;
122 struct {
123 u8 addr[3];
124 u8 size[2];
125 u8 crc[];
126 } __packed dma_cmd;
127 struct {
128 u8 addr[3];
129 u8 size[3];
130 u8 crc[];
131 } __packed dma_cmd_ext;
132 struct {
133 u8 addr[2];
134 __be32 data;
135 u8 crc[];
136 } __packed internal_w_cmd;
137 struct {
138 u8 addr[3];
139 __be32 data;
140 u8 crc[];
141 } __packed w_cmd;
142 } u;
143 } __packed;
144
145 struct wilc_spi_read_rsp_data {
146 u8 header;
147 u8 data[4];
148 u8 crc[];
149 } __packed;
150
151 struct wilc_spi_rsp_data {
152 u8 rsp_cmd_type;
153 u8 status;
154 u8 data[];
155 } __packed;
156
157 struct wilc_spi_special_cmd_rsp {
158 u8 skip_byte;
159 u8 rsp_cmd_type;
160 u8 status;
161 } __packed;
162
wilc_parse_gpios(struct wilc * wilc)163 static int wilc_parse_gpios(struct wilc *wilc)
164 {
165 struct spi_device *spi = to_spi_device(wilc->dev);
166 struct wilc_spi *spi_priv = wilc->bus_data;
167 struct wilc_gpios *gpios = &spi_priv->gpios;
168
169 /* get ENABLE pin and deassert it (if it is defined): */
170 gpios->enable = devm_gpiod_get_optional(&spi->dev,
171 "enable", GPIOD_OUT_LOW);
172 /* get RESET pin and assert it (if it is defined): */
173 if (gpios->enable) {
174 /* if enable pin exists, reset must exist as well */
175 gpios->reset = devm_gpiod_get(&spi->dev,
176 "reset", GPIOD_OUT_HIGH);
177 if (IS_ERR(gpios->reset)) {
178 dev_err(&spi->dev, "missing reset gpio.\n");
179 return PTR_ERR(gpios->reset);
180 }
181 } else {
182 gpios->reset = devm_gpiod_get_optional(&spi->dev,
183 "reset", GPIOD_OUT_HIGH);
184 }
185 return 0;
186 }
187
wilc_wlan_power(struct wilc * wilc,bool on)188 static void wilc_wlan_power(struct wilc *wilc, bool on)
189 {
190 struct wilc_spi *spi_priv = wilc->bus_data;
191 struct wilc_gpios *gpios = &spi_priv->gpios;
192
193 if (on) {
194 /* assert ENABLE: */
195 gpiod_set_value(gpios->enable, 1);
196 mdelay(5);
197 /* deassert RESET: */
198 gpiod_set_value(gpios->reset, 0);
199 } else {
200 /* assert RESET: */
201 gpiod_set_value(gpios->reset, 1);
202 /* deassert ENABLE: */
203 gpiod_set_value(gpios->enable, 0);
204 }
205 }
206
wilc_bus_probe(struct spi_device * spi)207 static int wilc_bus_probe(struct spi_device *spi)
208 {
209 struct wilc_spi *spi_priv;
210 struct wilc_vif *vif;
211 struct wilc *wilc;
212 int ret;
213
214 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
215 if (!spi_priv)
216 return -ENOMEM;
217
218 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
219 if (ret)
220 goto free;
221
222 spi_set_drvdata(spi, wilc);
223 wilc->dev = &spi->dev;
224 wilc->bus_data = spi_priv;
225 wilc->dev_irq_num = spi->irq;
226
227 ret = wilc_parse_gpios(wilc);
228 if (ret < 0)
229 goto netdev_cleanup;
230
231 wilc->rtc_clk = devm_clk_get_optional_enabled(&spi->dev, "rtc");
232 if (IS_ERR(wilc->rtc_clk)) {
233 ret = PTR_ERR(wilc->rtc_clk);
234 goto netdev_cleanup;
235 }
236
237 dev_info(&spi->dev, "Selected CRC config: crc7=%s, crc16=%s\n",
238 enable_crc7 ? "on" : "off", enable_crc16 ? "on" : "off");
239
240 /* we need power to configure the bus protocol and to read the chip id: */
241
242 wilc_wlan_power(wilc, true);
243
244 ret = wilc_spi_configure_bus_protocol(wilc);
245 if (ret)
246 goto power_down;
247
248 ret = wilc_get_chipid(wilc);
249 if (ret)
250 goto power_down;
251
252 ret = wilc_cfg80211_register(wilc);
253 if (ret)
254 goto power_down;
255
256 ret = wilc_load_mac_from_nv(wilc);
257 if (ret) {
258 pr_err("Can not retrieve MAC address from chip\n");
259 goto unregister_wiphy;
260 }
261
262 wilc_wlan_power(wilc, false);
263 vif = wilc_netdev_ifc_init(wilc, "wlan%d", WILC_STATION_MODE,
264 NL80211_IFTYPE_STATION, false);
265 if (IS_ERR(vif)) {
266 ret = PTR_ERR(vif);
267 goto unregister_wiphy;
268 }
269 return 0;
270
271 unregister_wiphy:
272 wiphy_unregister(wilc->wiphy);
273 power_down:
274 wilc_wlan_power(wilc, false);
275 netdev_cleanup:
276 wilc_netdev_cleanup(wilc);
277 wiphy_free(wilc->wiphy);
278 free:
279 kfree(spi_priv);
280 return ret;
281 }
282
wilc_bus_remove(struct spi_device * spi)283 static void wilc_bus_remove(struct spi_device *spi)
284 {
285 struct wilc *wilc = spi_get_drvdata(spi);
286 struct wilc_spi *spi_priv = wilc->bus_data;
287
288 wilc_netdev_cleanup(wilc);
289 wiphy_unregister(wilc->wiphy);
290 wiphy_free(wilc->wiphy);
291 kfree(spi_priv);
292 }
293
294 static const struct of_device_id wilc_of_match[] = {
295 { .compatible = "microchip,wilc1000", },
296 { /* sentinel */ }
297 };
298 MODULE_DEVICE_TABLE(of, wilc_of_match);
299
300 static const struct spi_device_id wilc_spi_id[] = {
301 { "wilc1000", 0 },
302 { /* sentinel */ }
303 };
304 MODULE_DEVICE_TABLE(spi, wilc_spi_id);
305
306 static struct spi_driver wilc_spi_driver = {
307 .driver = {
308 .name = SPI_MODALIAS,
309 .of_match_table = wilc_of_match,
310 },
311 .id_table = wilc_spi_id,
312 .probe = wilc_bus_probe,
313 .remove = wilc_bus_remove,
314 };
315 module_spi_driver(wilc_spi_driver);
316 MODULE_DESCRIPTION("Atmel WILC1000 SPI wireless driver");
317 MODULE_LICENSE("GPL");
318
wilc_spi_tx(struct wilc * wilc,u8 * b,u32 len)319 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
320 {
321 struct spi_device *spi = to_spi_device(wilc->dev);
322 int ret;
323 struct spi_message msg;
324
325 if (len > 0 && b) {
326 struct spi_transfer tr = {
327 .tx_buf = b,
328 .len = len,
329 .delay = {
330 .value = 0,
331 .unit = SPI_DELAY_UNIT_USECS
332 },
333 };
334 char *r_buffer = kzalloc(len, GFP_KERNEL);
335
336 if (!r_buffer)
337 return -ENOMEM;
338
339 tr.rx_buf = r_buffer;
340 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
341
342 memset(&msg, 0, sizeof(msg));
343 spi_message_init(&msg);
344 spi_message_add_tail(&tr, &msg);
345
346 ret = spi_sync(spi, &msg);
347 if (ret < 0)
348 dev_err(&spi->dev, "SPI transaction failed\n");
349
350 kfree(r_buffer);
351 } else {
352 dev_err(&spi->dev,
353 "can't write data with the following length: %d\n",
354 len);
355 ret = -EINVAL;
356 }
357
358 return ret;
359 }
360
wilc_spi_rx(struct wilc * wilc,u8 * rb,u32 rlen)361 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
362 {
363 struct spi_device *spi = to_spi_device(wilc->dev);
364 int ret;
365
366 if (rlen > 0) {
367 struct spi_message msg;
368 struct spi_transfer tr = {
369 .rx_buf = rb,
370 .len = rlen,
371 .delay = {
372 .value = 0,
373 .unit = SPI_DELAY_UNIT_USECS
374 },
375
376 };
377 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
378
379 if (!t_buffer)
380 return -ENOMEM;
381
382 tr.tx_buf = t_buffer;
383
384 memset(&msg, 0, sizeof(msg));
385 spi_message_init(&msg);
386 spi_message_add_tail(&tr, &msg);
387
388 ret = spi_sync(spi, &msg);
389 if (ret < 0)
390 dev_err(&spi->dev, "SPI transaction failed\n");
391 kfree(t_buffer);
392 } else {
393 dev_err(&spi->dev,
394 "can't read data with the following length: %u\n",
395 rlen);
396 ret = -EINVAL;
397 }
398
399 return ret;
400 }
401
wilc_spi_tx_rx(struct wilc * wilc,u8 * wb,u8 * rb,u32 rlen)402 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
403 {
404 struct spi_device *spi = to_spi_device(wilc->dev);
405 int ret;
406
407 if (rlen > 0) {
408 struct spi_message msg;
409 struct spi_transfer tr = {
410 .rx_buf = rb,
411 .tx_buf = wb,
412 .len = rlen,
413 .bits_per_word = 8,
414 .delay = {
415 .value = 0,
416 .unit = SPI_DELAY_UNIT_USECS
417 },
418
419 };
420
421 memset(&msg, 0, sizeof(msg));
422 spi_message_init(&msg);
423 spi_message_add_tail(&tr, &msg);
424 ret = spi_sync(spi, &msg);
425 if (ret < 0)
426 dev_err(&spi->dev, "SPI transaction failed\n");
427 } else {
428 dev_err(&spi->dev,
429 "can't read data with the following length: %u\n",
430 rlen);
431 ret = -EINVAL;
432 }
433
434 return ret;
435 }
436
spi_data_write(struct wilc * wilc,u8 * b,u32 sz)437 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
438 {
439 struct spi_device *spi = to_spi_device(wilc->dev);
440 struct wilc_spi *spi_priv = wilc->bus_data;
441 int ix, nbytes;
442 int result = 0;
443 u8 cmd, order, crc[2];
444 u16 crc_calc;
445
446 /*
447 * Data
448 */
449 ix = 0;
450 do {
451 if (sz <= DATA_PKT_SZ) {
452 nbytes = sz;
453 order = 0x3;
454 } else {
455 nbytes = DATA_PKT_SZ;
456 if (ix == 0)
457 order = 0x1;
458 else
459 order = 0x02;
460 }
461
462 /*
463 * Write command
464 */
465 cmd = 0xf0;
466 cmd |= order;
467
468 if (wilc_spi_tx(wilc, &cmd, 1)) {
469 dev_err(&spi->dev,
470 "Failed data block cmd write, bus error...\n");
471 result = -EINVAL;
472 break;
473 }
474
475 /*
476 * Write data
477 */
478 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
479 dev_err(&spi->dev,
480 "Failed data block write, bus error...\n");
481 result = -EINVAL;
482 break;
483 }
484
485 /*
486 * Write CRC
487 */
488 if (spi_priv->crc16_enabled) {
489 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
490 crc[0] = crc_calc >> 8;
491 crc[1] = crc_calc;
492 if (wilc_spi_tx(wilc, crc, 2)) {
493 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
494 result = -EINVAL;
495 break;
496 }
497 }
498
499 /*
500 * No need to wait for response
501 */
502 ix += nbytes;
503 sz -= nbytes;
504 } while (sz);
505
506 return result;
507 }
508
509 /********************************************
510 *
511 * Spi Internal Read/Write Function
512 *
513 ********************************************/
wilc_get_crc7(u8 * buffer,u32 len)514 static u8 wilc_get_crc7(u8 *buffer, u32 len)
515 {
516 return crc7_be(0xfe, buffer, len) | 0x01;
517 }
518
wilc_spi_single_read(struct wilc * wilc,u8 cmd,u32 adr,void * b,u8 clockless)519 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
520 u8 clockless)
521 {
522 struct spi_device *spi = to_spi_device(wilc->dev);
523 struct wilc_spi *spi_priv = wilc->bus_data;
524 u8 wb[32], rb[32];
525 int cmd_len, resp_len, i;
526 u16 crc_calc, crc_recv;
527 struct wilc_spi_cmd *c;
528 struct wilc_spi_rsp_data *r;
529 struct wilc_spi_read_rsp_data *r_data;
530
531 memset(wb, 0x0, sizeof(wb));
532 memset(rb, 0x0, sizeof(rb));
533 c = (struct wilc_spi_cmd *)wb;
534 c->cmd_type = cmd;
535 if (cmd == CMD_SINGLE_READ) {
536 c->u.simple_cmd.addr[0] = adr >> 16;
537 c->u.simple_cmd.addr[1] = adr >> 8;
538 c->u.simple_cmd.addr[2] = adr;
539 } else if (cmd == CMD_INTERNAL_READ) {
540 c->u.simple_cmd.addr[0] = adr >> 8;
541 if (clockless == 1)
542 c->u.simple_cmd.addr[0] |= BIT(7);
543 c->u.simple_cmd.addr[1] = adr;
544 c->u.simple_cmd.addr[2] = 0x0;
545 } else {
546 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
547 return -EINVAL;
548 }
549
550 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
551 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA;
552
553 if (spi_priv->crc7_enabled) {
554 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
555 cmd_len += 1;
556 resp_len += 2;
557 }
558
559 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
560 dev_err(&spi->dev,
561 "spi buffer size too small (%d) (%d) (%zu)\n",
562 cmd_len, resp_len, ARRAY_SIZE(wb));
563 return -EINVAL;
564 }
565
566 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
567 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
568 return -EINVAL;
569 }
570
571 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
572 if (r->rsp_cmd_type != cmd && !clockless) {
573 if (!spi_priv->probing_crc)
574 dev_err(&spi->dev,
575 "Failed cmd, cmd (%02x), resp (%02x)\n",
576 cmd, r->rsp_cmd_type);
577 return -EINVAL;
578 }
579
580 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
581 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
582 r->status);
583 return -EINVAL;
584 }
585
586 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i)
587 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf)
588 break;
589
590 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) {
591 dev_err(&spi->dev, "Error, data start missing\n");
592 return -EINVAL;
593 }
594
595 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i];
596
597 if (b)
598 memcpy(b, r_data->data, 4);
599
600 if (!clockless && spi_priv->crc16_enabled) {
601 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1];
602 crc_calc = crc_itu_t(0xffff, r_data->data, 4);
603 if (crc_recv != crc_calc) {
604 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
605 "(calculated 0x%04x)\n", __func__,
606 crc_recv, crc_calc);
607 return -EINVAL;
608 }
609 }
610
611 return 0;
612 }
613
wilc_spi_write_cmd(struct wilc * wilc,u8 cmd,u32 adr,u32 data,u8 clockless)614 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
615 u8 clockless)
616 {
617 struct spi_device *spi = to_spi_device(wilc->dev);
618 struct wilc_spi *spi_priv = wilc->bus_data;
619 u8 wb[32], rb[32];
620 int cmd_len, resp_len;
621 struct wilc_spi_cmd *c;
622 struct wilc_spi_rsp_data *r;
623
624 memset(wb, 0x0, sizeof(wb));
625 memset(rb, 0x0, sizeof(rb));
626 c = (struct wilc_spi_cmd *)wb;
627 c->cmd_type = cmd;
628 if (cmd == CMD_INTERNAL_WRITE) {
629 c->u.internal_w_cmd.addr[0] = adr >> 8;
630 if (clockless == 1)
631 c->u.internal_w_cmd.addr[0] |= BIT(7);
632
633 c->u.internal_w_cmd.addr[1] = adr;
634 c->u.internal_w_cmd.data = cpu_to_be32(data);
635 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
636 if (spi_priv->crc7_enabled)
637 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
638 } else if (cmd == CMD_SINGLE_WRITE) {
639 c->u.w_cmd.addr[0] = adr >> 16;
640 c->u.w_cmd.addr[1] = adr >> 8;
641 c->u.w_cmd.addr[2] = adr;
642 c->u.w_cmd.data = cpu_to_be32(data);
643 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
644 if (spi_priv->crc7_enabled)
645 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
646 } else {
647 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
648 return -EINVAL;
649 }
650
651 if (spi_priv->crc7_enabled)
652 cmd_len += 1;
653
654 resp_len = sizeof(*r);
655
656 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
657 dev_err(&spi->dev,
658 "spi buffer size too small (%d) (%d) (%zu)\n",
659 cmd_len, resp_len, ARRAY_SIZE(wb));
660 return -EINVAL;
661 }
662
663 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
664 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
665 return -EINVAL;
666 }
667
668 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
669 /*
670 * Clockless registers operations might return unexptected responses,
671 * even if successful.
672 */
673 if (r->rsp_cmd_type != cmd && !clockless) {
674 dev_err(&spi->dev,
675 "Failed cmd response, cmd (%02x), resp (%02x)\n",
676 cmd, r->rsp_cmd_type);
677 return -EINVAL;
678 }
679
680 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
681 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
682 r->status);
683 return -EINVAL;
684 }
685
686 return 0;
687 }
688
wilc_spi_dma_rw(struct wilc * wilc,u8 cmd,u32 adr,u8 * b,u32 sz)689 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
690 {
691 struct spi_device *spi = to_spi_device(wilc->dev);
692 struct wilc_spi *spi_priv = wilc->bus_data;
693 u16 crc_recv, crc_calc;
694 u8 wb[32], rb[32];
695 int cmd_len, resp_len;
696 int retry, ix = 0;
697 u8 crc[2];
698 struct wilc_spi_cmd *c;
699 struct wilc_spi_rsp_data *r;
700
701 memset(wb, 0x0, sizeof(wb));
702 memset(rb, 0x0, sizeof(rb));
703 c = (struct wilc_spi_cmd *)wb;
704 c->cmd_type = cmd;
705 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
706 c->u.dma_cmd.addr[0] = adr >> 16;
707 c->u.dma_cmd.addr[1] = adr >> 8;
708 c->u.dma_cmd.addr[2] = adr;
709 c->u.dma_cmd.size[0] = sz >> 8;
710 c->u.dma_cmd.size[1] = sz;
711 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
712 if (spi_priv->crc7_enabled)
713 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
714 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
715 c->u.dma_cmd_ext.addr[0] = adr >> 16;
716 c->u.dma_cmd_ext.addr[1] = adr >> 8;
717 c->u.dma_cmd_ext.addr[2] = adr;
718 c->u.dma_cmd_ext.size[0] = sz >> 16;
719 c->u.dma_cmd_ext.size[1] = sz >> 8;
720 c->u.dma_cmd_ext.size[2] = sz;
721 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
722 if (spi_priv->crc7_enabled)
723 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
724 } else {
725 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
726 cmd);
727 return -EINVAL;
728 }
729 if (spi_priv->crc7_enabled)
730 cmd_len += 1;
731
732 resp_len = sizeof(*r);
733
734 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
735 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
736 cmd_len, resp_len, ARRAY_SIZE(wb));
737 return -EINVAL;
738 }
739
740 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
741 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
742 return -EINVAL;
743 }
744
745 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
746 if (r->rsp_cmd_type != cmd) {
747 dev_err(&spi->dev,
748 "Failed cmd response, cmd (%02x), resp (%02x)\n",
749 cmd, r->rsp_cmd_type);
750 return -EINVAL;
751 }
752
753 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
754 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
755 r->status);
756 return -EINVAL;
757 }
758
759 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
760 return 0;
761
762 while (sz > 0) {
763 int nbytes;
764 u8 rsp;
765
766 nbytes = min_t(u32, sz, DATA_PKT_SZ);
767
768 /*
769 * Data Response header
770 */
771 retry = 100;
772 do {
773 if (wilc_spi_rx(wilc, &rsp, 1)) {
774 dev_err(&spi->dev,
775 "Failed resp read, bus err\n");
776 return -EINVAL;
777 }
778 if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
779 break;
780 } while (retry--);
781
782 /*
783 * Read bytes
784 */
785 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
786 dev_err(&spi->dev,
787 "Failed block read, bus err\n");
788 return -EINVAL;
789 }
790
791 /*
792 * Read CRC
793 */
794 if (spi_priv->crc16_enabled) {
795 if (wilc_spi_rx(wilc, crc, 2)) {
796 dev_err(&spi->dev,
797 "Failed block CRC read, bus err\n");
798 return -EINVAL;
799 }
800 crc_recv = (crc[0] << 8) | crc[1];
801 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
802 if (crc_recv != crc_calc) {
803 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
804 "(calculated 0x%04x)\n", __func__,
805 crc_recv, crc_calc);
806 return -EINVAL;
807 }
808 }
809
810 ix += nbytes;
811 sz -= nbytes;
812 }
813 return 0;
814 }
815
wilc_spi_special_cmd(struct wilc * wilc,u8 cmd)816 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd)
817 {
818 struct spi_device *spi = to_spi_device(wilc->dev);
819 struct wilc_spi *spi_priv = wilc->bus_data;
820 u8 wb[32], rb[32];
821 int cmd_len, resp_len = 0;
822 struct wilc_spi_cmd *c;
823 struct wilc_spi_special_cmd_rsp *r;
824
825 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET)
826 return -EINVAL;
827
828 memset(wb, 0x0, sizeof(wb));
829 memset(rb, 0x0, sizeof(rb));
830 c = (struct wilc_spi_cmd *)wb;
831 c->cmd_type = cmd;
832
833 if (cmd == CMD_RESET)
834 memset(c->u.simple_cmd.addr, 0xFF, 3);
835
836 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
837 resp_len = sizeof(*r);
838
839 if (spi_priv->crc7_enabled) {
840 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
841 cmd_len += 1;
842 }
843 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
844 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n",
845 cmd_len, resp_len, ARRAY_SIZE(wb));
846 return -EINVAL;
847 }
848
849 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
850 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
851 return -EINVAL;
852 }
853
854 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len];
855 if (r->rsp_cmd_type != cmd) {
856 if (!spi_priv->probing_crc)
857 dev_err(&spi->dev,
858 "Failed cmd response, cmd (%02x), resp (%02x)\n",
859 cmd, r->rsp_cmd_type);
860 return -EINVAL;
861 }
862
863 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
864 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
865 r->status);
866 return -EINVAL;
867 }
868 return 0;
869 }
870
wilc_spi_reset_cmd_sequence(struct wilc * wl,u8 attempt,u32 addr)871 static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr)
872 {
873 struct spi_device *spi = to_spi_device(wl->dev);
874 struct wilc_spi *spi_priv = wl->bus_data;
875
876 if (!spi_priv->probing_crc)
877 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr);
878
879 usleep_range(1000, 1100);
880 wilc_spi_reset(wl);
881 usleep_range(1000, 1100);
882 }
883
wilc_spi_read_reg(struct wilc * wilc,u32 addr,u32 * data)884 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
885 {
886 struct spi_device *spi = to_spi_device(wilc->dev);
887 int result;
888 u8 cmd = CMD_SINGLE_READ;
889 u8 clockless = 0;
890 u8 i;
891
892 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
893 /* Clockless register */
894 cmd = CMD_INTERNAL_READ;
895 clockless = 1;
896 }
897
898 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
899 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
900 if (!result) {
901 le32_to_cpus(data);
902 return 0;
903 }
904
905 /* retry is not applicable for clockless registers */
906 if (clockless)
907 break;
908
909 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
910 wilc_spi_reset_cmd_sequence(wilc, i, addr);
911 }
912
913 return result;
914 }
915
wilc_spi_read(struct wilc * wilc,u32 addr,u8 * buf,u32 size)916 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
917 {
918 struct spi_device *spi = to_spi_device(wilc->dev);
919 int result;
920 u8 i;
921
922 if (size <= 4)
923 return -EINVAL;
924
925 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
926 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr,
927 buf, size);
928 if (!result)
929 return 0;
930
931 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
932
933 wilc_spi_reset_cmd_sequence(wilc, i, addr);
934 }
935
936 return result;
937 }
938
spi_internal_write(struct wilc * wilc,u32 adr,u32 dat)939 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
940 {
941 struct spi_device *spi = to_spi_device(wilc->dev);
942 int result;
943 u8 i;
944
945 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
946 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr,
947 dat, 0);
948 if (!result)
949 return 0;
950 dev_err(&spi->dev, "Failed internal write cmd...\n");
951
952 wilc_spi_reset_cmd_sequence(wilc, i, adr);
953 }
954
955 return result;
956 }
957
spi_internal_read(struct wilc * wilc,u32 adr,u32 * data)958 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
959 {
960 struct spi_device *spi = to_spi_device(wilc->dev);
961 struct wilc_spi *spi_priv = wilc->bus_data;
962 int result;
963 u8 i;
964
965 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
966 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr,
967 data, 0);
968 if (!result) {
969 le32_to_cpus(data);
970 return 0;
971 }
972 if (!spi_priv->probing_crc)
973 dev_err(&spi->dev, "Failed internal read cmd...\n");
974
975 wilc_spi_reset_cmd_sequence(wilc, i, adr);
976 }
977
978 return result;
979 }
980
981 /********************************************
982 *
983 * Spi interfaces
984 *
985 ********************************************/
986
wilc_spi_write_reg(struct wilc * wilc,u32 addr,u32 data)987 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
988 {
989 struct spi_device *spi = to_spi_device(wilc->dev);
990 int result;
991 u8 cmd = CMD_SINGLE_WRITE;
992 u8 clockless = 0;
993 u8 i;
994
995 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
996 /* Clockless register */
997 cmd = CMD_INTERNAL_WRITE;
998 clockless = 1;
999 }
1000
1001 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
1002 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
1003 if (!result)
1004 return 0;
1005
1006 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
1007
1008 if (clockless)
1009 break;
1010
1011 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1012 }
1013 return result;
1014 }
1015
spi_data_rsp(struct wilc * wilc,u8 cmd)1016 static int spi_data_rsp(struct wilc *wilc, u8 cmd)
1017 {
1018 struct spi_device *spi = to_spi_device(wilc->dev);
1019 int result, i;
1020 u8 rsp[4];
1021
1022 /*
1023 * The response to data packets is two bytes long. For
1024 * efficiency's sake, wilc_spi_write() wisely ignores the
1025 * responses for all packets but the final one. The downside
1026 * of that optimization is that when the final data packet is
1027 * short, we may receive (part of) the response to the
1028 * second-to-last packet before the one for the final packet.
1029 * To handle this, we always read 4 bytes and then search for
1030 * the last byte that contains the "Response Start" code (0xc
1031 * in the top 4 bits). We then know that this byte is the
1032 * first response byte of the final data packet.
1033 */
1034 result = wilc_spi_rx(wilc, rsp, sizeof(rsp));
1035 if (result) {
1036 dev_err(&spi->dev, "Failed bus error...\n");
1037 return result;
1038 }
1039
1040 for (i = sizeof(rsp) - 2; i >= 0; --i)
1041 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG)
1042 break;
1043
1044 if (i < 0) {
1045 dev_err(&spi->dev,
1046 "Data packet response missing (%02x %02x %02x %02x)\n",
1047 rsp[0], rsp[1], rsp[2], rsp[3]);
1048 return -1;
1049 }
1050
1051 /* rsp[i] is the last response start byte */
1052
1053 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET
1054 || rsp[i + 1] != RSP_STATE_NO_ERROR) {
1055 dev_err(&spi->dev, "Data response error (%02x %02x)\n",
1056 rsp[i], rsp[i + 1]);
1057 return -1;
1058 }
1059 return 0;
1060 }
1061
wilc_spi_write(struct wilc * wilc,u32 addr,u8 * buf,u32 size)1062 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
1063 {
1064 struct spi_device *spi = to_spi_device(wilc->dev);
1065 int result;
1066 u8 i;
1067
1068 /*
1069 * has to be greated than 4
1070 */
1071 if (size <= 4)
1072 return -EINVAL;
1073
1074 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
1075 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr,
1076 NULL, size);
1077 if (result) {
1078 dev_err(&spi->dev,
1079 "Failed cmd, write block (%08x)...\n", addr);
1080 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1081 continue;
1082 }
1083
1084 /*
1085 * Data
1086 */
1087 result = spi_data_write(wilc, buf, size);
1088 if (result) {
1089 dev_err(&spi->dev, "Failed block data write...\n");
1090 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1091 continue;
1092 }
1093
1094 /*
1095 * Data response
1096 */
1097 result = spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
1098 if (result) {
1099 dev_err(&spi->dev, "Failed block data rsp...\n");
1100 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1101 continue;
1102 }
1103 break;
1104 }
1105 return result;
1106 }
1107
1108 /********************************************
1109 *
1110 * Bus interfaces
1111 *
1112 ********************************************/
1113
wilc_spi_reset(struct wilc * wilc)1114 static int wilc_spi_reset(struct wilc *wilc)
1115 {
1116 struct spi_device *spi = to_spi_device(wilc->dev);
1117 struct wilc_spi *spi_priv = wilc->bus_data;
1118 int result;
1119
1120 result = wilc_spi_special_cmd(wilc, CMD_RESET);
1121 if (result && !spi_priv->probing_crc)
1122 dev_err(&spi->dev, "Failed cmd reset\n");
1123
1124 return result;
1125 }
1126
wilc_spi_is_init(struct wilc * wilc)1127 static bool wilc_spi_is_init(struct wilc *wilc)
1128 {
1129 struct wilc_spi *spi_priv = wilc->bus_data;
1130
1131 return spi_priv->isinit;
1132 }
1133
wilc_spi_deinit(struct wilc * wilc)1134 static int wilc_spi_deinit(struct wilc *wilc)
1135 {
1136 struct wilc_spi *spi_priv = wilc->bus_data;
1137
1138 spi_priv->isinit = false;
1139 wilc_wlan_power(wilc, false);
1140 return 0;
1141 }
1142
wilc_spi_init(struct wilc * wilc,bool resume)1143 static int wilc_spi_init(struct wilc *wilc, bool resume)
1144 {
1145 struct wilc_spi *spi_priv = wilc->bus_data;
1146 int ret;
1147
1148 if (spi_priv->isinit) {
1149 /* Confirm we can read chipid register without error: */
1150 if (wilc_validate_chipid(wilc) == 0)
1151 return 0;
1152 }
1153
1154 wilc_wlan_power(wilc, true);
1155
1156 ret = wilc_spi_configure_bus_protocol(wilc);
1157 if (ret) {
1158 wilc_wlan_power(wilc, false);
1159 return ret;
1160 }
1161
1162 spi_priv->isinit = true;
1163
1164 return 0;
1165 }
1166
wilc_spi_configure_bus_protocol(struct wilc * wilc)1167 static int wilc_spi_configure_bus_protocol(struct wilc *wilc)
1168 {
1169 struct spi_device *spi = to_spi_device(wilc->dev);
1170 struct wilc_spi *spi_priv = wilc->bus_data;
1171 u32 reg;
1172 int ret, i;
1173
1174 /*
1175 * Infer the CRC settings that are currently in effect. This
1176 * is necessary because we can't be sure that the chip has
1177 * been RESET (e.g, after module unload and reload).
1178 */
1179 spi_priv->probing_crc = true;
1180 spi_priv->crc7_enabled = enable_crc7;
1181 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */
1182 for (i = 0; i < 2; ++i) {
1183 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
1184 if (ret == 0)
1185 break;
1186 spi_priv->crc7_enabled = !enable_crc7;
1187 }
1188 if (ret) {
1189 dev_err(&spi->dev, "Failed with CRC7 on and off.\n");
1190 return ret;
1191 }
1192
1193 /* set up the desired CRC configuration: */
1194 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK);
1195 if (enable_crc7)
1196 reg |= PROTOCOL_REG_CRC7_MASK;
1197 if (enable_crc16)
1198 reg |= PROTOCOL_REG_CRC16_MASK;
1199
1200 /* set up the data packet size: */
1201 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN
1202 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX);
1203 reg &= ~PROTOCOL_REG_PKT_SZ_MASK;
1204 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK,
1205 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN);
1206
1207 /* establish the new setup: */
1208 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
1209 if (ret) {
1210 dev_err(&spi->dev,
1211 "[wilc spi %d]: Failed internal write reg\n",
1212 __LINE__);
1213 return ret;
1214 }
1215 /* update our state to match new protocol settings: */
1216 spi_priv->crc7_enabled = enable_crc7;
1217 spi_priv->crc16_enabled = enable_crc16;
1218
1219 /* re-read to make sure new settings are in effect: */
1220 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
1221
1222 spi_priv->probing_crc = false;
1223
1224 return 0;
1225 }
1226
wilc_validate_chipid(struct wilc * wilc)1227 static int wilc_validate_chipid(struct wilc *wilc)
1228 {
1229 struct spi_device *spi = to_spi_device(wilc->dev);
1230 u32 chipid;
1231 int ret;
1232
1233 /*
1234 * make sure can read chip id without protocol error
1235 */
1236 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1237 if (ret) {
1238 dev_err(&spi->dev, "Fail cmd read chip id...\n");
1239 return ret;
1240 }
1241 if (!is_wilc1000(chipid) && !is_wilc3000(chipid)) {
1242 dev_err(&spi->dev, "Unknown chip id 0x%x\n", chipid);
1243 return -ENODEV;
1244 }
1245 return 0;
1246 }
1247
wilc_spi_read_size(struct wilc * wilc,u32 * size)1248 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
1249 {
1250 int ret;
1251
1252 ret = spi_internal_read(wilc,
1253 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
1254 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
1255
1256 return ret;
1257 }
1258
wilc_spi_read_int(struct wilc * wilc,u32 * int_status)1259 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
1260 {
1261 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
1262 int_status);
1263 }
1264
wilc_spi_clear_int_ext(struct wilc * wilc,u32 val)1265 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1266 {
1267 int ret;
1268 int retry = SPI_ENABLE_VMM_RETRY_LIMIT;
1269 u32 check;
1270
1271 while (retry) {
1272 ret = spi_internal_write(wilc,
1273 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1274 val);
1275 if (ret)
1276 break;
1277
1278 ret = spi_internal_read(wilc,
1279 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1280 &check);
1281 if (ret || ((check & EN_VMM) == (val & EN_VMM)))
1282 break;
1283
1284 retry--;
1285 }
1286 return ret;
1287 }
1288
wilc_spi_sync_ext(struct wilc * wilc,int nint)1289 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1290 {
1291 struct spi_device *spi = to_spi_device(wilc->dev);
1292 u32 reg;
1293 int ret, i;
1294
1295 if (nint > MAX_NUM_INT) {
1296 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1297 return -EINVAL;
1298 }
1299
1300 /*
1301 * interrupt pin mux select
1302 */
1303 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
1304 if (ret) {
1305 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1306 WILC_PIN_MUX_0);
1307 return ret;
1308 }
1309 reg |= BIT(8);
1310 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1311 if (ret) {
1312 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1313 WILC_PIN_MUX_0);
1314 return ret;
1315 }
1316
1317 /*
1318 * interrupt enable
1319 */
1320 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
1321 if (ret) {
1322 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1323 WILC_INTR_ENABLE);
1324 return ret;
1325 }
1326
1327 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1328 reg |= (BIT((27 + i)));
1329
1330 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1331 if (ret) {
1332 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1333 WILC_INTR_ENABLE);
1334 return ret;
1335 }
1336 if (nint) {
1337 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1338 if (ret) {
1339 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1340 WILC_INTR2_ENABLE);
1341 return ret;
1342 }
1343
1344 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1345 reg |= BIT(i);
1346
1347 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg);
1348 if (ret) {
1349 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1350 WILC_INTR2_ENABLE);
1351 return ret;
1352 }
1353 }
1354
1355 return 0;
1356 }
1357
1358 /* Global spi HIF function table */
1359 static const struct wilc_hif_func wilc_hif_spi = {
1360 .hif_init = wilc_spi_init,
1361 .hif_deinit = wilc_spi_deinit,
1362 .hif_read_reg = wilc_spi_read_reg,
1363 .hif_write_reg = wilc_spi_write_reg,
1364 .hif_block_rx = wilc_spi_read,
1365 .hif_block_tx = wilc_spi_write,
1366 .hif_read_int = wilc_spi_read_int,
1367 .hif_clear_int_ext = wilc_spi_clear_int_ext,
1368 .hif_read_size = wilc_spi_read_size,
1369 .hif_block_tx_ext = wilc_spi_write,
1370 .hif_block_rx_ext = wilc_spi_read,
1371 .hif_sync_ext = wilc_spi_sync_ext,
1372 .hif_reset = wilc_spi_reset,
1373 .hif_is_init = wilc_spi_is_init,
1374 };
1375