1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2024 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_AX210_UCODE_API_MAX 89 14 15 /* Lowest firmware API version supported */ 16 #define IWL_AX210_UCODE_API_MIN 77 17 18 /* NVM versions */ 19 #define IWL_AX210_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_AX210_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_AX210_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_AX210_DCCM2_OFFSET 0x880000 25 #define IWL_AX210_DCCM2_LEN 0x8000 26 #define IWL_AX210_SMEM_OFFSET 0x400000 27 #define IWL_AX210_SMEM_LEN 0xD0000 28 29 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0" 30 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0" 31 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0" 32 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0" 33 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0" 34 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0" 35 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0" 36 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0" 37 #define IWL_MA_B_HR_B_FW_PRE "iwlwifi-ma-b0-hr-b0" 38 #define IWL_MA_B_GF_A_FW_PRE "iwlwifi-ma-b0-gf-a0" 39 #define IWL_MA_B_GF4_A_FW_PRE "iwlwifi-ma-b0-gf4-a0" 40 41 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 42 IWL_SO_A_JF_B_FW_PRE "-" __stringify(api) ".ucode" 43 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 44 IWL_SO_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 45 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 46 IWL_MA_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 47 #define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api) \ 48 IWL_MA_B_HR_B_FW_PRE "-" __stringify(api) ".ucode" 49 50 static const struct iwl_base_params iwl_ax210_base_params = { 51 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 52 .num_of_queues = 512, 53 .max_tfd_queue_size = 65536, 54 .shadow_ram_support = true, 55 .led_compensation = 57, 56 .wd_timeout = IWL_LONG_WD_TIMEOUT, 57 .max_event_log_size = 512, 58 .shadow_reg_enable = true, 59 .pcie_l1_allowed = true, 60 }; 61 62 #define IWL_DEVICE_AX210_COMMON \ 63 .ucode_api_min = IWL_AX210_UCODE_API_MIN, \ 64 .led_mode = IWL_LED_RF_STATE, \ 65 .nvm_hw_section_num = 10, \ 66 .non_shared_ant = ANT_B, \ 67 .dccm_offset = IWL_AX210_DCCM_OFFSET, \ 68 .dccm_len = IWL_AX210_DCCM_LEN, \ 69 .dccm2_offset = IWL_AX210_DCCM2_OFFSET, \ 70 .dccm2_len = IWL_AX210_DCCM2_LEN, \ 71 .smem_offset = IWL_AX210_SMEM_OFFSET, \ 72 .smem_len = IWL_AX210_SMEM_LEN, \ 73 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 74 .apmg_not_supported = true, \ 75 .trans.mq_rx_supported = true, \ 76 .vht_mu_mimo_supported = true, \ 77 .mac_addr_from_csr = 0x380, \ 78 .ht_params = &iwl_22000_ht_params, \ 79 .nvm_ver = IWL_AX210_NVM_VERSION, \ 80 .trans.rf_id = true, \ 81 .trans.gen2 = true, \ 82 .nvm_type = IWL_NVM_EXT, \ 83 .dbgc_supported = true, \ 84 .min_umac_error_event_table = 0x400000, \ 85 .d3_debug_data_base_addr = 0x401000, \ 86 .d3_debug_data_length = 60 * 1024, \ 87 .mon_smem_regs = { \ 88 .write_ptr = { \ 89 .addr = LDBG_M2S_BUF_WPTR, \ 90 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 91 }, \ 92 .cycle_cnt = { \ 93 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 94 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 95 }, \ 96 } 97 98 #define IWL_DEVICE_AX210 \ 99 IWL_DEVICE_AX210_COMMON, \ 100 .ucode_api_max = IWL_AX210_UCODE_API_MAX, \ 101 .trans.umac_prph_offset = 0x300000, \ 102 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 103 .trans.base_params = &iwl_ax210_base_params, \ 104 .min_txq_size = 128, \ 105 .gp2_reg_addr = 0xd02c68, \ 106 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 107 .mon_dram_regs = { \ 108 .write_ptr = { \ 109 .addr = DBGC_CUR_DBGBUF_STATUS, \ 110 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 111 }, \ 112 .cycle_cnt = { \ 113 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 114 .mask = 0xffffffff, \ 115 }, \ 116 .cur_frag = { \ 117 .addr = DBGC_CUR_DBGBUF_STATUS, \ 118 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 119 }, \ 120 } 121 122 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 123 .mq_rx_supported = true, 124 .rf_id = true, 125 .gen2 = true, 126 .device_family = IWL_DEVICE_FAMILY_AX210, 127 .base_params = &iwl_ax210_base_params, 128 .umac_prph_offset = 0x300000, 129 .integrated = true, 130 /* TODO: the following values need to be checked */ 131 .xtal_latency = 500, 132 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 133 }; 134 135 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 136 .mq_rx_supported = true, 137 .rf_id = true, 138 .gen2 = true, 139 .device_family = IWL_DEVICE_FAMILY_AX210, 140 .base_params = &iwl_ax210_base_params, 141 .umac_prph_offset = 0x300000, 142 .integrated = true, 143 .low_latency_xtal = true, 144 .xtal_latency = 12000, 145 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 146 }; 147 148 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = { 149 .mq_rx_supported = true, 150 .rf_id = true, 151 .gen2 = true, 152 .device_family = IWL_DEVICE_FAMILY_AX210, 153 .base_params = &iwl_ax210_base_params, 154 .umac_prph_offset = 0x300000, 155 .integrated = true, 156 .low_latency_xtal = true, 157 .xtal_latency = 12000, 158 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 159 .imr_enabled = true, 160 }; 161 162 /* 163 * If the device doesn't support HE, no need to have that many buffers. 164 * AX210 devices can split multiple frames into a single RB, so fewer are 165 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 166 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 167 * additional overhead to account for processing time. 168 */ 169 #define IWL_NUM_RBDS_NON_HE 512 170 #define IWL_NUM_RBDS_AX210_HE 4096 171 172 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 173 .device_family = IWL_DEVICE_FAMILY_AX210, 174 .base_params = &iwl_ax210_base_params, 175 .mq_rx_supported = true, 176 .rf_id = true, 177 .gen2 = true, 178 .integrated = true, 179 .umac_prph_offset = 0x300000 180 }; 181 182 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 183 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 184 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 185 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 186 187 const char iwl_ax210_killer_1675w_name[] = 188 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 189 const char iwl_ax210_killer_1675x_name[] = 190 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 191 const char iwl_ax211_killer_1675s_name[] = 192 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 193 const char iwl_ax211_killer_1675i_name[] = 194 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 195 const char iwl_ax411_killer_1690s_name[] = 196 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 197 const char iwl_ax411_killer_1690i_name[] = 198 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 199 200 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 201 .name = "Intel(R) Wireless-AC 9560 160MHz", 202 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 203 IWL_DEVICE_AX210, 204 .num_rbds = IWL_NUM_RBDS_NON_HE, 205 }; 206 207 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 208 .name = iwl_ax211_name, 209 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 210 .uhb_supported = true, 211 IWL_DEVICE_AX210, 212 .num_rbds = IWL_NUM_RBDS_AX210_HE, 213 }; 214 215 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 216 .name = iwl_ax211_name, 217 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 218 .uhb_supported = true, 219 IWL_DEVICE_AX210, 220 .num_rbds = IWL_NUM_RBDS_AX210_HE, 221 .trans.xtal_latency = 12000, 222 .trans.low_latency_xtal = true, 223 }; 224 225 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 226 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 227 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 228 .uhb_supported = true, 229 IWL_DEVICE_AX210, 230 .num_rbds = IWL_NUM_RBDS_AX210_HE, 231 }; 232 233 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 234 .name = iwl_ax411_name, 235 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 236 .uhb_supported = true, 237 IWL_DEVICE_AX210, 238 .num_rbds = IWL_NUM_RBDS_AX210_HE, 239 }; 240 241 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 242 .name = iwl_ax411_name, 243 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 244 .uhb_supported = true, 245 IWL_DEVICE_AX210, 246 .num_rbds = IWL_NUM_RBDS_AX210_HE, 247 .trans.xtal_latency = 12000, 248 .trans.low_latency_xtal = true, 249 }; 250 251 const struct iwl_cfg iwl_cfg_ma = { 252 .fw_name_mac = "ma", 253 .uhb_supported = true, 254 IWL_DEVICE_AX210, 255 .num_rbds = IWL_NUM_RBDS_AX210_HE, 256 }; 257 258 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 259 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 260 IWL_DEVICE_AX210, 261 .num_rbds = IWL_NUM_RBDS_AX210_HE, 262 }; 263 264 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 265 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 266 IWL_FW_AND_PNVM(IWL_SO_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 267 IWL_FW_AND_PNVM(IWL_TY_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 268 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 269 IWL_FW_AND_PNVM(IWL_MA_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 270 IWL_FW_AND_PNVM(IWL_MA_A_GF4_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 271 MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 272 IWL_FW_AND_PNVM(IWL_MA_B_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 273 IWL_FW_AND_PNVM(IWL_MA_B_GF4_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 274