1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef DEBUG_H
18 #define DEBUG_H
19
20 #include "hw.h"
21 #include "dfs_debug.h"
22
23 struct ath_txq;
24 struct ath_buf;
25 struct fft_sample_tlv;
26
27 #ifdef CONFIG_ATH9K_DEBUGFS
28 #define TX_STAT_INC(sc, q, c) do { (sc)->debug.stats.txstats[q].c++; } while (0)
29 #define RX_STAT_INC(sc, c) do { (sc)->debug.stats.rxstats.c++; } while (0)
30 #define RESET_STAT_INC(sc, type) do { (sc)->debug.stats.reset[type]++; } while (0)
31 #define ANT_STAT_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].c++; } while (0)
32 #define ANT_LNA_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].lna_recv_cnt[c]++; } while (0)
33 #else
34 #define TX_STAT_INC(sc, q, c) do { (void)(sc); } while (0)
35 #define RX_STAT_INC(sc, c) do { (void)(sc); } while (0)
36 #define RESET_STAT_INC(sc, type) do { (void)(sc); } while (0)
37 #define ANT_STAT_INC(sc, i, c) do { (void)(sc); } while (0)
38 #define ANT_LNA_INC(sc, i, c) do { (void)(sc); } while (0)
39 #endif
40
41 enum ath_reset_type {
42 RESET_TYPE_USER,
43 RESET_TYPE_BB_HANG,
44 RESET_TYPE_BB_WATCHDOG,
45 RESET_TYPE_FATAL_INT,
46 RESET_TYPE_TX_ERROR,
47 RESET_TYPE_TX_GTT,
48 RESET_TYPE_TX_HANG,
49 RESET_TYPE_PLL_HANG,
50 RESET_TYPE_MAC_HANG,
51 RESET_TYPE_BEACON_STUCK,
52 RESET_TYPE_MCI,
53 RESET_TYPE_CALIBRATION,
54 RESET_TX_DMA_ERROR,
55 RESET_RX_DMA_ERROR,
56 RESET_TYPE_RX_INACTIVE,
57 __RESET_TYPE_MAX
58 };
59
60 #ifdef CONFIG_ATH9K_DEBUGFS
61
62 /**
63 * struct ath_interrupt_stats - Contains statistics about interrupts
64 * @total: Total no. of interrupts generated so far
65 * @rxok: RX with no errors
66 * @rxlp: RX with low priority RX
67 * @rxhp: RX with high priority, uapsd only
68 * @rxeol: RX with no more RXDESC available
69 * @rxorn: RX FIFO overrun
70 * @txok: TX completed at the requested rate
71 * @txurn: TX FIFO underrun
72 * @mib: MIB regs reaching its threshold
73 * @rxphyerr: RX with phy errors
74 * @rx_keycache_miss: RX with key cache misses
75 * @swba: Software Beacon Alert
76 * @bmiss: Beacon Miss
77 * @bnr: Beacon Not Ready
78 * @cst: Carrier Sense TImeout
79 * @gtt: Global TX Timeout
80 * @tim: RX beacon TIM occurrence
81 * @cabend: RX End of CAB traffic
82 * @dtimsync: DTIM sync lossage
83 * @dtim: RX Beacon with DTIM
84 * @bb_watchdog: Baseband watchdog
85 * @tsfoor: TSF out of range, indicates that the corrected TSF received
86 * from a beacon differs from the PCU's internal TSF by more than a
87 * (programmable) threshold
88 * @local_timeout: Internal bus timeout.
89 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
90 * @gen_timer: Generic hardware timer interrupt
91 */
92 struct ath_interrupt_stats {
93 u32 total;
94 u32 rxok;
95 u32 rxlp;
96 u32 rxhp;
97 u32 rxeol;
98 u32 rxorn;
99 u32 txok;
100 u32 txeol;
101 u32 txurn;
102 u32 mib;
103 u32 rxphyerr;
104 u32 rx_keycache_miss;
105 u32 swba;
106 u32 bmiss;
107 u32 bnr;
108 u32 cst;
109 u32 gtt;
110 u32 tim;
111 u32 cabend;
112 u32 dtimsync;
113 u32 dtim;
114 u32 bb_watchdog;
115 u32 tsfoor;
116 u32 mci;
117 u32 gen_timer;
118
119 /* Sync-cause stats */
120 u32 sync_cause_all;
121 u32 sync_rtc_irq;
122 u32 sync_mac_irq;
123 u32 eeprom_illegal_access;
124 u32 apb_timeout;
125 u32 pci_mode_conflict;
126 u32 host1_fatal;
127 u32 host1_perr;
128 u32 trcv_fifo_perr;
129 u32 radm_cpl_ep;
130 u32 radm_cpl_dllp_abort;
131 u32 radm_cpl_tlp_abort;
132 u32 radm_cpl_ecrc_err;
133 u32 radm_cpl_timeout;
134 u32 local_timeout;
135 u32 pm_access;
136 u32 mac_awake;
137 u32 mac_asleep;
138 u32 mac_sleep_access;
139 };
140
141
142 /**
143 * struct ath_tx_stats - Statistics about TX
144 * @tx_pkts_all: No. of total frames transmitted, including ones that
145 may have had errors.
146 * @tx_bytes_all: No. of total bytes transmitted, including ones that
147 may have had errors.
148 * @queued: Total MPDUs (non-aggr) queued
149 * @completed: Total MPDUs (non-aggr) completed
150 * @a_aggr: Total no. of aggregates queued
151 * @a_queued_hw: Total AMPDUs queued to hardware
152 * @a_completed: Total AMPDUs completed
153 * @a_retries: No. of AMPDUs retried (SW)
154 * @a_xretries: No. of AMPDUs dropped due to xretries
155 * @txerr_filtered: No. of frames with TXERR_FILT flag set.
156 * @fifo_underrun: FIFO underrun occurrences
157 Valid only for:
158 - non-aggregate condition.
159 - first packet of aggregate.
160 * @xtxop: No. of frames filtered because of TXOP limit
161 * @timer_exp: Transmit timer expiry
162 * @desc_cfg_err: Descriptor configuration errors
163 * @data_urn: TX data underrun errors
164 * @delim_urn: TX delimiter underrun errors
165 * @puttxbuf: Number of times hardware was given txbuf to write.
166 * @txstart: Number of times hardware was told to start tx.
167 * @txprocdesc: Number of times tx descriptor was processed
168 * @txfailed: Out-of-memory or other errors in xmit path.
169 */
170 struct ath_tx_stats {
171 u32 tx_pkts_all;
172 u32 tx_bytes_all;
173 u32 queued;
174 u32 completed;
175 u32 xretries;
176 u32 a_aggr;
177 u32 a_queued_hw;
178 u32 a_completed;
179 u32 a_retries;
180 u32 a_xretries;
181 u32 txerr_filtered;
182 u32 fifo_underrun;
183 u32 xtxop;
184 u32 timer_exp;
185 u32 desc_cfg_err;
186 u32 data_underrun;
187 u32 delim_underrun;
188 u32 puttxbuf;
189 u32 txstart;
190 u32 txprocdesc;
191 u32 txfailed;
192 };
193
194 /*
195 * Various utility macros to print TX/Queue counters.
196 */
197 #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
198 #define TXSTATS sc->debug.stats.txstats
199 #define PR(str, elem) \
200 do { \
201 seq_printf(file, "%s%13u%11u%10u%10u\n", str, \
202 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
203 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
204 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
205 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
206 } while(0)
207
208 struct ath_rx_rate_stats {
209 struct {
210 u32 ht20_cnt;
211 u32 ht40_cnt;
212 u32 sgi_cnt;
213 u32 lgi_cnt;
214 } ht_stats[24];
215
216 struct {
217 u32 ofdm_cnt;
218 } ofdm_stats[8];
219
220 struct {
221 u32 cck_lp_cnt;
222 u32 cck_sp_cnt;
223 } cck_stats[4];
224 };
225
226 struct ath_airtime_stats {
227 u32 rx_airtime;
228 u32 tx_airtime;
229 };
230
231 #define ANT_MAIN 0
232 #define ANT_ALT 1
233
234 struct ath_antenna_stats {
235 u32 recv_cnt;
236 u32 rssi_avg;
237 u32 lna_recv_cnt[4];
238 u32 lna_attempt_cnt[4];
239 };
240
241 struct ath_stats {
242 struct ath_interrupt_stats istats;
243 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
244 struct ath_rx_stats rxstats;
245 struct ath_dfs_stats dfs_stats;
246 struct ath_antenna_stats ant_stats[2];
247 u32 reset[__RESET_TYPE_MAX];
248 };
249
250 struct ath9k_debug {
251 struct dentry *debugfs_phy;
252 u32 regidx;
253 struct ath_stats stats;
254 };
255
256 int ath9k_init_debug(struct ath_hw *ah);
257 void ath9k_deinit_debug(struct ath_softc *sc);
258
259 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
260 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
261 struct ath_tx_status *ts, struct ath_txq *txq,
262 unsigned int flags);
263 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
264 int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
265 struct ieee80211_vif *vif, int sset);
266 void ath9k_get_et_stats(struct ieee80211_hw *hw,
267 struct ieee80211_vif *vif,
268 struct ethtool_stats *stats, u64 *data);
269 void ath9k_get_et_strings(struct ieee80211_hw *hw,
270 struct ieee80211_vif *vif,
271 u32 sset, u8 *data);
272 void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
273 struct ieee80211_vif *vif,
274 struct ieee80211_sta *sta,
275 struct dentry *dir);
276 void ath9k_debug_stat_ant(struct ath_softc *sc,
277 struct ath_hw_antcomb_conf *div_ant_conf,
278 int main_rssi_avg, int alt_rssi_avg);
279 void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
280
281 #else
282
ath9k_init_debug(struct ath_hw * ah)283 static inline int ath9k_init_debug(struct ath_hw *ah)
284 {
285 return 0;
286 }
287
ath9k_deinit_debug(struct ath_softc * sc)288 static inline void ath9k_deinit_debug(struct ath_softc *sc)
289 {
290 }
ath_debug_stat_interrupt(struct ath_softc * sc,enum ath9k_int status)291 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
292 enum ath9k_int status)
293 {
294 }
ath_debug_stat_tx(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,struct ath_txq * txq,unsigned int flags)295 static inline void ath_debug_stat_tx(struct ath_softc *sc,
296 struct ath_buf *bf,
297 struct ath_tx_status *ts,
298 struct ath_txq *txq,
299 unsigned int flags)
300 {
301 }
ath_debug_stat_rx(struct ath_softc * sc,struct ath_rx_status * rs)302 static inline void ath_debug_stat_rx(struct ath_softc *sc,
303 struct ath_rx_status *rs)
304 {
305 }
ath9k_debug_stat_ant(struct ath_softc * sc,struct ath_hw_antcomb_conf * div_ant_conf,int main_rssi_avg,int alt_rssi_avg)306 static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
307 struct ath_hw_antcomb_conf *div_ant_conf,
308 int main_rssi_avg, int alt_rssi_avg)
309 {
310
311 }
312
313 static inline void
ath9k_debug_sync_cause(struct ath_softc * sc,u32 sync_cause)314 ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
315 {
316 }
317
318 #endif /* CONFIG_ATH9K_DEBUGFS */
319
320 #ifdef CONFIG_ATH9K_STATION_STATISTICS
321 void ath_debug_rate_stats(struct ath_softc *sc,
322 struct ath_rx_status *rs,
323 struct sk_buff *skb);
324 #else
ath_debug_rate_stats(struct ath_softc * sc,struct ath_rx_status * rs,struct sk_buff * skb)325 static inline void ath_debug_rate_stats(struct ath_softc *sc,
326 struct ath_rx_status *rs,
327 struct sk_buff *skb)
328 {
329 }
330 #endif /* CONFIG_ATH9K_STATION_STATISTICS */
331
332 #endif /* DEBUG_H */
333