1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HAL_RX_H
8 #define ATH12K_HAL_RX_H
9
10 struct hal_rx_wbm_rel_info {
11 u32 cookie;
12 enum hal_wbm_rel_src_module err_rel_src;
13 enum hal_reo_dest_ring_push_reason push_reason;
14 u32 err_code;
15 bool first_msdu;
16 bool last_msdu;
17 bool continuation;
18 void *rx_desc;
19 bool hw_cc_done;
20 };
21
22 #define HAL_INVALID_PEERID 0x3fff
23 #define VHT_SIG_SU_NSS_MASK 0x7
24
25 #define HAL_RX_MAX_MCS 12
26 #define HAL_RX_MAX_NSS 8
27
28 #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \
29 le32_get_bits((__val), GENMASK(7, 0))
30
31 #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \
32 le32_get_bits((__val), GENMASK(15, 8))
33
34 #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \
35 le32_get_bits((__val), GENMASK(23, 16))
36
37 #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \
38 le32_get_bits((__val), GENMASK(31, 24))
39
40 struct hal_rx_mon_status_tlv_hdr {
41 u32 hdr;
42 u8 value[];
43 };
44
45 enum hal_rx_su_mu_coding {
46 HAL_RX_SU_MU_CODING_BCC,
47 HAL_RX_SU_MU_CODING_LDPC,
48 HAL_RX_SU_MU_CODING_MAX,
49 };
50
51 enum hal_rx_gi {
52 HAL_RX_GI_0_8_US,
53 HAL_RX_GI_0_4_US,
54 HAL_RX_GI_1_6_US,
55 HAL_RX_GI_3_2_US,
56 HAL_RX_GI_MAX,
57 };
58
59 enum hal_rx_bw {
60 HAL_RX_BW_20MHZ,
61 HAL_RX_BW_40MHZ,
62 HAL_RX_BW_80MHZ,
63 HAL_RX_BW_160MHZ,
64 HAL_RX_BW_320MHZ,
65 HAL_RX_BW_MAX,
66 };
67
68 enum hal_rx_preamble {
69 HAL_RX_PREAMBLE_11A,
70 HAL_RX_PREAMBLE_11B,
71 HAL_RX_PREAMBLE_11N,
72 HAL_RX_PREAMBLE_11AC,
73 HAL_RX_PREAMBLE_11AX,
74 HAL_RX_PREAMBLE_MAX,
75 };
76
77 enum hal_rx_reception_type {
78 HAL_RX_RECEPTION_TYPE_SU,
79 HAL_RX_RECEPTION_TYPE_MU_MIMO,
80 HAL_RX_RECEPTION_TYPE_MU_OFDMA,
81 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
82 HAL_RX_RECEPTION_TYPE_MAX,
83 };
84
85 enum hal_rx_legacy_rate {
86 HAL_RX_LEGACY_RATE_1_MBPS,
87 HAL_RX_LEGACY_RATE_2_MBPS,
88 HAL_RX_LEGACY_RATE_5_5_MBPS,
89 HAL_RX_LEGACY_RATE_6_MBPS,
90 HAL_RX_LEGACY_RATE_9_MBPS,
91 HAL_RX_LEGACY_RATE_11_MBPS,
92 HAL_RX_LEGACY_RATE_12_MBPS,
93 HAL_RX_LEGACY_RATE_18_MBPS,
94 HAL_RX_LEGACY_RATE_24_MBPS,
95 HAL_RX_LEGACY_RATE_36_MBPS,
96 HAL_RX_LEGACY_RATE_48_MBPS,
97 HAL_RX_LEGACY_RATE_54_MBPS,
98 HAL_RX_LEGACY_RATE_INVALID,
99 };
100
101 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
102 #define HAL_TLV_STATUS_PPDU_DONE 1
103 #define HAL_TLV_STATUS_BUF_DONE 2
104 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
105 #define HAL_RX_FCS_LEN 4
106
107 enum hal_rx_mon_status {
108 HAL_RX_MON_STATUS_PPDU_NOT_DONE,
109 HAL_RX_MON_STATUS_PPDU_DONE,
110 HAL_RX_MON_STATUS_BUF_DONE,
111 HAL_RX_MON_STATUS_BUF_ADDR,
112 HAL_RX_MON_STATUS_MPDU_END,
113 HAL_RX_MON_STATUS_MSDU_END,
114 };
115
116 #define HAL_RX_MAX_MPDU 256
117 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5)
118
119 struct hal_rx_user_status {
120 u32 mcs:4,
121 nss:3,
122 ofdma_info_valid:1,
123 ul_ofdma_ru_start_index:7,
124 ul_ofdma_ru_width:7,
125 ul_ofdma_ru_size:8;
126 u32 ul_ofdma_user_v0_word0;
127 u32 ul_ofdma_user_v0_word1;
128 u32 ast_index;
129 u32 tid;
130 u16 tcp_msdu_count;
131 u16 tcp_ack_msdu_count;
132 u16 udp_msdu_count;
133 u16 other_msdu_count;
134 u16 frame_control;
135 u8 frame_control_info_valid;
136 u8 data_sequence_control_info_valid;
137 u16 first_data_seq_ctrl;
138 u32 preamble_type;
139 u16 ht_flags;
140 u16 vht_flags;
141 u16 he_flags;
142 u8 rs_flags;
143 u8 ldpc;
144 u32 mpdu_cnt_fcs_ok;
145 u32 mpdu_cnt_fcs_err;
146 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
147 u32 mpdu_ok_byte_count;
148 u32 mpdu_err_byte_count;
149 };
150
151 #define HAL_MAX_UL_MU_USERS 37
152
153 struct hal_rx_mon_ppdu_info {
154 u32 ppdu_id;
155 u32 last_ppdu_id;
156 u64 ppdu_ts;
157 u32 num_mpdu_fcs_ok;
158 u32 num_mpdu_fcs_err;
159 u32 preamble_type;
160 u32 mpdu_len;
161 u16 chan_num;
162 u16 freq;
163 u16 tcp_msdu_count;
164 u16 tcp_ack_msdu_count;
165 u16 udp_msdu_count;
166 u16 other_msdu_count;
167 u16 peer_id;
168 u8 rate;
169 u8 mcs;
170 u8 nss;
171 u8 bw;
172 u8 vht_flag_values1;
173 u8 vht_flag_values2;
174 u8 vht_flag_values3[4];
175 u8 vht_flag_values4;
176 u8 vht_flag_values5;
177 u16 vht_flag_values6;
178 u8 is_stbc;
179 u8 gi;
180 u8 sgi;
181 u8 ldpc;
182 u8 beamformed;
183 u8 rssi_comb;
184 u16 tid;
185 u8 fc_valid;
186 u16 ht_flags;
187 u16 vht_flags;
188 u16 he_flags;
189 u16 he_mu_flags;
190 u8 dcm;
191 u8 ru_alloc;
192 u8 reception_type;
193 u64 tsft;
194 u64 rx_duration;
195 u16 frame_control;
196 u32 ast_index;
197 u8 rs_fcs_err;
198 u8 rs_flags;
199 u8 cck_flag;
200 u8 ofdm_flag;
201 u8 ulofdma_flag;
202 u8 frame_control_info_valid;
203 u16 he_per_user_1;
204 u16 he_per_user_2;
205 u8 he_per_user_position;
206 u8 he_per_user_known;
207 u16 he_flags1;
208 u16 he_flags2;
209 u8 he_RU[4];
210 u16 he_data1;
211 u16 he_data2;
212 u16 he_data3;
213 u16 he_data4;
214 u16 he_data5;
215 u16 he_data6;
216 u32 ppdu_len;
217 u32 prev_ppdu_id;
218 u32 device_id;
219 u16 first_data_seq_ctrl;
220 u8 monitor_direct_used;
221 u8 data_sequence_control_info_valid;
222 u8 ltf_size;
223 u8 rxpcu_filter_pass;
224 s8 rssi_chain[8][8];
225 u32 num_users;
226 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
227 u8 addr1[ETH_ALEN];
228 u8 addr2[ETH_ALEN];
229 u8 addr3[ETH_ALEN];
230 u8 addr4[ETH_ALEN];
231 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS];
232 u8 userid;
233 u16 ampdu_id[HAL_MAX_UL_MU_USERS];
234 bool first_msdu_in_mpdu;
235 bool is_ampdu;
236 u8 medium_prot_type;
237 };
238
239 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
240 #define HAL_RX_PPDU_START_INFO1_CHAN_NUM GENMASK(15, 0)
241 #define HAL_RX_PPDU_START_INFO1_CHAN_FREQ GENMASK(31, 16)
242
243 struct hal_rx_ppdu_start {
244 __le32 info0;
245 __le32 info1;
246 __le32 ppdu_start_ts_31_0;
247 __le32 ppdu_start_ts_63_32;
248 __le32 rsvd[2];
249 } __packed;
250
251 #define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID GENMASK(13, 0)
252 #define HAL_RX_PPDU_END_USER_STATS_INFO0_DEVICE_ID GENMASK(15, 14)
253 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(26, 16)
254
255 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(10, 0)
256 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(11)
257 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(12)
258 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(13)
259 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(24, 21)
260
261 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
262 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
263
264 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
265
266 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
267 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
268
269 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
270 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
271
272 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)
273 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)
274
275 #define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT GENMASK(24, 0)
276 #define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)
277
278 struct hal_rx_ppdu_end_user_stats {
279 __le32 rsvd0[2];
280 __le32 info0;
281 __le32 info1;
282 __le32 info2;
283 __le32 info3;
284 __le32 ht_ctrl;
285 __le32 rsvd1[2];
286 __le32 info4;
287 __le32 info5;
288 __le32 usr_resp_ref;
289 __le32 info6;
290 __le32 rsvd3[4];
291 __le32 info7;
292 __le32 rsvd4;
293 __le32 info8;
294 __le32 rsvd5[2];
295 __le32 usr_resp_ref_ext;
296 __le32 rsvd6;
297 } __packed;
298
299 struct hal_rx_ppdu_end_user_stats_ext {
300 __le32 info0;
301 __le32 info1;
302 __le32 info2;
303 __le32 info3;
304 __le32 info4;
305 __le32 info5;
306 __le32 info6;
307 __le32 rsvd;
308 } __packed;
309
310 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
311 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
312
313 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
314 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
315 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
316
317 struct hal_rx_ht_sig_info {
318 __le32 info0;
319 __le32 info1;
320 } __packed;
321
322 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
323 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
324
325 struct hal_rx_lsig_b_info {
326 __le32 info0;
327 } __packed;
328
329 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
330 #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
331 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
332
333 struct hal_rx_lsig_a_info {
334 __le32 info0;
335 } __packed;
336
337 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
338 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
339 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
340 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
341
342 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
343 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
344 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
345 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
346
347 struct hal_rx_vht_sig_a_info {
348 __le32 info0;
349 __le32 info1;
350 } __packed;
351
352 enum hal_rx_vht_sig_a_gi_setting {
353 HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
354 HAL_RX_VHT_SIG_A_SHORT_GI = 1,
355 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
356 };
357
358 #define HE_GI_0_8 0
359 #define HE_GI_0_4 1
360 #define HE_GI_1_6 2
361 #define HE_GI_3_2 3
362
363 #define HE_LTF_1_X 0
364 #define HE_LTF_2_X 1
365 #define HE_LTF_4_X 2
366
367 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
368 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
369 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
370 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
371 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
372 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
373 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
374 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
375 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
376 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
377
378 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
379 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
380 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
381 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
382 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
383 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
384 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
385 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
386
387 struct hal_rx_he_sig_a_su_info {
388 __le32 info0;
389 __le32 info1;
390 } __packed;
391
392 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1)
393 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1)
394 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4)
395 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5)
396 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11)
397 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15)
398 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
399 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22)
400 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23)
401 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25)
402
403 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0)
404 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
405 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11)
406 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12)
407 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
408 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15)
409
410 struct hal_rx_he_sig_a_mu_dl_info {
411 __le32 info0;
412 __le32 info1;
413 } __packed;
414
415 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
416
417 struct hal_rx_he_sig_b1_mu_info {
418 __le32 info0;
419 } __packed;
420
421 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
422 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
423 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
424 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
425
426 struct hal_rx_he_sig_b2_mu_info {
427 __le32 info0;
428 } __packed;
429
430 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
431 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
432 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(14)
433 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
434 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
435 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
436
437 struct hal_rx_he_sig_b2_ofdma_info {
438 __le32 info0;
439 } __packed;
440
441 enum hal_rx_ul_reception_type {
442 HAL_RECEPTION_TYPE_ULOFMDA,
443 HAL_RECEPTION_TYPE_ULMIMO,
444 HAL_RECEPTION_TYPE_OTHER,
445 HAL_RECEPTION_TYPE_FRAMELESS
446 };
447
448 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0)
449 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5)
450 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8)
451
452 struct hal_rx_phyrx_rssi_legacy_info {
453 __le32 info0;
454 __le32 rsvd0[39];
455 __le32 info1;
456 __le32 rsvd1;
457 } __packed;
458
459 #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16)
460 #define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(29, 16)
461 #define HAL_RX_MPDU_START_INFO1_DEVICE_ID GENMASK(31, 30)
462 #define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0)
463 struct hal_rx_mpdu_start {
464 __le32 rsvd0[9];
465 __le32 info0;
466 __le32 info1;
467 __le32 rsvd1[2];
468 __le32 info2;
469 __le32 rsvd2[16];
470 } __packed;
471
472 #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
473 struct hal_rx_ppdu_end_duration {
474 __le32 rsvd0[9];
475 __le32 info0;
476 __le32 rsvd1[18];
477 } __packed;
478
479 struct hal_rx_rxpcu_classification_overview {
480 u32 rsvd0;
481 } __packed;
482
483 struct hal_rx_msdu_desc_info {
484 u32 msdu_flags;
485 u16 msdu_len; /* 14 bits for length */
486 };
487
488 #define HAL_RX_NUM_MSDU_DESC 6
489 struct hal_rx_msdu_list {
490 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
491 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
492 u8 rbm[HAL_RX_NUM_MSDU_DESC];
493 };
494
495 #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0)
496 #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0)
497 #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16)
498 #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0)
499
500 struct hal_rx_frame_bitmap_ack {
501 __le32 reserved;
502 __le32 info0;
503 __le32 info1;
504 __le32 info2;
505 __le32 reserved1[10];
506 } __packed;
507
508 #define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0)
509 #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16)
510 #define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0)
511 #define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21)
512 #define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25)
513 #define HAL_RX_RESP_REQ_INFO1_STBC BIT(27)
514 #define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28)
515 #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29)
516 #define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0)
517 #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0)
518 #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0)
519 #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16)
520 #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0)
521
522 struct hal_rx_resp_req_info {
523 __le32 info0;
524 __le32 reserved[1];
525 __le32 info1;
526 __le32 info2;
527 __le32 reserved1[2];
528 __le32 info3;
529 __le32 info4;
530 __le32 info5;
531 __le32 reserved2[5];
532 } __packed;
533
534 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
535 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
536 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
537 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
538
539 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30)
540 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31)
541 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0)
542 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3)
543 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7)
544 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8)
545 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9)
546 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16)
547
548 /* HE Radiotap data1 Mask */
549 #define HE_SU_FORMAT_TYPE 0x0000
550 #define HE_EXT_SU_FORMAT_TYPE 0x0001
551 #define HE_MU_FORMAT_TYPE 0x0002
552 #define HE_TRIG_FORMAT_TYPE 0x0003
553 #define HE_BEAM_CHANGE_KNOWN 0x0008
554 #define HE_DL_UL_KNOWN 0x0010
555 #define HE_MCS_KNOWN 0x0020
556 #define HE_DCM_KNOWN 0x0040
557 #define HE_CODING_KNOWN 0x0080
558 #define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100
559 #define HE_STBC_KNOWN 0x0200
560 #define HE_DATA_BW_RU_KNOWN 0x4000
561 #define HE_DOPPLER_KNOWN 0x8000
562 #define HE_BSS_COLOR_KNOWN 0x0004
563
564 /* HE Radiotap data2 Mask */
565 #define HE_GI_KNOWN 0x0002
566 #define HE_TXBF_KNOWN 0x0010
567 #define HE_PE_DISAMBIGUITY_KNOWN 0x0020
568 #define HE_TXOP_KNOWN 0x0040
569 #define HE_LTF_SYMBOLS_KNOWN 0x0004
570 #define HE_PRE_FEC_PADDING_KNOWN 0x0008
571 #define HE_MIDABLE_PERIODICITY_KNOWN 0x0080
572
573 /* HE radiotap data3 shift values */
574 #define HE_BEAM_CHANGE_SHIFT 6
575 #define HE_DL_UL_SHIFT 7
576 #define HE_TRANSMIT_MCS_SHIFT 8
577 #define HE_DCM_SHIFT 12
578 #define HE_CODING_SHIFT 13
579 #define HE_LDPC_EXTRA_SYMBOL_SHIFT 14
580 #define HE_STBC_SHIFT 15
581
582 /* HE radiotap data4 shift values */
583 #define HE_STA_ID_SHIFT 4
584
585 /* HE radiotap data5 */
586 #define HE_GI_SHIFT 4
587 #define HE_LTF_SIZE_SHIFT 6
588 #define HE_LTF_SYM_SHIFT 8
589 #define HE_TXBF_SHIFT 14
590 #define HE_PE_DISAMBIGUITY_SHIFT 15
591 #define HE_PRE_FEC_PAD_SHIFT 12
592
593 /* HE radiotap data6 */
594 #define HE_DOPPLER_SHIFT 4
595 #define HE_TXOP_SHIFT 8
596
597 /* HE radiotap HE-MU flags1 */
598 #define HE_SIG_B_MCS_KNOWN 0x0010
599 #define HE_SIG_B_DCM_KNOWN 0x0040
600 #define HE_SIG_B_SYM_NUM_KNOWN 0x8000
601 #define HE_RU_0_KNOWN 0x0100
602 #define HE_RU_1_KNOWN 0x0200
603 #define HE_RU_2_KNOWN 0x0400
604 #define HE_RU_3_KNOWN 0x0800
605 #define HE_DCM_FLAG_1_SHIFT 5
606 #define HE_SPATIAL_REUSE_MU_KNOWN 0x0100
607 #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000
608
609 /* HE radiotap HE-MU flags2 */
610 #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3
611 #define HE_BW_KNOWN 0x0004
612 #define HE_NUM_SIG_B_SYMBOLS_SHIFT 4
613 #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100
614 #define HE_NUM_SIG_B_FLAG_2_SHIFT 9
615 #define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12
616 #define HE_LTF_KNOWN 0x8000
617
618 /* HE radiotap per_user_1 */
619 #define HE_STA_SPATIAL_SHIFT 11
620 #define HE_TXBF_SHIFT 14
621 #define HE_RESERVED_SET_TO_1_SHIFT 19
622 #define HE_STA_CODING_SHIFT 20
623
624 /* HE radiotap per_user_2 */
625 #define HE_STA_MCS_SHIFT 4
626 #define HE_STA_DCM_SHIFT 5
627
628 /* HE radiotap per user known */
629 #define HE_USER_FIELD_POSITION_KNOWN 0x01
630 #define HE_STA_ID_PER_USER_KNOWN 0x02
631 #define HE_STA_NSTS_KNOWN 0x04
632 #define HE_STA_TX_BF_KNOWN 0x08
633 #define HE_STA_SPATIAL_CONFIG_KNOWN 0x10
634 #define HE_STA_MCS_KNOWN 0x20
635 #define HE_STA_DCM_KNOWN 0x40
636 #define HE_STA_CODING_KNOWN 0x80
637
638 #define HAL_RX_MPDU_ERR_FCS BIT(0)
639 #define HAL_RX_MPDU_ERR_DECRYPT BIT(1)
640 #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2)
641 #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3)
642 #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4)
643 #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5)
644 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6)
645 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)
646
647 static inline
ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)648 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
649 {
650 enum nl80211_he_ru_alloc ret;
651
652 switch (ru_tones) {
653 case RU_52:
654 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
655 break;
656 case RU_106:
657 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
658 break;
659 case RU_242:
660 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
661 break;
662 case RU_484:
663 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
664 break;
665 case RU_996:
666 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
667 break;
668 case RU_26:
669 fallthrough;
670 default:
671 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
672 break;
673 }
674 return ret;
675 }
676
677 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab,
678 struct hal_tlv_64_hdr *tlv,
679 struct hal_reo_status *status);
680 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab,
681 struct hal_tlv_64_hdr *tlv,
682 struct hal_reo_status *status);
683 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab,
684 struct hal_tlv_64_hdr *tlv,
685 struct hal_reo_status *status);
686 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab,
687 struct hal_tlv_64_hdr *tlv,
688 struct hal_reo_status *status);
689 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
690 struct hal_tlv_64_hdr *tlv,
691 struct hal_reo_status *status);
692 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
693 struct hal_tlv_64_hdr *tlv,
694 struct hal_reo_status *status);
695 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
696 struct hal_tlv_64_hdr *tlv,
697 struct hal_reo_status *status);
698 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
699 u32 *msdu_cookies,
700 enum hal_rx_buf_return_buf_manager *rbm);
701 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
702 struct hal_wbm_release_ring *dst_desc,
703 struct hal_wbm_release_ring *src_desc,
704 enum hal_wbm_rel_bm_act action);
705 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
706 dma_addr_t paddr, u32 cookie, u8 manager);
707 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
708 dma_addr_t *paddr,
709 u32 *cookie, u8 *rbm);
710 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
711 struct hal_reo_dest_ring *desc,
712 dma_addr_t *paddr, u32 *desc_bank);
713 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
714 struct hal_rx_wbm_rel_info *rel_info);
715 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
716 struct ath12k_buffer_addr *buff_addr,
717 dma_addr_t *paddr, u32 *cookie);
718
719 #endif
720