1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "core.h"
8 #include "dp_tx.h"
9 #include "debug.h"
10 #include "hw.h"
11
12 static enum hal_tcl_encap_type
ath12k_dp_tx_get_encap_type(struct ath12k_link_vif * arvif,struct sk_buff * skb)13 ath12k_dp_tx_get_encap_type(struct ath12k_link_vif *arvif, struct sk_buff *skb)
14 {
15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
16 struct ath12k_base *ab = arvif->ar->ab;
17
18 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags))
19 return HAL_TCL_ENCAP_TYPE_RAW;
20
21 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
22 return HAL_TCL_ENCAP_TYPE_ETHERNET;
23
24 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
25 }
26
ath12k_dp_tx_encap_nwifi(struct sk_buff * skb)27 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb)
28 {
29 struct ieee80211_hdr *hdr = (void *)skb->data;
30 u8 *qos_ctl;
31
32 if (!ieee80211_is_data_qos(hdr->frame_control))
33 return;
34
35 qos_ctl = ieee80211_get_qos_ctl(hdr);
36 memmove(skb->data + IEEE80211_QOS_CTL_LEN,
37 skb->data, (void *)qos_ctl - (void *)skb->data);
38 skb_pull(skb, IEEE80211_QOS_CTL_LEN);
39
40 hdr = (void *)skb->data;
41 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
42 }
43
ath12k_dp_tx_get_tid(struct sk_buff * skb)44 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb)
45 {
46 struct ieee80211_hdr *hdr = (void *)skb->data;
47 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb);
48
49 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP)
50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
51 else if (!ieee80211_is_data_qos(hdr->frame_control))
52 return HAL_DESC_REO_NON_QOS_TID;
53 else
54 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
55 }
56
ath12k_dp_tx_get_encrypt_type(u32 cipher)57 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher)
58 {
59 switch (cipher) {
60 case WLAN_CIPHER_SUITE_WEP40:
61 return HAL_ENCRYPT_TYPE_WEP_40;
62 case WLAN_CIPHER_SUITE_WEP104:
63 return HAL_ENCRYPT_TYPE_WEP_104;
64 case WLAN_CIPHER_SUITE_TKIP:
65 return HAL_ENCRYPT_TYPE_TKIP_MIC;
66 case WLAN_CIPHER_SUITE_CCMP:
67 return HAL_ENCRYPT_TYPE_CCMP_128;
68 case WLAN_CIPHER_SUITE_CCMP_256:
69 return HAL_ENCRYPT_TYPE_CCMP_256;
70 case WLAN_CIPHER_SUITE_GCMP:
71 return HAL_ENCRYPT_TYPE_GCMP_128;
72 case WLAN_CIPHER_SUITE_GCMP_256:
73 return HAL_ENCRYPT_TYPE_AES_GCMP_256;
74 default:
75 return HAL_ENCRYPT_TYPE_OPEN;
76 }
77 }
78
ath12k_dp_tx_release_txbuf(struct ath12k_dp * dp,struct ath12k_tx_desc_info * tx_desc,u8 pool_id)79 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp,
80 struct ath12k_tx_desc_info *tx_desc,
81 u8 pool_id)
82 {
83 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
84 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]);
85 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
86 }
87
ath12k_dp_tx_assign_buffer(struct ath12k_dp * dp,u8 pool_id)88 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp,
89 u8 pool_id)
90 {
91 struct ath12k_tx_desc_info *desc;
92
93 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
94 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id],
95 struct ath12k_tx_desc_info,
96 list);
97 if (!desc) {
98 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
99 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n");
100 return NULL;
101 }
102
103 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]);
104 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
105
106 return desc;
107 }
108
ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base * ab,struct hal_tx_msdu_ext_desc * tcl_ext_cmd,struct hal_tx_info * ti)109 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab,
110 struct hal_tx_msdu_ext_desc *tcl_ext_cmd,
111 struct hal_tx_info *ti)
112 {
113 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr,
114 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO);
115 tcl_ext_cmd->info1 = le32_encode_bits(0x0,
116 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) |
117 le32_encode_bits(ti->data_len,
118 HAL_TX_MSDU_EXT_INFO1_BUF_LEN);
119
120 tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) |
121 le32_encode_bits(ti->encap_type,
122 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) |
123 le32_encode_bits(ti->encrypt_type,
124 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE);
125 }
126
127 #define HTT_META_DATA_ALIGNMENT 0x8
128
ath12k_dp_metadata_align_skb(struct sk_buff * skb,u8 tail_len)129 static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len)
130 {
131 struct sk_buff *tail;
132 void *metadata;
133
134 if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0))
135 return NULL;
136
137 metadata = pskb_put(skb, tail, tail_len);
138 memset(metadata, 0, tail_len);
139 return metadata;
140 }
141
142 /* Preparing HTT Metadata when utilized with ext MSDU */
ath12k_dp_prepare_htt_metadata(struct sk_buff * skb)143 static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb)
144 {
145 struct hal_tx_msdu_metadata *desc_ext;
146 u8 htt_desc_size;
147 /* Size rounded of multiple of 8 bytes */
148 u8 htt_desc_size_aligned;
149
150 htt_desc_size = sizeof(struct hal_tx_msdu_metadata);
151 htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT);
152
153 desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned);
154 if (!desc_ext)
155 return -ENOMEM;
156
157 desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) |
158 le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) |
159 le32_encode_bits(1,
160 HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL);
161
162 return 0;
163 }
164
ath12k_dp_tx_move_payload(struct sk_buff * skb,unsigned long delta,bool head)165 static void ath12k_dp_tx_move_payload(struct sk_buff *skb,
166 unsigned long delta,
167 bool head)
168 {
169 unsigned long len = skb->len;
170
171 if (head) {
172 skb_push(skb, delta);
173 memmove(skb->data, skb->data + delta, len);
174 skb_trim(skb, len);
175 } else {
176 skb_put(skb, delta);
177 memmove(skb->data + delta, skb->data, len);
178 skb_pull(skb, delta);
179 }
180 }
181
ath12k_dp_tx_align_payload(struct ath12k_base * ab,struct sk_buff ** pskb)182 static int ath12k_dp_tx_align_payload(struct ath12k_base *ab,
183 struct sk_buff **pskb)
184 {
185 u32 iova_mask = ab->hw_params->iova_mask;
186 unsigned long offset, delta1, delta2;
187 struct sk_buff *skb2, *skb = *pskb;
188 unsigned int headroom = skb_headroom(skb);
189 int tailroom = skb_tailroom(skb);
190 int ret = 0;
191
192 offset = (unsigned long)skb->data & iova_mask;
193 delta1 = offset;
194 delta2 = iova_mask - offset + 1;
195
196 if (headroom >= delta1) {
197 ath12k_dp_tx_move_payload(skb, delta1, true);
198 } else if (tailroom >= delta2) {
199 ath12k_dp_tx_move_payload(skb, delta2, false);
200 } else {
201 skb2 = skb_realloc_headroom(skb, iova_mask);
202 if (!skb2) {
203 ret = -ENOMEM;
204 goto out;
205 }
206
207 dev_kfree_skb_any(skb);
208
209 offset = (unsigned long)skb2->data & iova_mask;
210 if (offset)
211 ath12k_dp_tx_move_payload(skb2, offset, true);
212 *pskb = skb2;
213 }
214
215 out:
216 return ret;
217 }
218
ath12k_dp_tx(struct ath12k * ar,struct ath12k_link_vif * arvif,struct sk_buff * skb)219 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_link_vif *arvif,
220 struct sk_buff *skb)
221 {
222 struct ath12k_base *ab = ar->ab;
223 struct ath12k_dp *dp = &ab->dp;
224 struct hal_tx_info ti = {0};
225 struct ath12k_tx_desc_info *tx_desc;
226 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
227 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb);
228 struct hal_tcl_data_cmd *hal_tcl_desc;
229 struct hal_tx_msdu_ext_desc *msg;
230 struct sk_buff *skb_ext_desc;
231 struct hal_srng *tcl_ring;
232 struct ieee80211_hdr *hdr = (void *)skb->data;
233 struct ath12k_vif *ahvif = arvif->ahvif;
234 struct dp_tx_ring *tx_ring;
235 u8 pool_id;
236 u8 hal_ring_id;
237 int ret;
238 u8 ring_selector, ring_map = 0;
239 bool tcl_ring_retry;
240 bool msdu_ext_desc = false;
241 bool add_htt_metadata = false;
242 u32 iova_mask = ab->hw_params->iova_mask;
243
244 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))
245 return -ESHUTDOWN;
246
247 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
248 !ieee80211_is_data(hdr->frame_control))
249 return -EOPNOTSUPP;
250
251 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1);
252
253 /* Let the default ring selection be based on current processor
254 * number, where one of the 3 tcl rings are selected based on
255 * the smp_processor_id(). In case that ring
256 * is full/busy, we resort to other available rings.
257 * If all rings are full, we drop the packet.
258 * TODO: Add throttling logic when all rings are full
259 */
260 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb);
261
262 tcl_ring_sel:
263 tcl_ring_retry = false;
264 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring;
265
266 ring_map |= BIT(ti.ring_id);
267 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id;
268
269 tx_ring = &dp->tx_ring[ti.ring_id];
270
271 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id);
272 if (!tx_desc)
273 return -ENOMEM;
274
275 ti.bank_id = arvif->bank_id;
276 ti.meta_data_flags = arvif->tcl_metadata;
277
278 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&
279 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) {
280 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) {
281 ti.encrypt_type =
282 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher);
283
284 if (ieee80211_has_protected(hdr->frame_control))
285 skb_put(skb, IEEE80211_CCMP_MIC_LEN);
286 } else {
287 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
288 }
289
290 msdu_ext_desc = true;
291 }
292
293 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb);
294 ti.addr_search_flags = arvif->hal_addr_search_flags;
295 ti.search_type = arvif->search_type;
296 ti.type = HAL_TCL_DESC_TYPE_BUFFER;
297 ti.pkt_offset = 0;
298 ti.lmac_id = ar->lmac_id;
299 ti.vdev_id = arvif->vdev_id;
300 ti.bss_ast_hash = arvif->ast_hash;
301 ti.bss_ast_idx = arvif->ast_idx;
302 ti.dscp_tid_tbl_idx = 0;
303
304 if (skb->ip_summed == CHECKSUM_PARTIAL &&
305 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) {
306 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) |
307 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) |
308 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) |
309 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) |
310 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN);
311 }
312
313 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE);
314
315 ti.tid = ath12k_dp_tx_get_tid(skb);
316
317 switch (ti.encap_type) {
318 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
319 ath12k_dp_tx_encap_nwifi(skb);
320 break;
321 case HAL_TCL_ENCAP_TYPE_RAW:
322 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) {
323 ret = -EINVAL;
324 goto fail_remove_tx_buf;
325 }
326 break;
327 case HAL_TCL_ENCAP_TYPE_ETHERNET:
328 /* no need to encap */
329 break;
330 case HAL_TCL_ENCAP_TYPE_802_3:
331 default:
332 /* TODO: Take care of other encap modes as well */
333 ret = -EINVAL;
334 atomic_inc(&ab->soc_stats.tx_err.misc_fail);
335 goto fail_remove_tx_buf;
336 }
337
338 if (iova_mask &&
339 (unsigned long)skb->data & iova_mask) {
340 ret = ath12k_dp_tx_align_payload(ab, &skb);
341 if (ret) {
342 ath12k_warn(ab, "failed to align TX buffer %d\n", ret);
343 /* don't bail out, give original buffer
344 * a chance even unaligned.
345 */
346 goto map;
347 }
348
349 /* hdr is pointing to a wrong place after alignment,
350 * so refresh it for later use.
351 */
352 hdr = (void *)skb->data;
353 }
354 map:
355 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
356 if (dma_mapping_error(ab->dev, ti.paddr)) {
357 atomic_inc(&ab->soc_stats.tx_err.misc_fail);
358 ath12k_warn(ab, "failed to DMA map data Tx buffer\n");
359 ret = -ENOMEM;
360 goto fail_remove_tx_buf;
361 }
362
363 if (!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) &&
364 !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) &&
365 !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) &&
366 ieee80211_has_protected(hdr->frame_control)) {
367 /* Add metadata for sw encrypted vlan group traffic */
368 add_htt_metadata = true;
369 msdu_ext_desc = true;
370 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW);
371 ti.meta_data_flags |= HTT_TCL_META_DATA_VALID_HTT;
372 ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW;
373 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
374 }
375
376 tx_desc->skb = skb;
377 tx_desc->mac_id = ar->pdev_idx;
378 ti.desc_id = tx_desc->desc_id;
379 ti.data_len = skb->len;
380 skb_cb->paddr = ti.paddr;
381 skb_cb->vif = ahvif->vif;
382 skb_cb->ar = ar;
383
384 if (msdu_ext_desc) {
385 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc));
386 if (!skb_ext_desc) {
387 ret = -ENOMEM;
388 goto fail_unmap_dma;
389 }
390
391 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc));
392 memset(skb_ext_desc->data, 0, skb_ext_desc->len);
393
394 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data;
395 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti);
396
397 if (add_htt_metadata) {
398 ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc);
399 if (ret < 0) {
400 ath12k_dbg(ab, ATH12K_DBG_DP_TX,
401 "Failed to add HTT meta data, dropping packet\n");
402 kfree_skb(skb_ext_desc);
403 goto fail_unmap_dma;
404 }
405 }
406
407 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data,
408 skb_ext_desc->len, DMA_TO_DEVICE);
409 ret = dma_mapping_error(ab->dev, ti.paddr);
410 if (ret) {
411 kfree_skb(skb_ext_desc);
412 goto fail_unmap_dma;
413 }
414
415 ti.data_len = skb_ext_desc->len;
416 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC;
417
418 skb_cb->paddr_ext_desc = ti.paddr;
419 }
420
421 hal_ring_id = tx_ring->tcl_data_ring.ring_id;
422 tcl_ring = &ab->hal.srng_list[hal_ring_id];
423
424 spin_lock_bh(&tcl_ring->lock);
425
426 ath12k_hal_srng_access_begin(ab, tcl_ring);
427
428 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring);
429 if (!hal_tcl_desc) {
430 /* NOTE: It is highly unlikely we'll be running out of tcl_ring
431 * desc because the desc is directly enqueued onto hw queue.
432 */
433 ath12k_hal_srng_access_end(ab, tcl_ring);
434 ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
435 spin_unlock_bh(&tcl_ring->lock);
436 ret = -ENOMEM;
437
438 /* Checking for available tcl descriptors in another ring in
439 * case of failure due to full tcl ring now, is better than
440 * checking this ring earlier for each pkt tx.
441 * Restart ring selection if some rings are not checked yet.
442 */
443 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) &&
444 ab->hw_params->tcl_ring_retry) {
445 tcl_ring_retry = true;
446 ring_selector++;
447 }
448
449 goto fail_unmap_dma;
450 }
451
452 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti);
453
454 ath12k_hal_srng_access_end(ab, tcl_ring);
455
456 spin_unlock_bh(&tcl_ring->lock);
457
458 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ",
459 skb->data, skb->len);
460
461 atomic_inc(&ar->dp.num_tx_pending);
462
463 return 0;
464
465 fail_unmap_dma:
466 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
467
468 if (skb_cb->paddr_ext_desc)
469 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
470 sizeof(struct hal_tx_msdu_ext_desc),
471 DMA_TO_DEVICE);
472
473 fail_remove_tx_buf:
474 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id);
475 if (tcl_ring_retry)
476 goto tcl_ring_sel;
477
478 return ret;
479 }
480
ath12k_dp_tx_free_txbuf(struct ath12k_base * ab,struct sk_buff * msdu,u8 mac_id,struct dp_tx_ring * tx_ring)481 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab,
482 struct sk_buff *msdu, u8 mac_id,
483 struct dp_tx_ring *tx_ring)
484 {
485 struct ath12k *ar;
486 struct ath12k_skb_cb *skb_cb;
487 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
488
489 skb_cb = ATH12K_SKB_CB(msdu);
490 ar = ab->pdevs[pdev_id].ar;
491
492 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
493 if (skb_cb->paddr_ext_desc)
494 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
495 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
496
497 ieee80211_free_txskb(ar->ah->hw, msdu);
498
499 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
500 wake_up(&ar->dp.tx_empty_waitq);
501 }
502
503 static void
ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base * ab,struct sk_buff * msdu,struct dp_tx_ring * tx_ring,struct ath12k_dp_htt_wbm_tx_status * ts)504 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab,
505 struct sk_buff *msdu,
506 struct dp_tx_ring *tx_ring,
507 struct ath12k_dp_htt_wbm_tx_status *ts)
508 {
509 struct ieee80211_tx_info *info;
510 struct ath12k_skb_cb *skb_cb;
511 struct ath12k *ar;
512
513 skb_cb = ATH12K_SKB_CB(msdu);
514 info = IEEE80211_SKB_CB(msdu);
515
516 ar = skb_cb->ar;
517
518 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
519 wake_up(&ar->dp.tx_empty_waitq);
520
521 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
522 if (skb_cb->paddr_ext_desc)
523 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
524 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
525
526 memset(&info->status, 0, sizeof(info->status));
527
528 if (ts->acked) {
529 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
530 info->flags |= IEEE80211_TX_STAT_ACK;
531 info->status.ack_signal = ts->ack_rssi;
532
533 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
534 ab->wmi_ab.svc_map))
535 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR;
536
537 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
538 } else {
539 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
540 }
541 }
542
543 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu);
544 }
545
546 static void
ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base * ab,void * desc,u8 mac_id,struct sk_buff * msdu,struct dp_tx_ring * tx_ring)547 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab,
548 void *desc, u8 mac_id,
549 struct sk_buff *msdu,
550 struct dp_tx_ring *tx_ring)
551 {
552 struct htt_tx_wbm_completion *status_desc;
553 struct ath12k_dp_htt_wbm_tx_status ts = {0};
554 enum hal_wbm_htt_tx_comp_status wbm_status;
555
556 status_desc = desc;
557
558 wbm_status = le32_get_bits(status_desc->info0,
559 HTT_TX_WBM_COMP_INFO0_STATUS);
560
561 switch (wbm_status) {
562 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
563 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
564 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
565 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
566 ts.ack_rssi = le32_get_bits(status_desc->info2,
567 HTT_TX_WBM_COMP_INFO2_ACK_RSSI);
568 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts);
569 break;
570 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
571 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
572 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring);
573 break;
574 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
575 /* This event is to be handled only when the driver decides to
576 * use WDS offload functionality.
577 */
578 break;
579 default:
580 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
581 break;
582 }
583 }
584
ath12k_dp_tx_complete_msdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)585 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar,
586 struct sk_buff *msdu,
587 struct hal_tx_status *ts)
588 {
589 struct ath12k_base *ab = ar->ab;
590 struct ath12k_hw *ah = ar->ah;
591 struct ieee80211_tx_info *info;
592 struct ath12k_skb_cb *skb_cb;
593
594 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
595 /* Must not happen */
596 return;
597 }
598
599 skb_cb = ATH12K_SKB_CB(msdu);
600
601 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
602 if (skb_cb->paddr_ext_desc)
603 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
604 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
605
606 rcu_read_lock();
607
608 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) {
609 ieee80211_free_txskb(ah->hw, msdu);
610 goto exit;
611 }
612
613 if (!skb_cb->vif) {
614 ieee80211_free_txskb(ah->hw, msdu);
615 goto exit;
616 }
617
618 info = IEEE80211_SKB_CB(msdu);
619 memset(&info->status, 0, sizeof(info->status));
620
621 /* skip tx rate update from ieee80211_status*/
622 info->status.rates[0].idx = -1;
623
624 switch (ts->status) {
625 case HAL_WBM_TQM_REL_REASON_FRAME_ACKED:
626 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
627 info->flags |= IEEE80211_TX_STAT_ACK;
628 info->status.ack_signal = ts->ack_rssi;
629
630 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
631 ab->wmi_ab.svc_map))
632 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR;
633
634 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
635 }
636 break;
637 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX:
638 if (info->flags & IEEE80211_TX_CTL_NO_ACK) {
639 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
640 break;
641 }
642 fallthrough;
643 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU:
644 case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD:
645 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES:
646 /* The failure status is due to internal firmware tx failure
647 * hence drop the frame; do not update the status of frame to
648 * the upper layer
649 */
650 ieee80211_free_txskb(ah->hw, msdu);
651 goto exit;
652 default:
653 ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n",
654 ts->status);
655 break;
656 }
657
658 /* NOTE: Tx rate status reporting. Tx completion status does not have
659 * necessary information (for example nss) to build the tx rate.
660 * Might end up reporting it out-of-band from HTT stats.
661 */
662
663 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu);
664
665 exit:
666 rcu_read_unlock();
667 }
668
ath12k_dp_tx_status_parse(struct ath12k_base * ab,struct hal_wbm_completion_ring_tx * desc,struct hal_tx_status * ts)669 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab,
670 struct hal_wbm_completion_ring_tx *desc,
671 struct hal_tx_status *ts)
672 {
673 ts->buf_rel_source =
674 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE);
675 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
676 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)
677 return;
678
679 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)
680 return;
681
682 ts->status = le32_get_bits(desc->info0,
683 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON);
684
685 ts->ppdu_id = le32_get_bits(desc->info1,
686 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER);
687 if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID)
688 ts->rate_stats = le32_to_cpu(desc->rate_stats.info0);
689 else
690 ts->rate_stats = 0;
691 }
692
ath12k_dp_tx_completion_handler(struct ath12k_base * ab,int ring_id)693 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id)
694 {
695 struct ath12k *ar;
696 struct ath12k_dp *dp = &ab->dp;
697 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
698 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
699 struct ath12k_tx_desc_info *tx_desc = NULL;
700 struct sk_buff *msdu;
701 struct hal_tx_status ts = { 0 };
702 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
703 struct hal_wbm_release_ring *desc;
704 u8 mac_id, pdev_id;
705 u64 desc_va;
706
707 spin_lock_bh(&status_ring->lock);
708
709 ath12k_hal_srng_access_begin(ab, status_ring);
710
711 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) {
712 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring);
713 if (!desc)
714 break;
715
716 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
717 desc, sizeof(*desc));
718 tx_ring->tx_status_head =
719 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head);
720 }
721
722 if (ath12k_hal_srng_dst_peek(ab, status_ring) &&
723 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) {
724 /* TODO: Process pending tx_status messages when kfifo_is_full() */
725 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
726 }
727
728 ath12k_hal_srng_access_end(ab, status_ring);
729
730 spin_unlock_bh(&status_ring->lock);
731
732 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
733 struct hal_wbm_completion_ring_tx *tx_status;
734 u32 desc_id;
735
736 tx_ring->tx_status_tail =
737 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
738 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
739 ath12k_dp_tx_status_parse(ab, tx_status, &ts);
740
741 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) {
742 /* HW done cookie conversion */
743 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 |
744 le32_to_cpu(tx_status->buf_va_lo));
745 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va);
746 } else {
747 /* SW does cookie conversion to VA */
748 desc_id = le32_get_bits(tx_status->buf_va_hi,
749 BUFFER_ADDR_INFO1_SW_COOKIE);
750
751 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id);
752 }
753 if (!tx_desc) {
754 ath12k_warn(ab, "unable to retrieve tx_desc!");
755 continue;
756 }
757
758 msdu = tx_desc->skb;
759 mac_id = tx_desc->mac_id;
760
761 /* Release descriptor as soon as extracting necessary info
762 * to reduce contention
763 */
764 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id);
765 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) {
766 ath12k_dp_tx_process_htt_tx_complete(ab,
767 (void *)tx_status,
768 mac_id, msdu,
769 tx_ring);
770 continue;
771 }
772
773 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
774 ar = ab->pdevs[pdev_id].ar;
775
776 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
777 wake_up(&ar->dp.tx_empty_waitq);
778
779 ath12k_dp_tx_complete_msdu(ar, msdu, &ts);
780 }
781 }
782
783 static int
ath12k_dp_tx_get_ring_id_type(struct ath12k_base * ab,int mac_id,u32 ring_id,enum hal_ring_type ring_type,enum htt_srng_ring_type * htt_ring_type,enum htt_srng_ring_id * htt_ring_id)784 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab,
785 int mac_id, u32 ring_id,
786 enum hal_ring_type ring_type,
787 enum htt_srng_ring_type *htt_ring_type,
788 enum htt_srng_ring_id *htt_ring_id)
789 {
790 int ret = 0;
791
792 switch (ring_type) {
793 case HAL_RXDMA_BUF:
794 /* for some targets, host fills rx buffer to fw and fw fills to
795 * rxbuf ring for each rxdma
796 */
797 if (!ab->hw_params->rx_mac_buf_ring) {
798 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 ||
799 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) {
800 ret = -EINVAL;
801 }
802 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
803 *htt_ring_type = HTT_SW_TO_HW_RING;
804 } else {
805 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) {
806 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
807 *htt_ring_type = HTT_SW_TO_SW_RING;
808 } else {
809 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
810 *htt_ring_type = HTT_SW_TO_HW_RING;
811 }
812 }
813 break;
814 case HAL_RXDMA_DST:
815 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
816 *htt_ring_type = HTT_HW_TO_SW_RING;
817 break;
818 case HAL_RXDMA_MONITOR_BUF:
819 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
820 *htt_ring_type = HTT_SW_TO_HW_RING;
821 break;
822 case HAL_RXDMA_MONITOR_STATUS:
823 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
824 *htt_ring_type = HTT_SW_TO_HW_RING;
825 break;
826 case HAL_RXDMA_MONITOR_DST:
827 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
828 *htt_ring_type = HTT_HW_TO_SW_RING;
829 break;
830 case HAL_RXDMA_MONITOR_DESC:
831 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
832 *htt_ring_type = HTT_SW_TO_HW_RING;
833 break;
834 default:
835 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
836 ret = -EINVAL;
837 }
838 return ret;
839 }
840
ath12k_dp_tx_htt_srng_setup(struct ath12k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type)841 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
842 int mac_id, enum hal_ring_type ring_type)
843 {
844 struct htt_srng_setup_cmd *cmd;
845 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
846 struct hal_srng_params params;
847 struct sk_buff *skb;
848 u32 ring_entry_sz;
849 int len = sizeof(*cmd);
850 dma_addr_t hp_addr, tp_addr;
851 enum htt_srng_ring_type htt_ring_type;
852 enum htt_srng_ring_id htt_ring_id;
853 int ret;
854
855 skb = ath12k_htc_alloc_skb(ab, len);
856 if (!skb)
857 return -ENOMEM;
858
859 memset(¶ms, 0, sizeof(params));
860 ath12k_hal_srng_get_params(ab, srng, ¶ms);
861
862 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);
863 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);
864
865 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
866 ring_type, &htt_ring_type,
867 &htt_ring_id);
868 if (ret)
869 goto err_free;
870
871 skb_put(skb, len);
872 cmd = (struct htt_srng_setup_cmd *)skb->data;
873 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP,
874 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE);
875 if (htt_ring_type == HTT_SW_TO_HW_RING ||
876 htt_ring_type == HTT_HW_TO_SW_RING)
877 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id),
878 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
879 else
880 cmd->info0 |= le32_encode_bits(mac_id,
881 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
882 cmd->info0 |= le32_encode_bits(htt_ring_type,
883 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE);
884 cmd->info0 |= le32_encode_bits(htt_ring_id,
885 HTT_SRNG_SETUP_CMD_INFO0_RING_ID);
886
887 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr &
888 HAL_ADDR_LSB_REG_MASK);
889
890 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >>
891 HAL_ADDR_MSB_REG_SHIFT);
892
893 ret = ath12k_hal_srng_get_entrysize(ab, ring_type);
894 if (ret < 0)
895 goto err_free;
896
897 ring_entry_sz = ret;
898
899 ring_entry_sz >>= 2;
900 cmd->info1 = le32_encode_bits(ring_entry_sz,
901 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE);
902 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz,
903 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE);
904 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
905 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP);
906 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
907 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP);
908 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP),
909 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP);
910 if (htt_ring_type == HTT_SW_TO_HW_RING)
911 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS);
912
913 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr));
914 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr));
915
916 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr));
917 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr));
918
919 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr));
920 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr));
921 cmd->msi_data = cpu_to_le32(params.msi_data);
922
923 cmd->intr_info =
924 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz,
925 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH);
926 cmd->intr_info |=
927 le32_encode_bits(params.intr_timer_thres_us >> 3,
928 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH);
929
930 cmd->info2 = 0;
931 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
932 cmd->info2 = le32_encode_bits(params.low_threshold,
933 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH);
934 }
935
936 ath12k_dbg(ab, ATH12K_DBG_HAL,
937 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
938 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
939 cmd->msi_data);
940
941 ath12k_dbg(ab, ATH12K_DBG_HAL,
942 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
943 ring_id, ring_type, cmd->intr_info, cmd->info2);
944
945 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
946 if (ret)
947 goto err_free;
948
949 return 0;
950
951 err_free:
952 dev_kfree_skb_any(skb);
953
954 return ret;
955 }
956
957 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
958
ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base * ab)959 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab)
960 {
961 struct ath12k_dp *dp = &ab->dp;
962 struct sk_buff *skb;
963 struct htt_ver_req_cmd *cmd;
964 int len = sizeof(*cmd);
965 int ret;
966
967 init_completion(&dp->htt_tgt_version_received);
968
969 skb = ath12k_htc_alloc_skb(ab, len);
970 if (!skb)
971 return -ENOMEM;
972
973 skb_put(skb, len);
974 cmd = (struct htt_ver_req_cmd *)skb->data;
975 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ,
976 HTT_VER_REQ_INFO_MSG_ID);
977
978 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
979 if (ret) {
980 dev_kfree_skb_any(skb);
981 return ret;
982 }
983
984 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
985 HTT_TARGET_VERSION_TIMEOUT_HZ);
986 if (ret == 0) {
987 ath12k_warn(ab, "htt target version request timed out\n");
988 return -ETIMEDOUT;
989 }
990
991 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
992 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n",
993 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
994 return -EOPNOTSUPP;
995 }
996
997 return 0;
998 }
999
ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k * ar,u32 mask)1000 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask)
1001 {
1002 struct ath12k_base *ab = ar->ab;
1003 struct ath12k_dp *dp = &ab->dp;
1004 struct sk_buff *skb;
1005 struct htt_ppdu_stats_cfg_cmd *cmd;
1006 int len = sizeof(*cmd);
1007 u8 pdev_mask;
1008 int ret;
1009 int i;
1010
1011 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
1012 skb = ath12k_htc_alloc_skb(ab, len);
1013 if (!skb)
1014 return -ENOMEM;
1015
1016 skb_put(skb, len);
1017 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
1018 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG,
1019 HTT_PPDU_STATS_CFG_MSG_TYPE);
1020
1021 pdev_mask = 1 << (i + 1);
1022 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID);
1023 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK);
1024
1025 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
1026 if (ret) {
1027 dev_kfree_skb_any(skb);
1028 return ret;
1029 }
1030 }
1031
1032 return 0;
1033 }
1034
ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type,int rx_buf_size,struct htt_rx_ring_tlv_filter * tlv_filter)1035 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
1036 int mac_id, enum hal_ring_type ring_type,
1037 int rx_buf_size,
1038 struct htt_rx_ring_tlv_filter *tlv_filter)
1039 {
1040 struct htt_rx_ring_selection_cfg_cmd *cmd;
1041 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1042 struct hal_srng_params params;
1043 struct sk_buff *skb;
1044 int len = sizeof(*cmd);
1045 enum htt_srng_ring_type htt_ring_type;
1046 enum htt_srng_ring_id htt_ring_id;
1047 int ret;
1048
1049 skb = ath12k_htc_alloc_skb(ab, len);
1050 if (!skb)
1051 return -ENOMEM;
1052
1053 memset(¶ms, 0, sizeof(params));
1054 ath12k_hal_srng_get_params(ab, srng, ¶ms);
1055
1056 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1057 ring_type, &htt_ring_type,
1058 &htt_ring_id);
1059 if (ret)
1060 goto err_free;
1061
1062 skb_put(skb, len);
1063 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
1064 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG,
1065 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
1066 if (htt_ring_type == HTT_SW_TO_HW_RING ||
1067 htt_ring_type == HTT_HW_TO_SW_RING)
1068 cmd->info0 |=
1069 le32_encode_bits(DP_SW2HW_MACID(mac_id),
1070 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1071 else
1072 cmd->info0 |=
1073 le32_encode_bits(mac_id,
1074 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1075 cmd->info0 |= le32_encode_bits(htt_ring_id,
1076 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
1077 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
1078 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS);
1079 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
1080 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS);
1081 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid,
1082 HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID);
1083 cmd->info1 = le32_encode_bits(rx_buf_size,
1084 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE);
1085 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0);
1086 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1);
1087 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2);
1088 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3);
1089 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter);
1090
1091 if (tlv_filter->offset_valid) {
1092 cmd->rx_packet_offset =
1093 le32_encode_bits(tlv_filter->rx_packet_offset,
1094 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET);
1095
1096 cmd->rx_packet_offset |=
1097 le32_encode_bits(tlv_filter->rx_header_offset,
1098 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET);
1099
1100 cmd->rx_mpdu_offset =
1101 le32_encode_bits(tlv_filter->rx_mpdu_end_offset,
1102 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET);
1103
1104 cmd->rx_mpdu_offset |=
1105 le32_encode_bits(tlv_filter->rx_mpdu_start_offset,
1106 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET);
1107
1108 cmd->rx_msdu_offset =
1109 le32_encode_bits(tlv_filter->rx_msdu_end_offset,
1110 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET);
1111
1112 cmd->rx_msdu_offset |=
1113 le32_encode_bits(tlv_filter->rx_msdu_start_offset,
1114 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET);
1115
1116 cmd->rx_attn_offset =
1117 le32_encode_bits(tlv_filter->rx_attn_offset,
1118 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET);
1119 }
1120
1121 if (tlv_filter->rx_mpdu_start_wmask > 0 &&
1122 tlv_filter->rx_msdu_end_wmask > 0) {
1123 cmd->info2 |=
1124 le32_encode_bits(true,
1125 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET);
1126 cmd->rx_mpdu_start_end_mask =
1127 le32_encode_bits(tlv_filter->rx_mpdu_start_wmask,
1128 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK);
1129 /* mpdu_end is not used for any hardwares so far
1130 * please assign it in future if any chip is
1131 * using through hal ops
1132 */
1133 cmd->rx_mpdu_start_end_mask |=
1134 le32_encode_bits(tlv_filter->rx_mpdu_end_wmask,
1135 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK);
1136 cmd->rx_msdu_end_word_mask =
1137 le32_encode_bits(tlv_filter->rx_msdu_end_wmask,
1138 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK);
1139 }
1140
1141 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
1142 if (ret)
1143 goto err_free;
1144
1145 return 0;
1146
1147 err_free:
1148 dev_kfree_skb_any(skb);
1149
1150 return ret;
1151 }
1152
1153 int
ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k * ar,u8 type,struct htt_ext_stats_cfg_params * cfg_params,u64 cookie)1154 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,
1155 struct htt_ext_stats_cfg_params *cfg_params,
1156 u64 cookie)
1157 {
1158 struct ath12k_base *ab = ar->ab;
1159 struct ath12k_dp *dp = &ab->dp;
1160 struct sk_buff *skb;
1161 struct htt_ext_stats_cfg_cmd *cmd;
1162 int len = sizeof(*cmd);
1163 int ret;
1164 u32 pdev_id;
1165
1166 skb = ath12k_htc_alloc_skb(ab, len);
1167 if (!skb)
1168 return -ENOMEM;
1169
1170 skb_put(skb, len);
1171
1172 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
1173 memset(cmd, 0, sizeof(*cmd));
1174 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
1175
1176 pdev_id = ath12k_mac_get_target_pdev_id(ar);
1177 cmd->hdr.pdev_mask = 1 << pdev_id;
1178
1179 cmd->hdr.stats_type = type;
1180 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0);
1181 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1);
1182 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2);
1183 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3);
1184 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie));
1185 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie));
1186
1187 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
1188 if (ret) {
1189 ath12k_warn(ab, "failed to send htt type stats request: %d",
1190 ret);
1191 dev_kfree_skb_any(skb);
1192 return ret;
1193 }
1194
1195 return 0;
1196 }
1197
ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k * ar,bool reset)1198 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset)
1199 {
1200 struct ath12k_base *ab = ar->ab;
1201 int ret;
1202
1203 ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset);
1204 if (ret) {
1205 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret);
1206 return ret;
1207 }
1208
1209 return 0;
1210 }
1211
ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k * ar,bool reset)1212 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
1213 {
1214 struct ath12k_base *ab = ar->ab;
1215 struct ath12k_dp *dp = &ab->dp;
1216 struct htt_rx_ring_tlv_filter tlv_filter = {0};
1217 int ret, ring_id;
1218
1219 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
1220 tlv_filter.offset_valid = false;
1221
1222 if (!reset) {
1223 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
1224 tlv_filter.pkt_filter_flags0 =
1225 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
1226 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
1227 tlv_filter.pkt_filter_flags1 =
1228 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
1229 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
1230 tlv_filter.pkt_filter_flags2 =
1231 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
1232 HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
1233 tlv_filter.pkt_filter_flags3 =
1234 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
1235 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
1236 HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
1237 HTT_RX_MON_MO_DATA_FILTER_FLASG3;
1238 }
1239
1240 if (ab->hw_params->rxdma1_enable) {
1241 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0,
1242 HAL_RXDMA_MONITOR_BUF,
1243 DP_RXDMA_REFILL_RING_SIZE,
1244 &tlv_filter);
1245 if (ret) {
1246 ath12k_err(ab,
1247 "failed to setup filter for monitor buf %d\n", ret);
1248 return ret;
1249 }
1250 }
1251
1252 return 0;
1253 }
1254
ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type,int tx_buf_size,struct htt_tx_ring_tlv_filter * htt_tlv_filter)1255 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,
1256 int mac_id, enum hal_ring_type ring_type,
1257 int tx_buf_size,
1258 struct htt_tx_ring_tlv_filter *htt_tlv_filter)
1259 {
1260 struct htt_tx_ring_selection_cfg_cmd *cmd;
1261 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1262 struct hal_srng_params params;
1263 struct sk_buff *skb;
1264 int len = sizeof(*cmd);
1265 enum htt_srng_ring_type htt_ring_type;
1266 enum htt_srng_ring_id htt_ring_id;
1267 int ret;
1268
1269 skb = ath12k_htc_alloc_skb(ab, len);
1270 if (!skb)
1271 return -ENOMEM;
1272
1273 memset(¶ms, 0, sizeof(params));
1274 ath12k_hal_srng_get_params(ab, srng, ¶ms);
1275
1276 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1277 ring_type, &htt_ring_type,
1278 &htt_ring_id);
1279
1280 if (ret)
1281 goto err_free;
1282
1283 skb_put(skb, len);
1284 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data;
1285 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG,
1286 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
1287 if (htt_ring_type == HTT_SW_TO_HW_RING ||
1288 htt_ring_type == HTT_HW_TO_SW_RING)
1289 cmd->info0 |=
1290 le32_encode_bits(DP_SW2HW_MACID(mac_id),
1291 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1292 else
1293 cmd->info0 |=
1294 le32_encode_bits(mac_id,
1295 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1296 cmd->info0 |= le32_encode_bits(htt_ring_id,
1297 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
1298 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
1299 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS);
1300 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
1301 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS);
1302
1303 cmd->info1 |=
1304 le32_encode_bits(tx_buf_size,
1305 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE);
1306
1307 if (htt_tlv_filter->tx_mon_mgmt_filter) {
1308 cmd->info1 |=
1309 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
1310 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1311 cmd->info1 |=
1312 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1313 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
1314 cmd->info2 |=
1315 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
1316 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1317 }
1318
1319 if (htt_tlv_filter->tx_mon_data_filter) {
1320 cmd->info1 |=
1321 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
1322 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1323 cmd->info1 |=
1324 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1325 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
1326 cmd->info2 |=
1327 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
1328 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1329 }
1330
1331 if (htt_tlv_filter->tx_mon_ctrl_filter) {
1332 cmd->info1 |=
1333 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
1334 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1335 cmd->info1 |=
1336 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1337 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
1338 cmd->info2 |=
1339 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
1340 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1341 }
1342
1343 cmd->tlv_filter_mask_in0 =
1344 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags);
1345 cmd->tlv_filter_mask_in1 =
1346 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0);
1347 cmd->tlv_filter_mask_in2 =
1348 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1);
1349 cmd->tlv_filter_mask_in3 =
1350 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2);
1351
1352 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
1353 if (ret)
1354 goto err_free;
1355
1356 return 0;
1357
1358 err_free:
1359 dev_kfree_skb_any(skb);
1360 return ret;
1361 }
1362